rggen 0.26.0 → 0.27.0

checksums.yaml

@@ -1,7 +1,7 @@
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data/README.md

@@ -11,17 +11,23 @@
 
 # RgGen
 
-RgGen is a code generation tool for ASIC/IP/FPGA/RTL engineers. It will automatically generate soruce code related to configuration and status registers (CSR), e.g. SytemVerilog RTL, UVM register model (UVM RAL), Wiki documents, from human readable register map specifications.
+RgGen is a code generation tool for ASIC/IP/FPGA/RTL engineers. It will automatically generate soruce code related to configuration and status registers (CSR), e.g. SytemVerilog RTL, UVM register model (UVM RAL/uvm_reg), C header file, Wiki documents, from human readable register map specifications.
 
 RgGen has following features:
 
 * Generate source files related to CSR from register map specifications
-    * SystemVerilog RTL
-    * Verilog RTL
-        * Need [rggen-verilog](https://github.com/rggen/rggen-verilog) plugin
-    * VHDL RTL
-        * Need [rggen-vhdl](https://github.com/rggen/rggen-vhdl) plugin
-    * UVM register model (UVM RAL)
+    * RTL module
+        * SystemVerilog
+        * Verilog
+            * Need [rggen-verilog](https://github.com/rggen/rggen-verilog) plugin
+        * VHDL
+            * Need [rggen-vhdl](https://github.com/rggen/rggen-vhdl) plugin
+        * Supports standard bus protocols
+            * AMBA APB
+            * AMBA AXI4-Lite
+            * Wishbone
+    * UVM register model (UVM RAL/uvm_reg)
+    * C header file
     * Register map documents written in Markdown
 * Register map specifications can be written in human readable format
     * Ruby with APIs to describe register map information
@@ -47,6 +53,7 @@ RgGen depends on following sub components and other Ruby libraries.
 * [rggen-core](https://github.com/rggen/rggen-core)
 * [rggen-default-register-map](https://github.com/rggen/rggen-default-register-map)
 * [rggen-systemverilog](https://github.com/rggen/rggen-systemverilog)
+* [rggen-c-header](https://github.com/rggen/rggen-c-header)
 * [rggen-markdown](https://github.com/rggen/rggen-markdown)
 * [rggen-spreadsheet-loader](https://github.com/rggen/rggen-spreadsheet-loader)
 
@@ -92,8 +99,6 @@ Following EDA tools can accept the generated source files.
     * Synopsys VCS
     * Cadence Xcelium
     * Xilinx Vivado Simulator
-        * Confirmed RTL only
-        * Not sure if UVM register models are accepted
     * Verilator
         * Need `-Wno-fatal` switch
     * Icarus Verilog
@@ -107,7 +112,7 @@ Following EDA tools can accept the generated source files.
 
 ## Example
 
-You can get example configuration file and register map specification listed below:
+You can get an example configuration file and register map specifications listed below:
 
 * Configuration file
     * https://github.com/rggen/rggen-sample/blob/master/config.yml
@@ -115,7 +120,7 @@ You can get example configuration file and register map specification listed bel
     * https://github.com/rggen/rggen-sample/blob/master/block_0.yml
     * https://github.com/rggen/rggen-sample/blob/master/block_1.yml
 
-By using these example files, you can try to use RgGen. Hit command below:
+You can try to use RgGen by uisng these example files. Hit command below:
 
 ```
 $ rggen -c config.yml -o out block_0.yml block_1.yml
@@ -132,6 +137,9 @@ Then, generated files listed below will be written to `out` directory.
 * UVM register model
     * https://github.com/rggen/rggen-sample/blob/master/block_0_ral_pkg.sv
     * https://github.com/rggen/rggen-sample/blob/master/block_1_ral_pkg.sv
+* C header file
+    * https://github.com/rggen/rggen-sample/blob/master/block_0.h
+    * https://github.com/rggen/rggen-sample/blob/master/block_1.h
 * Markdown document
     * https://github.com/rggen/rggen-sample/blob/master/block_0.md
     * https://github.com/rggen/rggen-sample/blob/master/block_1.md
@@ -155,6 +163,7 @@ Feedbacks, bug reports, questions and etc. are wellcome! You can post them by us
 * https://github.com/rggen/rggen-core
 * https://github.com/rggen/rggen-default-register-map
 * https://github.com/rggen/rggen-systemverilog
+* https://github.com/rggen/rggen-c-header
 * https://github.com/rggen/rggen-markdown
 * https://github.com/rggen/rggen-spreadsheet-loader
 * https://github.com/rggen/rggen-duh

data/lib/rggen/{setup.rb → default.rb}

@@ -3,5 +3,6 @@
 RgGen.load_plugin 'rggen-default-register-map'
 RgGen.load_plugin 'rggen-systemverilog/rtl'
 RgGen.load_plugin 'rggen-systemverilog/ral'
+RgGen.load_plugin 'rggen-c-header'
 RgGen.load_plugin 'rggen-markdown'
 RgGen.load_plugin 'rggen-spreadsheet-loader'

data/lib/rggen/version.rb

@@ -1,5 +1,5 @@
 # frozen_string_literal: true
 
 module RgGen
-  VERSION = '0.26.0'
+  VERSION = '0.27.0'
 end

metadata

@@ -1,85 +1,99 @@
 --- !ruby/object:Gem::Specification
 name: rggen
 version: !ruby/object:Gem::Version
-  version: 0.26.0
+  version: 0.27.0
 platform: ruby
 authors:
 - Taichi Ishitani
 autorequire: 
 bindir: bin
 cert_chain: []
-date: 2022-03-25 00:00:00.000000000 Z
+date: 2022-07-05 00:00:00.000000000 Z
 dependencies:
+- !ruby/object:Gem::Dependency
+  name: rggen-c-header
+  requirement: !ruby/object:Gem::Requirement
+    requirements:
+    - - "~>"
+      - !ruby/object:Gem::Version
+        version: 0.2.0
+  type: :runtime
+  prerelease: false
+  version_requirements: !ruby/object:Gem::Requirement
+    requirements:
+    - - "~>"
+      - !ruby/object:Gem::Version
+        version: 0.2.0
 - !ruby/object:Gem::Dependency
   name: rggen-core
   requirement: !ruby/object:Gem::Requirement
     requirements:
     - - "~>"
       - !ruby/object:Gem::Version
-        version: 0.26.0
+        version: 0.27.0
   type: :runtime
   prerelease: false
   version_requirements: !ruby/object:Gem::Requirement
     requirements:
     - - "~>"
       - !ruby/object:Gem::Version
-        version: 0.26.0
+        version: 0.27.0
 - !ruby/object:Gem::Dependency
   name: rggen-default-register-map
   requirement: !ruby/object:Gem::Requirement
     requirements:
     - - "~>"
       - !ruby/object:Gem::Version
-        version: 0.26.0
+        version: 0.27.0
   type: :runtime
   prerelease: false
   version_requirements: !ruby/object:Gem::Requirement
     requirements:
     - - "~>"
       - !ruby/object:Gem::Version
-        version: 0.26.0
+        version: 0.27.0
 - !ruby/object:Gem::Dependency
   name: rggen-markdown
   requirement: !ruby/object:Gem::Requirement
     requirements:
     - - "~>"
       - !ruby/object:Gem::Version
-        version: 0.22.0
+        version: 0.23.0
   type: :runtime
   prerelease: false
   version_requirements: !ruby/object:Gem::Requirement
     requirements:
     - - "~>"
       - !ruby/object:Gem::Version
-        version: 0.22.0
+        version: 0.23.0
 - !ruby/object:Gem::Dependency
   name: rggen-spreadsheet-loader
   requirement: !ruby/object:Gem::Requirement
     requirements:
     - - "~>"
       - !ruby/object:Gem::Version
-        version: 0.21.0
+        version: 0.22.0
   type: :runtime
   prerelease: false
   version_requirements: !ruby/object:Gem::Requirement
     requirements:
     - - "~>"
       - !ruby/object:Gem::Version
-        version: 0.21.0
+        version: 0.22.0
 - !ruby/object:Gem::Dependency
   name: rggen-systemverilog
   requirement: !ruby/object:Gem::Requirement
     requirements:
     - - "~>"
       - !ruby/object:Gem::Version
-        version: 0.26.0
+        version: 0.27.0
   type: :runtime
   prerelease: false
   version_requirements: !ruby/object:Gem::Requirement
     requirements:
     - - "~>"
       - !ruby/object:Gem::Version
-        version: 0.26.0
+        version: 0.27.0
 - !ruby/object:Gem::Dependency
   name: bundler
   requirement: !ruby/object:Gem::Requirement
@@ -109,7 +123,7 @@ files:
 - LICENSE
 - README.md
 - lib/rggen.rb
-- lib/rggen/setup.rb
+- lib/rggen/default.rb
 - lib/rggen/version.rb
 - logo/rggen.png
 homepage: https://github.com/rggen/rggen