rggen 0.25.3 → 0.26.2

checksums.yaml

@@ -1,7 +1,7 @@
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data/CONTRIBUTING.md

@@ -49,12 +49,12 @@ to fix the bug which you found or implement enhancements which you want.
 
 1. Create a working directory
 2. Clone your forked version of the repositories to the working directory
-3. Clone folloiwng repositories for development tools to the working directory
+3. Clone following repositories for development tools to the working directory
     * https://github.com/rggen/rggen-devtools
     * https://github.com/rggen/rggen-checkout
 4. Clone other RgGen's repositories
     * Invoke commnad below on to the working directory
-        * `./rggen-devtools/bin/checkout --list ./rggen-checkout/all.yml --dir .`
+        * `./rggen-devtools/bin/checkout.rb --list ./rggen-checkout/all.yml --dir .`
 
 ```
 $ mkdir work

data/LICENSE

@@ -1,6 +1,6 @@
 The MIT License (MIT)
 
-Copyright (c) 2019-2021 Taichi Ishitani
+Copyright (c) 2019-2022 Taichi Ishitani
 
 Permission is hereby granted, free of charge, to any person obtaining a copy
 of this software and associated documentation files (the "Software"), to deal

data/README.md

@@ -11,18 +11,25 @@
 
 # RgGen
 
-RgGen is a code generation tool for ASIC/IP/FPGA/RTL engineers. It will automatically generate soruce code related to configuration and status registers (CSR), e.g. SytemVerilog RTL, UVM register model (UVM RAL), Wiki documents, from human readable register map specifications.
+RgGen is a code generation tool for ASIC/IP/FPGA/RTL engineers. It will automatically generate soruce code related to configuration and status registers (CSR), e.g. SytemVerilog RTL, UVM register model (UVM RAL/uvm_reg), Wiki documents, from human readable register map specifications.
 
 RgGen has following features:
 
 * Generate source files related to CSR from register map specifications
-    * SystemVerilog RTL
-    * Verilog RTL
-        * Need [rggen-verilog](https://github.com/rggen/rggen-verilog) plugin
-    * VHDL RTL
-        * Need [rggen-vhdl](https://github.com/rggen/rggen-vhdl) plugin
-    * UVM register model (UVM RAL)
+    * RTL module
+        * SystemVerilog
+        * Verilog
+            * Need [rggen-verilog](https://github.com/rggen/rggen-verilog) plugin
+        * VHDL
+            * Need [rggen-vhdl](https://github.com/rggen/rggen-vhdl) plugin
+        * Supports standard bus protocols
+            * AMBA APB
+            * AMBA AXI4-Lite
+            * Wishbone
+    * UVM register model (UVM RAL/uvm_reg)
     * Register map documents written in Markdown
+    * C header file
+        * Need [rggen-c-header](https://github.com/rggen/rggen-c-header) plugin
 * Register map specifications can be written in human readable format
     * Ruby with APIs to describe register map information
     * YAML
@@ -31,14 +38,14 @@ RgGen has following features:
     * Spreadsheet (XLSX, XLS, OSD, CSV)
     * [SiFive DUH](https://github.com/sifive/duh)
         * Need [rggen-duh](https://github.com/rggen/rggen-duh) plugin
-* Costomize RgGen for you environment
+* Customize RgGen for you environment
     * E.g. add special bit field types
 
 ## Installation
 
 ### Ruby
 
-RgGen is written in the [Ruby](https://www.ruby-lang.org/en/about/) programing language and its required version is 2.5 or later. You need to install  any of these versions of Ruby before installing RgGen tool. To install Ruby, see [this page](https://www.ruby-lang.org/en/downloads/).
+RgGen is written in the [Ruby](https://www.ruby-lang.org/en/about/) programing language and its required version is 2.6 or later. You need to install  any of these versions of Ruby before installing RgGen tool. To install Ruby, see [this page](https://www.ruby-lang.org/en/downloads/).
 
 ### Installatin Command
 
@@ -92,14 +99,16 @@ Following EDA tools can accept the generated source files.
     * Synopsys VCS
     * Cadence Xcelium
     * Xilinx Vivado Simulator
-        * Confirmed RTL only
-        * Not sure if UVM register models are accepted
     * Verilator
         * Need `-Wno-fatal` switch
+    * Icarus Verilog
+        * Verilog RTL only
 * Synthesis tools
     * Synopsys Design Compiler
     * Intel Quartus
     * Xilinx Vivado
+    * [Yosys](http://www.clifford.at/yosys/)
+        * Verilog RTL
 
 ## Example
 
@@ -156,10 +165,11 @@ Feedbacks, bug reports, questions and etc. are wellcome! You can post them by us
 * https://github.com/rggen/rggen-duh
 * https://github.com/rggen/rggen-verilog
 * https://github.com/rggen/rggen-vhdl
+* https://github.com/rggen/rggen-c-header
 
 ## Copyright & License
 
-Copyright © 2019-2021 Taichi Ishitani. RgGen is licensed under the [MIT License](https://opensource.org/licenses/MIT), see [LICENSE](LICENSE) for futher detils.
+Copyright © 2019-2022 Taichi Ishitani. RgGen is licensed under the [MIT License](https://opensource.org/licenses/MIT), see [LICENSE](LICENSE) for futher detils.
 
 ## Code of Conduct
 

data/lib/rggen/version.rb

@@ -1,5 +1,5 @@
 # frozen_string_literal: true
 
 module RgGen
-  VERSION = '0.25.3'
+  VERSION = '0.26.2'
 end

metadata

@@ -1,14 +1,14 @@
 --- !ruby/object:Gem::Specification
 name: rggen
 version: !ruby/object:Gem::Version
-  version: 0.25.3
+  version: 0.26.2
 platform: ruby
 authors:
 - Taichi Ishitani
 autorequire: 
 bindir: bin
 cert_chain: []
-date: 2021-05-17 00:00:00.000000000 Z
+date: 2022-06-13 00:00:00.000000000 Z
 dependencies:
 - !ruby/object:Gem::Dependency
   name: rggen-core
@@ -16,70 +16,70 @@ dependencies:
     requirements:
     - - "~>"
       - !ruby/object:Gem::Version
-        version: 0.25.1
+        version: 0.26.0
   type: :runtime
   prerelease: false
   version_requirements: !ruby/object:Gem::Requirement
     requirements:
     - - "~>"
       - !ruby/object:Gem::Version
-        version: 0.25.1
+        version: 0.26.0
 - !ruby/object:Gem::Dependency
   name: rggen-default-register-map
   requirement: !ruby/object:Gem::Requirement
     requirements:
     - - "~>"
       - !ruby/object:Gem::Version
-        version: 0.25.1
+        version: 0.26.0
   type: :runtime
   prerelease: false
   version_requirements: !ruby/object:Gem::Requirement
     requirements:
     - - "~>"
       - !ruby/object:Gem::Version
-        version: 0.25.1
+        version: 0.26.0
 - !ruby/object:Gem::Dependency
   name: rggen-markdown
   requirement: !ruby/object:Gem::Requirement
     requirements:
     - - "~>"
       - !ruby/object:Gem::Version
-        version: 0.21.0
+        version: 0.22.0
   type: :runtime
   prerelease: false
   version_requirements: !ruby/object:Gem::Requirement
     requirements:
     - - "~>"
       - !ruby/object:Gem::Version
-        version: 0.21.0
+        version: 0.22.0
 - !ruby/object:Gem::Dependency
   name: rggen-spreadsheet-loader
   requirement: !ruby/object:Gem::Requirement
     requirements:
     - - "~>"
       - !ruby/object:Gem::Version
-        version: 0.20.0
+        version: 0.21.0
   type: :runtime
   prerelease: false
   version_requirements: !ruby/object:Gem::Requirement
     requirements:
     - - "~>"
       - !ruby/object:Gem::Version
-        version: 0.20.0
+        version: 0.21.0
 - !ruby/object:Gem::Dependency
   name: rggen-systemverilog
   requirement: !ruby/object:Gem::Requirement
     requirements:
     - - "~>"
       - !ruby/object:Gem::Version
-        version: 0.25.1
+        version: 0.26.1
   type: :runtime
   prerelease: false
   version_requirements: !ruby/object:Gem::Requirement
     requirements:
     - - "~>"
       - !ruby/object:Gem::Version
-        version: 0.25.1
+        version: 0.26.1
 - !ruby/object:Gem::Dependency
   name: bundler
   requirement: !ruby/object:Gem::Requirement
@@ -118,6 +118,7 @@ licenses:
 metadata:
   bug_tracker_uri: https://github.com/rggen/rggen/issues
   mailing_list_uri: https://groups.google.com/d/forum/rggen
+  rubygems_mfa_required: 'true'
   source_code_uri: https://github.com/rggen/rggen
   wiki_uri: https://github.com/rggen/rggen/wiki
 post_install_message: 
@@ -128,14 +129,14 @@ required_ruby_version: !ruby/object:Gem::Requirement
   requirements:
   - - ">="
     - !ruby/object:Gem::Version
-      version: '2.5'
+      version: '2.6'
 required_rubygems_version: !ruby/object:Gem::Requirement
   requirements:
   - - ">="
     - !ruby/object:Gem::Version
       version: '0'
 requirements: []
-rubygems_version: 3.2.3
+rubygems_version: 3.3.3
 signing_key: 
 specification_version: 4
 summary: Code generation tool for configuration and status registers