rggen 0.25.2 → 0.26.1

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data/CONTRIBUTING.md CHANGED
@@ -49,12 +49,12 @@ to fix the bug which you found or implement enhancements which you want.
49
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50
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  1. Create a working directory
51
51
  2. Clone your forked version of the repositories to the working directory
52
- 3. Clone folloiwng repositories for development tools to the working directory
52
+ 3. Clone following repositories for development tools to the working directory
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53
  * https://github.com/rggen/rggen-devtools
54
54
  * https://github.com/rggen/rggen-checkout
55
55
  4. Clone other RgGen's repositories
56
56
  * Invoke commnad below on to the working directory
57
- * `./rggen-devtools/bin/checkout --list ./rggen-checkout/all.yml --dir .`
57
+ * `./rggen-devtools/bin/checkout.rb --list ./rggen-checkout/all.yml --dir .`
58
58
 
59
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  ```
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60
  $ mkdir work
data/LICENSE CHANGED
@@ -1,6 +1,6 @@
1
1
  The MIT License (MIT)
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2
 
3
- Copyright (c) 2019-2021 Taichi Ishitani
3
+ Copyright (c) 2019-2022 Taichi Ishitani
4
4
 
5
5
  Permission is hereby granted, free of charge, to any person obtaining a copy
6
6
  of this software and associated documentation files (the "Software"), to deal
data/README.md CHANGED
@@ -11,17 +11,22 @@
11
11
 
12
12
  # RgGen
13
13
 
14
- RgGen is a code generation tool for ASIC/IP/FPGA/RTL engineers. It will automatically generate soruce code related to configuration and status registers (CSR), e.g. SytemVerilog RTL, UVM register model (UVM RAL), Wiki documents, from human readable register map specifications.
14
+ RgGen is a code generation tool for ASIC/IP/FPGA/RTL engineers. It will automatically generate soruce code related to configuration and status registers (CSR), e.g. SytemVerilog RTL, UVM register model (UVM RAL/uvm_reg), Wiki documents, from human readable register map specifications.
15
15
 
16
16
  RgGen has following features:
17
17
 
18
18
  * Generate source files related to CSR from register map specifications
19
- * SystemVerilog RTL
20
- * Verilog RTL
21
- * Need [rggen-verilog](https://github.com/rggen/rggen-verilog) plugin
22
- * VHDL RTL
23
- * Need [rggen-vhdl](https://github.com/rggen/rggen-vhdl) plugin
24
- * UVM register model (UVM RAL)
19
+ * RTL module
20
+ * SystemVerilog
21
+ * Verilog
22
+ * Need [rggen-verilog](https://github.com/rggen/rggen-verilog) plugin
23
+ * VHDL
24
+ * Need [rggen-vhdl](https://github.com/rggen/rggen-vhdl) plugin
25
+ * Supports standard bus protocols
26
+ * AMBA APB
27
+ * AMBA AXI4-Lite
28
+ * Wishbone
29
+ * UVM register model (UVM RAL/uvm_reg)
25
30
  * Register map documents written in Markdown
26
31
  * Register map specifications can be written in human readable format
27
32
  * Ruby with APIs to describe register map information
@@ -31,14 +36,14 @@ RgGen has following features:
31
36
  * Spreadsheet (XLSX, XLS, OSD, CSV)
32
37
  * [SiFive DUH](https://github.com/sifive/duh)
33
38
  * Need [rggen-duh](https://github.com/rggen/rggen-duh) plugin
34
- * Costomize RgGen for you environment
39
+ * Customize RgGen for you environment
35
40
  * E.g. add special bit field types
36
41
 
37
42
  ## Installation
38
43
 
39
44
  ### Ruby
40
45
 
41
- RgGen is written in the [Ruby](https://www.ruby-lang.org/en/about/) programing language and its required version is 2.5 or later. You need to install any of these versions of Ruby before installing RgGen tool. To install Ruby, see [this page](https://www.ruby-lang.org/en/downloads/).
46
+ RgGen is written in the [Ruby](https://www.ruby-lang.org/en/about/) programing language and its required version is 2.6 or later. You need to install any of these versions of Ruby before installing RgGen tool. To install Ruby, see [this page](https://www.ruby-lang.org/en/downloads/).
42
47
 
43
48
  ### Installatin Command
44
49
 
@@ -92,14 +97,16 @@ Following EDA tools can accept the generated source files.
92
97
  * Synopsys VCS
93
98
  * Cadence Xcelium
94
99
  * Xilinx Vivado Simulator
95
- * Confirmed RTL only
96
- * Not sure if UVM register models are accepted
97
100
  * Verilator
98
101
  * Need `-Wno-fatal` switch
102
+ * Icarus Verilog
103
+ * Verilog RTL only
99
104
  * Synthesis tools
100
105
  * Synopsys Design Compiler
101
106
  * Intel Quartus
102
107
  * Xilinx Vivado
108
+ * [Yosys](http://www.clifford.at/yosys/)
109
+ * Verilog RTL
103
110
 
104
111
  ## Example
105
112
 
@@ -159,7 +166,7 @@ Feedbacks, bug reports, questions and etc. are wellcome! You can post them by us
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  ## Copyright & License
161
168
 
162
- Copyright © 2019-2021 Taichi Ishitani. RgGen is licensed under the [MIT License](https://opensource.org/licenses/MIT), see [LICENSE](LICENSE) for futher detils.
169
+ Copyright © 2019-2022 Taichi Ishitani. RgGen is licensed under the [MIT License](https://opensource.org/licenses/MIT), see [LICENSE](LICENSE) for futher detils.
163
170
 
164
171
  ## Code of Conduct
165
172
 
data/lib/rggen/version.rb CHANGED
@@ -1,5 +1,5 @@
1
1
  # frozen_string_literal: true
2
2
 
3
3
  module RgGen
4
- VERSION = '0.25.2'
4
+ VERSION = '0.26.1'
5
5
  end
metadata CHANGED
@@ -1,14 +1,14 @@
1
1
  --- !ruby/object:Gem::Specification
2
2
  name: rggen
3
3
  version: !ruby/object:Gem::Version
4
- version: 0.25.2
4
+ version: 0.26.1
5
5
  platform: ruby
6
6
  authors:
7
7
  - Taichi Ishitani
8
8
  autorequire:
9
9
  bindir: bin
10
10
  cert_chain: []
11
- date: 2021-05-16 00:00:00.000000000 Z
11
+ date: 2022-06-07 00:00:00.000000000 Z
12
12
  dependencies:
13
13
  - !ruby/object:Gem::Dependency
14
14
  name: rggen-core
@@ -16,70 +16,70 @@ dependencies:
16
16
  requirements:
17
17
  - - "~>"
18
18
  - !ruby/object:Gem::Version
19
- version: 0.25.0
19
+ version: 0.26.0
20
20
  type: :runtime
21
21
  prerelease: false
22
22
  version_requirements: !ruby/object:Gem::Requirement
23
23
  requirements:
24
24
  - - "~>"
25
25
  - !ruby/object:Gem::Version
26
- version: 0.25.0
26
+ version: 0.26.0
27
27
  - !ruby/object:Gem::Dependency
28
28
  name: rggen-default-register-map
29
29
  requirement: !ruby/object:Gem::Requirement
30
30
  requirements:
31
31
  - - "~>"
32
32
  - !ruby/object:Gem::Version
33
- version: 0.25.1
33
+ version: 0.26.0
34
34
  type: :runtime
35
35
  prerelease: false
36
36
  version_requirements: !ruby/object:Gem::Requirement
37
37
  requirements:
38
38
  - - "~>"
39
39
  - !ruby/object:Gem::Version
40
- version: 0.25.1
40
+ version: 0.26.0
41
41
  - !ruby/object:Gem::Dependency
42
42
  name: rggen-markdown
43
43
  requirement: !ruby/object:Gem::Requirement
44
44
  requirements:
45
45
  - - "~>"
46
46
  - !ruby/object:Gem::Version
47
- version: 0.21.0
47
+ version: 0.22.0
48
48
  type: :runtime
49
49
  prerelease: false
50
50
  version_requirements: !ruby/object:Gem::Requirement
51
51
  requirements:
52
52
  - - "~>"
53
53
  - !ruby/object:Gem::Version
54
- version: 0.21.0
54
+ version: 0.22.0
55
55
  - !ruby/object:Gem::Dependency
56
56
  name: rggen-spreadsheet-loader
57
57
  requirement: !ruby/object:Gem::Requirement
58
58
  requirements:
59
59
  - - "~>"
60
60
  - !ruby/object:Gem::Version
61
- version: 0.20.0
61
+ version: 0.21.0
62
62
  type: :runtime
63
63
  prerelease: false
64
64
  version_requirements: !ruby/object:Gem::Requirement
65
65
  requirements:
66
66
  - - "~>"
67
67
  - !ruby/object:Gem::Version
68
- version: 0.20.0
68
+ version: 0.21.0
69
69
  - !ruby/object:Gem::Dependency
70
70
  name: rggen-systemverilog
71
71
  requirement: !ruby/object:Gem::Requirement
72
72
  requirements:
73
73
  - - "~>"
74
74
  - !ruby/object:Gem::Version
75
- version: 0.25.1
75
+ version: 0.26.1
76
76
  type: :runtime
77
77
  prerelease: false
78
78
  version_requirements: !ruby/object:Gem::Requirement
79
79
  requirements:
80
80
  - - "~>"
81
81
  - !ruby/object:Gem::Version
82
- version: 0.25.1
82
+ version: 0.26.1
83
83
  - !ruby/object:Gem::Dependency
84
84
  name: bundler
85
85
  requirement: !ruby/object:Gem::Requirement
@@ -118,6 +118,7 @@ licenses:
118
118
  metadata:
119
119
  bug_tracker_uri: https://github.com/rggen/rggen/issues
120
120
  mailing_list_uri: https://groups.google.com/d/forum/rggen
121
+ rubygems_mfa_required: 'true'
121
122
  source_code_uri: https://github.com/rggen/rggen
122
123
  wiki_uri: https://github.com/rggen/rggen/wiki
123
124
  post_install_message:
@@ -128,14 +129,14 @@ required_ruby_version: !ruby/object:Gem::Requirement
128
129
  requirements:
129
130
  - - ">="
130
131
  - !ruby/object:Gem::Version
131
- version: '2.5'
132
+ version: '2.6'
132
133
  required_rubygems_version: !ruby/object:Gem::Requirement
133
134
  requirements:
134
135
  - - ">="
135
136
  - !ruby/object:Gem::Version
136
137
  version: '0'
137
138
  requirements: []
138
- rubygems_version: 3.2.3
139
+ rubygems_version: 3.3.3
139
140
  signing_key:
140
141
  specification_version: 4
141
142
  summary: Code generation tool for configuration and status registers