rggen 0.23.0 → 0.25.1

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Files changed (6) hide show
  1. checksums.yaml +4 -4
  2. data/CONTRIBUTING.md +66 -0
  3. data/LICENSE +1 -1
  4. data/README.md +26 -18
  5. data/lib/rggen/version.rb +1 -1
  6. metadata +15 -14
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data/CONTRIBUTING.md ADDED
@@ -0,0 +1,66 @@
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+ # Contributing
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+
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+ Your contributions are welcome!
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+
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+ ## Bug Report
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+
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+ You can submit bug reports on [GitHub Issue Tracker](https://github.com/rggen/rggen/issues).
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+ Please include information below in your report:
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+
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+ * How to reproduce the bug which you found
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+ * test code
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+ * command
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+ * Information about your environment
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+ * Ruby/RgGen version
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+ * OS
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+ * etc.
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+ * Expected result
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+
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+ ## Question
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+
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+ Questions are accepted on following channels:
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+
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+ * [GitHub Discussions](https://github.com/rggen/rggen/discussions)
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+ * [GitHub Issue Tracker](https://github.com/rggen/rggen/issues)
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+ * [Gitter Chat Room](https://gitter.im/rggen/rggen)
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+
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+ ## Enhancement Request
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+
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+ You can submit your enhancement request on [GitHub Issue Tracker](https://github.com/rggen/rggen/issues).
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+
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+ ## Pull Request
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+
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+ You can also submit pull requests on [GitHub Issue Tracker](https://github.com/rggen/rggen/pulls)
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+ to fix the bug which you found or implement enhancements which you want.
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+
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+ 1. Fork the repositories which you will change
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+ 2. Setup your working environment
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+ * See the next section
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+ 3. Add your change to the repositories
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+ * You need to add RSpec exmaples if you add new features
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+ * You need to make sure all existing RSpec examples pass
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+ * Invoke `rake spec` on the repositry root
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+ 4. Make sure all existing RSpec exmaples for other repositories pass
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+ * Invoke command below on the working directory
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+ * `./rggen-devtools/bin/run_all_spec.rb`
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+ 5. Commit your changes and submit a pull request
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+
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+ ### Setup Working Environment
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+
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+ 1. Create a working directory
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+ 2. Clone your forked version of the repositories to the working directory
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+ 3. Clone folloiwng repositories for development tools to the working directory
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+ * https://github.com/rggen/rggen-devtools
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+ * https://github.com/rggen/rggen-checkout
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+ 4. Clone other RgGen's repositories
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+ * Invoke commnad below on to the working directory
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+ * `./rggen-devtools/bin/checkout --list ./rggen-checkout/all.yml --dir .`
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+
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+ ```
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+ $ mkdir work
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+ $ cd work
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+ $ git clone git@github.com:yourname/your_repository.git
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+ $ git clone git@github.com:rggen/rggen-devtools.git
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+ $ git clone git@github.com:rggen/rggen-checkout.git
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+ $ ./rggen-devtools/bin/checkout.rb --list ./rggen-checkout/all.yml --dir .
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+ ```
data/LICENSE CHANGED
@@ -1,6 +1,6 @@
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  The MIT License (MIT)
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- Copyright (c) 2019-2020 Taichi Ishitani
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+ Copyright (c) 2019-2021 Taichi Ishitani
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  Permission is hereby granted, free of charge, to any person obtaining a copy
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  of this software and associated documentation files (the "Software"), to deal
data/README.md CHANGED
@@ -5,24 +5,28 @@
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  [![Quality Gate Status](https://sonarcloud.io/api/project_badges/measure?project=rggen_rggen&metric=alert_status)](https://sonarcloud.io/dashboard?id=rggen_rggen)
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  [![Gitter](https://badges.gitter.im/rggen/rggen.svg)](https://gitter.im/rggen/rggen?utm_source=badge&utm_medium=badge&utm_campaign=pr-badge)
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+ [![ko-fi](https://www.ko-fi.com/img/githubbutton_sm.svg)](https://ko-fi.com/A0A231E3I)
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+
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  # RgGen
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- RgGen is a code generation tool for ASIC/IP/FPGA/RTL engineers. It will automatically generate soruce code related to configuration and status registers (CSR), e.g. SytemVerilog RTL, UVM RAL model, Wiki documents, from human readable register map specifications.
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+ RgGen is a code generation tool for ASIC/IP/FPGA/RTL engineers. It will automatically generate soruce code related to configuration and status registers (CSR), e.g. SytemVerilog RTL, UVM register model (UVM RAL), Wiki documents, from human readable register map specifications.
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  RgGen has following features:
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  * Generate source files related to CSR from register map specifications
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  * SystemVerilog RTL
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- * UVM RAL model
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+ * Verilog RTL
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+ * Need [rggen-verilog](https://github.com/rggen/rggen-verilog) plugin
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+ * UVM register model (UVM RAL)
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  * Register map documents written in Markdown
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  * Register map specifications can be written in human readable format
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- * Supported formats are listed below:
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- * Ruby with APIs to describe register map information
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- * YAML
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- * JSON
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- * Spreadsheet (XLSX, XLS, OSD, CSV)
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- * [SiFive DUH](https://github.com/sifive/duh)
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- * Need [rggen-duh](https://github.com/rggen/rggen-duh) plugin
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+ * Ruby with APIs to describe register map information
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+ * YAML
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+ * JSON
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+ * TOML
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+ * Spreadsheet (XLSX, XLS, OSD, CSV)
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+ * [SiFive DUH](https://github.com/sifive/duh)
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+ * Need [rggen-duh](https://github.com/rggen/rggen-duh) plugin
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  * Costomize RgGen for you environment
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  * E.g. add special bit field types
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@@ -30,7 +34,7 @@ RgGen has following features:
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  ### Ruby
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- RgGen is written in the [Ruby](https://www.ruby-lang.org/en/about/) programing language and its required version is 2.4 or later. You need to install any of these versions of Ruby before installing RgGen tool. To install Ruby, see [this page](https://www.ruby-lang.org/en/downloads/).
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+ RgGen is written in the [Ruby](https://www.ruby-lang.org/en/about/) programing language and its required version is 2.5 or later. You need to install any of these versions of Ruby before installing RgGen tool. To install Ruby, see [this page](https://www.ruby-lang.org/en/downloads/).
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  ### Installatin Command
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@@ -79,7 +83,7 @@ Following EDA tools can accept the generated source files.
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  * Cadence Xcelium
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  * Xilinx Vivado Simulator
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  * Confirmed RTL only
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- * Not sure if RAL models are accepted
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+ * Not sure if UVM register models are accepted
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  * Verilator
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  * Need `-Wno-fatal` switch
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  * Synthesis tools
@@ -103,28 +107,31 @@ By using these example files, you can try to use RgGen. Hit command below:
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  $ rggen -c config.yml -o out block_0.yml block_1.yml
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  ```
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- * `-c`
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- * Specify path to your configuration file
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- * `-o`
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- * Specify path to the directory where generated files will be written to
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+ * `-c`: Specify path to your configuration file
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+ * `-o`: Specify path to the directory where generated files will be written to
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  Then, generated files listed below will be written to `out` directory.
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  * SystemVerilog RTL
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  * https://github.com/rggen/rggen-sample/blob/master/block_0.sv
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  * https://github.com/rggen/rggen-sample/blob/master/block_1.sv
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- * UVM RAL model
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+ * UVM register model
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  * https://github.com/rggen/rggen-sample/blob/master/block_0_ral_pkg.sv
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  * https://github.com/rggen/rggen-sample/blob/master/block_1_ral_pkg.sv
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  * Markdown document
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  * https://github.com/rggen/rggen-sample/blob/master/block_0.md
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  * https://github.com/rggen/rggen-sample/blob/master/block_1.md
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+ ## Contributing
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+
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+ See [Contributing Guide](CONTRIBUTING.md).
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+
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  ## Contact
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  Feedbacks, bug reports, questions and etc. are wellcome! You can post them by using following ways:
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  * [GitHub Issue Tracker](https://github.com/rggen/rggen/issues)
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+ * [GitHub Discussions](https://github.com/rggen/rggen/discussions)
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  * [Chat Room](https://gitter.im/rggen/rggen)
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  * [Mailing List](https://groups.google.com/d/forum/rggen)
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  * [Mail](mailto:rggen@googlegroups.com)
@@ -137,11 +144,12 @@ Feedbacks, bug reports, questions and etc. are wellcome! You can post them by us
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  * https://github.com/rggen/rggen-markdown
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  * https://github.com/rggen/rggen-spreadsheet-loader
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  * https://github.com/rggen/rggen-duh
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+ * https://github.com/rggen/rggen-verilog
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  ## Copyright & License
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- Copyright © 2019-2020 Taichi Ishitani. RgGen is licensed under the [MIT License](https://opensource.org/licenses/MIT), see [LICENSE](LICENSE) for futher detils.
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+ Copyright © 2019-2021 Taichi Ishitani. RgGen is licensed under the [MIT License](https://opensource.org/licenses/MIT), see [LICENSE](LICENSE) for futher detils.
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  ## Code of Conduct
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- Everyone interacting in the RgGen project’s codebases, issue trackers, chat rooms and mailing lists is expected to follow the [code of conduct](https://github.com/rggen/rggen/blob/master/CODE_OF_CONDUCT.md).
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+ Everyone interacting in the RgGen project’s codebases, issue trackers, chat rooms and mailing lists is expected to follow the [code of conduct](CODE_OF_CONDUCT.md).
data/lib/rggen/version.rb CHANGED
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  # frozen_string_literal: true
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  module RgGen
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- VERSION = '0.23.0'
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+ VERSION = '0.25.1'
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  end
metadata CHANGED
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  --- !ruby/object:Gem::Specification
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  name: rggen
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  version: !ruby/object:Gem::Version
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- version: 0.23.0
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+ version: 0.25.1
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  platform: ruby
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  authors:
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  - Taichi Ishitani
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  autorequire:
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  bindir: bin
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  cert_chain: []
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- date: 2020-08-25 00:00:00.000000000 Z
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+ date: 2021-03-02 00:00:00.000000000 Z
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  dependencies:
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  - !ruby/object:Gem::Dependency
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  name: rggen-core
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  requirements:
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  - - "~>"
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  - !ruby/object:Gem::Version
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- version: 0.23.0
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+ version: 0.25.0
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  type: :runtime
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  prerelease: false
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  version_requirements: !ruby/object:Gem::Requirement
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  requirements:
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  - - "~>"
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  - !ruby/object:Gem::Version
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- version: 0.23.0
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+ version: 0.25.0
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  - !ruby/object:Gem::Dependency
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  name: rggen-default-register-map
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  requirement: !ruby/object:Gem::Requirement
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  requirements:
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  - - "~>"
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  - !ruby/object:Gem::Version
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- version: 0.23.0
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+ version: 0.25.1
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  type: :runtime
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  prerelease: false
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  version_requirements: !ruby/object:Gem::Requirement
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  requirements:
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  - - "~>"
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  - !ruby/object:Gem::Version
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- version: 0.23.0
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+ version: 0.25.1
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  - !ruby/object:Gem::Dependency
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  name: rggen-markdown
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  requirement: !ruby/object:Gem::Requirement
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  requirements:
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  - - "~>"
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  - !ruby/object:Gem::Version
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- version: 0.19.0
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+ version: 0.21.0
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  type: :runtime
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  prerelease: false
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  version_requirements: !ruby/object:Gem::Requirement
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  requirements:
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  - - "~>"
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  - !ruby/object:Gem::Version
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- version: 0.19.0
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+ version: 0.21.0
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  - !ruby/object:Gem::Dependency
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  name: rggen-spreadsheet-loader
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  requirement: !ruby/object:Gem::Requirement
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  requirements:
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  - - "~>"
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  - !ruby/object:Gem::Version
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- version: 0.18.0
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+ version: 0.20.0
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  type: :runtime
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  prerelease: false
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  version_requirements: !ruby/object:Gem::Requirement
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  requirements:
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  - - "~>"
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  - !ruby/object:Gem::Version
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- version: 0.18.0
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+ version: 0.20.0
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  - !ruby/object:Gem::Dependency
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  name: rggen-systemverilog
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  requirement: !ruby/object:Gem::Requirement
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  requirements:
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  - - "~>"
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  - !ruby/object:Gem::Version
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- version: 0.23.0
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+ version: 0.25.0
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  type: :runtime
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  prerelease: false
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  version_requirements: !ruby/object:Gem::Requirement
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  requirements:
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  - - "~>"
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  - !ruby/object:Gem::Version
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- version: 0.23.0
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+ version: 0.25.0
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  - !ruby/object:Gem::Dependency
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  name: bundler
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  requirement: !ruby/object:Gem::Requirement
@@ -105,6 +105,7 @@ extensions: []
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  extra_rdoc_files: []
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  files:
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  - CODE_OF_CONDUCT.md
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+ - CONTRIBUTING.md
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  - LICENSE
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110
  - README.md
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111
  - lib/rggen.rb
@@ -126,14 +127,14 @@ required_ruby_version: !ruby/object:Gem::Requirement
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  requirements:
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128
  - - ">="
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  - !ruby/object:Gem::Version
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- version: '2.4'
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+ version: '2.5'
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  required_rubygems_version: !ruby/object:Gem::Requirement
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132
  requirements:
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133
  - - ">="
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  - !ruby/object:Gem::Version
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135
  version: '0'
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136
  requirements: []
136
- rubygems_version: 3.1.2
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+ rubygems_version: 3.2.3
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138
  signing_key:
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139
  specification_version: 4
139
140
  summary: Code generation tool for configuration and status registers