rggen 0.23.0 → 0.23.1

Sign up to get free protection for your applications and to get access to all the features.
Files changed (4) hide show
  1. checksums.yaml +4 -4
  2. data/README.md +14 -15
  3. data/lib/rggen/version.rb +1 -1
  4. metadata +6 -6
checksums.yaml CHANGED
@@ -1,7 +1,7 @@
1
1
  ---
2
2
  SHA256:
3
- metadata.gz: ba77b2a87d728a3057ebba1db78074f7cce7131589209ff662040874648abab4
4
- data.tar.gz: 6b8006bf45effc2f8f3ec9b921a2b1ea3806f1763ebb1433bd3b6874aad40520
3
+ metadata.gz: f0ddaed15239e1e1ad506d82524fb130c7963dbb8b68d592e8cf8e85e475c8c4
4
+ data.tar.gz: 86b7464bb96f2793f763d0ac60dee061fd9425544031ab205a761925777c0365
5
5
  SHA512:
6
- metadata.gz: 214db04731767ad6d780ed97b66773be3cf6aeb31dc4ae083c46b67c7548c7c949a6c26e61703aea6f697e03cd3fbe8e3b7393e72f3b86e95fc8d6202735bfd1
7
- data.tar.gz: b0329a9cc3dc6c6d15f0191e5bdf91d268d730f0205e66a337e0932ff3bd058dca1153cd096466340b2adba14e1d0cd6880238c4bde227ada54d1a20feb4f179
6
+ metadata.gz: 408d5c642724bdd06e77670e088ca190ec453df4d6cae4147b161e7e26e393979a4d54d1e4fc3477b464e352b422b51e6a4d9f004b2bc673a0db18ab3a3104f8
7
+ data.tar.gz: d10f8310d38b88458954979f051ef78bca55813c83d9f2f1ddb8a9585a98f43045c30a424160de6bffde35d0e8f47837f92795cd8a02eea2a4910b2584f3e177
data/README.md CHANGED
@@ -7,22 +7,23 @@
7
7
 
8
8
  # RgGen
9
9
 
10
- RgGen is a code generation tool for ASIC/IP/FPGA/RTL engineers. It will automatically generate soruce code related to configuration and status registers (CSR), e.g. SytemVerilog RTL, UVM RAL model, Wiki documents, from human readable register map specifications.
10
+ RgGen is a code generation tool for ASIC/IP/FPGA/RTL engineers. It will automatically generate soruce code related to configuration and status registers (CSR), e.g. SytemVerilog RTL, UVM register model (UVM RAL), Wiki documents, from human readable register map specifications.
11
11
 
12
12
  RgGen has following features:
13
13
 
14
14
  * Generate source files related to CSR from register map specifications
15
15
  * SystemVerilog RTL
16
- * UVM RAL model
16
+ * Verilog RTL
17
+ * Need [rggen-verilog](https://github.com/rggen/rggen-verilog) plugin
18
+ * UVM register model (UVM RAL)
17
19
  * Register map documents written in Markdown
18
20
  * Register map specifications can be written in human readable format
19
- * Supported formats are listed below:
20
- * Ruby with APIs to describe register map information
21
- * YAML
22
- * JSON
23
- * Spreadsheet (XLSX, XLS, OSD, CSV)
24
- * [SiFive DUH](https://github.com/sifive/duh)
25
- * Need [rggen-duh](https://github.com/rggen/rggen-duh) plugin
21
+ * Ruby with APIs to describe register map information
22
+ * YAML
23
+ * JSON
24
+ * Spreadsheet (XLSX, XLS, OSD, CSV)
25
+ * [SiFive DUH](https://github.com/sifive/duh)
26
+ * Need [rggen-duh](https://github.com/rggen/rggen-duh) plugin
26
27
  * Costomize RgGen for you environment
27
28
  * E.g. add special bit field types
28
29
 
@@ -79,7 +80,7 @@ Following EDA tools can accept the generated source files.
79
80
  * Cadence Xcelium
80
81
  * Xilinx Vivado Simulator
81
82
  * Confirmed RTL only
82
- * Not sure if RAL models are accepted
83
+ * Not sure if UVM register models are accepted
83
84
  * Verilator
84
85
  * Need `-Wno-fatal` switch
85
86
  * Synthesis tools
@@ -103,17 +104,15 @@ By using these example files, you can try to use RgGen. Hit command below:
103
104
  $ rggen -c config.yml -o out block_0.yml block_1.yml
104
105
  ```
105
106
 
106
- * `-c`
107
- * Specify path to your configuration file
108
- * `-o`
109
- * Specify path to the directory where generated files will be written to
107
+ * `-c`: Specify path to your configuration file
108
+ * `-o`: Specify path to the directory where generated files will be written to
110
109
 
111
110
  Then, generated files listed below will be written to `out` directory.
112
111
 
113
112
  * SystemVerilog RTL
114
113
  * https://github.com/rggen/rggen-sample/blob/master/block_0.sv
115
114
  * https://github.com/rggen/rggen-sample/blob/master/block_1.sv
116
- * UVM RAL model
115
+ * UVM register model
117
116
  * https://github.com/rggen/rggen-sample/blob/master/block_0_ral_pkg.sv
118
117
  * https://github.com/rggen/rggen-sample/blob/master/block_1_ral_pkg.sv
119
118
  * Markdown document
@@ -1,5 +1,5 @@
1
1
  # frozen_string_literal: true
2
2
 
3
3
  module RgGen
4
- VERSION = '0.23.0'
4
+ VERSION = '0.23.1'
5
5
  end
metadata CHANGED
@@ -1,14 +1,14 @@
1
1
  --- !ruby/object:Gem::Specification
2
2
  name: rggen
3
3
  version: !ruby/object:Gem::Version
4
- version: 0.23.0
4
+ version: 0.23.1
5
5
  platform: ruby
6
6
  authors:
7
7
  - Taichi Ishitani
8
8
  autorequire:
9
9
  bindir: bin
10
10
  cert_chain: []
11
- date: 2020-08-25 00:00:00.000000000 Z
11
+ date: 2020-10-24 00:00:00.000000000 Z
12
12
  dependencies:
13
13
  - !ruby/object:Gem::Dependency
14
14
  name: rggen-core
@@ -16,14 +16,14 @@ dependencies:
16
16
  requirements:
17
17
  - - "~>"
18
18
  - !ruby/object:Gem::Version
19
- version: 0.23.0
19
+ version: 0.23.1
20
20
  type: :runtime
21
21
  prerelease: false
22
22
  version_requirements: !ruby/object:Gem::Requirement
23
23
  requirements:
24
24
  - - "~>"
25
25
  - !ruby/object:Gem::Version
26
- version: 0.23.0
26
+ version: 0.23.1
27
27
  - !ruby/object:Gem::Dependency
28
28
  name: rggen-default-register-map
29
29
  requirement: !ruby/object:Gem::Requirement
@@ -72,14 +72,14 @@ dependencies:
72
72
  requirements:
73
73
  - - "~>"
74
74
  - !ruby/object:Gem::Version
75
- version: 0.23.0
75
+ version: 0.23.1
76
76
  type: :runtime
77
77
  prerelease: false
78
78
  version_requirements: !ruby/object:Gem::Requirement
79
79
  requirements:
80
80
  - - "~>"
81
81
  - !ruby/object:Gem::Version
82
- version: 0.23.0
82
+ version: 0.23.1
83
83
  - !ruby/object:Gem::Dependency
84
84
  name: bundler
85
85
  requirement: !ruby/object:Gem::Requirement