rggen 0.23.0 → 0.23.1
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- checksums.yaml +4 -4
- data/README.md +14 -15
- data/lib/rggen/version.rb +1 -1
- metadata +6 -6
checksums.yaml
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SHA256:
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metadata.gz:
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metadata.gz: f0ddaed15239e1e1ad506d82524fb130c7963dbb8b68d592e8cf8e85e475c8c4
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data.tar.gz: 86b7464bb96f2793f763d0ac60dee061fd9425544031ab205a761925777c0365
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SHA512:
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metadata.gz:
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metadata.gz: 408d5c642724bdd06e77670e088ca190ec453df4d6cae4147b161e7e26e393979a4d54d1e4fc3477b464e352b422b51e6a4d9f004b2bc673a0db18ab3a3104f8
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data.tar.gz: d10f8310d38b88458954979f051ef78bca55813c83d9f2f1ddb8a9585a98f43045c30a424160de6bffde35d0e8f47837f92795cd8a02eea2a4910b2584f3e177
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data/README.md
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# RgGen
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RgGen is a code generation tool for ASIC/IP/FPGA/RTL engineers. It will automatically generate soruce code related to configuration and status registers (CSR), e.g. SytemVerilog RTL, UVM
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RgGen is a code generation tool for ASIC/IP/FPGA/RTL engineers. It will automatically generate soruce code related to configuration and status registers (CSR), e.g. SytemVerilog RTL, UVM register model (UVM RAL), Wiki documents, from human readable register map specifications.
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RgGen has following features:
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* Generate source files related to CSR from register map specifications
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* SystemVerilog RTL
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*
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* Verilog RTL
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* Need [rggen-verilog](https://github.com/rggen/rggen-verilog) plugin
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* UVM register model (UVM RAL)
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* Register map documents written in Markdown
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* Register map specifications can be written in human readable format
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*
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* [
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* Need [rggen-duh](https://github.com/rggen/rggen-duh) plugin
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* Ruby with APIs to describe register map information
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* YAML
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* JSON
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* Spreadsheet (XLSX, XLS, OSD, CSV)
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* [SiFive DUH](https://github.com/sifive/duh)
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* Need [rggen-duh](https://github.com/rggen/rggen-duh) plugin
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* Costomize RgGen for you environment
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* E.g. add special bit field types
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@@ -79,7 +80,7 @@ Following EDA tools can accept the generated source files.
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* Cadence Xcelium
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* Xilinx Vivado Simulator
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* Confirmed RTL only
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* Not sure if
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* Not sure if UVM register models are accepted
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* Verilator
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* Need `-Wno-fatal` switch
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* Synthesis tools
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@@ -103,17 +104,15 @@ By using these example files, you can try to use RgGen. Hit command below:
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$ rggen -c config.yml -o out block_0.yml block_1.yml
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```
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* `-c
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* `-o`
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* Specify path to the directory where generated files will be written to
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* `-c`: Specify path to your configuration file
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* `-o`: Specify path to the directory where generated files will be written to
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Then, generated files listed below will be written to `out` directory.
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* SystemVerilog RTL
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* https://github.com/rggen/rggen-sample/blob/master/block_0.sv
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* https://github.com/rggen/rggen-sample/blob/master/block_1.sv
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* UVM
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* UVM register model
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* https://github.com/rggen/rggen-sample/blob/master/block_0_ral_pkg.sv
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* https://github.com/rggen/rggen-sample/blob/master/block_1_ral_pkg.sv
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* Markdown document
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data/lib/rggen/version.rb
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metadata
CHANGED
@@ -1,14 +1,14 @@
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--- !ruby/object:Gem::Specification
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name: rggen
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version: !ruby/object:Gem::Version
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version: 0.23.
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version: 0.23.1
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platform: ruby
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authors:
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- Taichi Ishitani
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autorequire:
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bindir: bin
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cert_chain: []
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date: 2020-
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date: 2020-10-24 00:00:00.000000000 Z
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dependencies:
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- !ruby/object:Gem::Dependency
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name: rggen-core
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requirements:
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- - "~>"
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- !ruby/object:Gem::Version
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version: 0.23.
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version: 0.23.1
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type: :runtime
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prerelease: false
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version_requirements: !ruby/object:Gem::Requirement
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requirements:
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- - "~>"
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- !ruby/object:Gem::Version
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version: 0.23.
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version: 0.23.1
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- !ruby/object:Gem::Dependency
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name: rggen-default-register-map
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requirement: !ruby/object:Gem::Requirement
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requirements:
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- - "~>"
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- !ruby/object:Gem::Version
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version: 0.23.
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version: 0.23.1
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type: :runtime
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prerelease: false
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version_requirements: !ruby/object:Gem::Requirement
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requirements:
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- - "~>"
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- !ruby/object:Gem::Version
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version: 0.23.
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version: 0.23.1
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- !ruby/object:Gem::Dependency
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name: bundler
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requirement: !ruby/object:Gem::Requirement
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