rggen 0.21.1 → 0.24.0

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data/LICENSE

@@ -1,6 +1,6 @@
 The MIT License (MIT)
 
-Copyright (c) 2019-2020 Taichi Ishitani
+Copyright (c) 2019-2021 Taichi Ishitani
 
 Permission is hereby granted, free of charge, to any person obtaining a copy
 of this software and associated documentation files (the "Software"), to deal

data/README.md

@@ -5,22 +5,28 @@
 [![Quality Gate Status](https://sonarcloud.io/api/project_badges/measure?project=rggen_rggen&metric=alert_status)](https://sonarcloud.io/dashboard?id=rggen_rggen)
 [![Gitter](https://badges.gitter.im/rggen/rggen.svg)](https://gitter.im/rggen/rggen?utm_source=badge&utm_medium=badge&utm_campaign=pr-badge)
 
+[![ko-fi](https://www.ko-fi.com/img/githubbutton_sm.svg)](https://ko-fi.com/A0A231E3I)
+
 # RgGen
 
-RgGen is a code generation tool for ASIC/IP/FPGA/RTL engineers. It will automatically generate soruce code related to configuration and status registers (CSR), e.g. SytemVerilog RTL, UVM RAL model, Wiki documents, from human readable register map specifications.
+RgGen is a code generation tool for ASIC/IP/FPGA/RTL engineers. It will automatically generate soruce code related to configuration and status registers (CSR), e.g. SytemVerilog RTL, UVM register model (UVM RAL), Wiki documents, from human readable register map specifications.
 
 RgGen has following features:
 
 * Generate source files related to CSR from register map specifications
     * SystemVerilog RTL
-    * UVM RAL model
+    * Verilog RTL
+        * Need [rggen-verilog](https://github.com/rggen/rggen-verilog) plugin
+    * UVM register model (UVM RAL)
     * Register map documents written in Markdown
 * Register map specifications can be written in human readable format
-    * Supported formats are listed below:
-        * Ruby with APIs to describe register map information
-        * YAML
-        * JSON
-        * Spreadsheet (XLSX, XLS, OSD, CSV)
+    * Ruby with APIs to describe register map information
+    * YAML
+    * JSON
+    * TOML
+    * Spreadsheet (XLSX, XLS, OSD, CSV)
+    * [SiFive DUH](https://github.com/sifive/duh)
+        * Need [rggen-duh](https://github.com/rggen/rggen-duh) plugin
 * Costomize RgGen for you environment
     * E.g. add special bit field types
 
@@ -77,7 +83,7 @@ Following EDA tools can accept the generated source files.
     * Cadence Xcelium
     * Xilinx Vivado Simulator
         * Confirmed RTL only
-        * Not sure if RAL models are accepted
+        * Not sure if UVM register models are accepted
     * Verilator
         * Need `-Wno-fatal` switch
 * Synthesis tools
@@ -101,17 +107,15 @@ By using these example files, you can try to use RgGen. Hit command below:
 $ rggen -c config.yml -o out block_0.yml block_1.yml
 ```
 
-* `-c`
-    * Specify path to your configuration file
-* `-o`
-    * Specify path to the directory where generated files will be written to
+* `-c`: Specify path to your configuration file
+* `-o`: Specify path to the directory where generated files will be written to
 
 Then, generated files listed below will be written to `out` directory.
 
 * SystemVerilog RTL
     * https://github.com/rggen/rggen-sample/blob/master/block_0.sv
     * https://github.com/rggen/rggen-sample/blob/master/block_1.sv
-* UVM RAL model
+* UVM register model
     * https://github.com/rggen/rggen-sample/blob/master/block_0_ral_pkg.sv
     * https://github.com/rggen/rggen-sample/blob/master/block_1_ral_pkg.sv
 * Markdown document
@@ -123,6 +127,7 @@ Then, generated files listed below will be written to `out` directory.
 Feedbacks, bug reports, questions and etc. are wellcome! You can post them by using following ways:
 
 * [GitHub Issue Tracker](https://github.com/rggen/rggen/issues)
+* [GitHub Discussions](https://github.com/rggen/rggen/discussions)
 * [Chat Room](https://gitter.im/rggen/rggen)
 * [Mailing List](https://groups.google.com/d/forum/rggen)
 * [Mail](mailto:rggen@googlegroups.com)
@@ -134,11 +139,12 @@ Feedbacks, bug reports, questions and etc. are wellcome! You can post them by us
 * https://github.com/rggen/rggen-systemverilog
 * https://github.com/rggen/rggen-markdown
 * https://github.com/rggen/rggen-spreadsheet-loader
-
+* https://github.com/rggen/rggen-duh
+* https://github.com/rggen/rggen-verilog
 
 ## Copyright & License
 
-Copyright © 2019-2020 Taichi Ishitani. RgGen is licensed under the [MIT License](https://opensource.org/licenses/MIT), see [LICENSE](LICENSE) for futher detils.
+Copyright © 2019-2021 Taichi Ishitani. RgGen is licensed under the [MIT License](https://opensource.org/licenses/MIT), see [LICENSE](LICENSE) for futher detils.
 
 ## Code of Conduct
 

data/lib/rggen.rb

@@ -1,4 +1,3 @@
 # frozen_string_literal: true
 
 require_relative 'rggen/version'
-require_relative 'rggen/default_setup_file'

data/lib/rggen/setup.rb

@@ -0,0 +1,7 @@
+# frozen_string_literal: true
+
+RgGen.load_plugin 'rggen-default-register-map'
+RgGen.load_plugin 'rggen-systemverilog/rtl'
+RgGen.load_plugin 'rggen-systemverilog/ral'
+RgGen.load_plugin 'rggen-markdown'
+RgGen.load_plugin 'rggen-spreadsheet-loader'

data/lib/rggen/version.rb

@@ -1,5 +1,5 @@
 # frozen_string_literal: true
 
 module RgGen
-  VERSION = '0.21.1'
+  VERSION = '0.24.0'
 end

metadata

@@ -1,14 +1,14 @@
 --- !ruby/object:Gem::Specification
 name: rggen
 version: !ruby/object:Gem::Version
-  version: 0.21.1
+  version: 0.24.0
 platform: ruby
 authors:
 - Taichi Ishitani
 autorequire: 
 bindir: bin
 cert_chain: []
-date: 2020-07-24 00:00:00.000000000 Z
+date: 2021-01-20 00:00:00.000000000 Z
 dependencies:
 - !ruby/object:Gem::Dependency
   name: rggen-core
@@ -16,70 +16,70 @@ dependencies:
     requirements:
     - - "~>"
       - !ruby/object:Gem::Version
-        version: 0.21.0
+        version: 0.24.0
   type: :runtime
   prerelease: false
   version_requirements: !ruby/object:Gem::Requirement
     requirements:
     - - "~>"
       - !ruby/object:Gem::Version
-        version: 0.21.0
+        version: 0.24.0
 - !ruby/object:Gem::Dependency
   name: rggen-default-register-map
   requirement: !ruby/object:Gem::Requirement
     requirements:
     - - "~>"
       - !ruby/object:Gem::Version
-        version: 0.21.0
+        version: 0.24.0
   type: :runtime
   prerelease: false
   version_requirements: !ruby/object:Gem::Requirement
     requirements:
     - - "~>"
       - !ruby/object:Gem::Version
-        version: 0.21.0
+        version: 0.24.0
 - !ruby/object:Gem::Dependency
   name: rggen-markdown
   requirement: !ruby/object:Gem::Requirement
     requirements:
     - - "~>"
       - !ruby/object:Gem::Version
-        version: 0.18.0
+        version: 0.20.0
   type: :runtime
   prerelease: false
   version_requirements: !ruby/object:Gem::Requirement
     requirements:
     - - "~>"
       - !ruby/object:Gem::Version
-        version: 0.18.0
+        version: 0.20.0
 - !ruby/object:Gem::Dependency
   name: rggen-spreadsheet-loader
   requirement: !ruby/object:Gem::Requirement
     requirements:
     - - "~>"
       - !ruby/object:Gem::Version
-        version: 0.17.0
+        version: 0.19.0
   type: :runtime
   prerelease: false
   version_requirements: !ruby/object:Gem::Requirement
     requirements:
     - - "~>"
       - !ruby/object:Gem::Version
-        version: 0.17.0
+        version: 0.19.0
 - !ruby/object:Gem::Dependency
   name: rggen-systemverilog
   requirement: !ruby/object:Gem::Requirement
     requirements:
     - - "~>"
       - !ruby/object:Gem::Version
-        version: 0.21.1
+        version: 0.24.0
   type: :runtime
   prerelease: false
   version_requirements: !ruby/object:Gem::Requirement
     requirements:
     - - "~>"
       - !ruby/object:Gem::Version
-        version: 0.21.1
+        version: 0.24.0
 - !ruby/object:Gem::Dependency
   name: bundler
   requirement: !ruby/object:Gem::Requirement
@@ -108,8 +108,7 @@ files:
 - LICENSE
 - README.md
 - lib/rggen.rb
-- lib/rggen/default.rb
-- lib/rggen/default_setup_file.rb
+- lib/rggen/setup.rb
 - lib/rggen/version.rb
 homepage: https://github.com/rggen/rggen
 licenses:
@@ -134,7 +133,7 @@ required_rubygems_version: !ruby/object:Gem::Requirement
     - !ruby/object:Gem::Version
       version: '0'
 requirements: []
-rubygems_version: 3.1.2
+rubygems_version: 3.2.3
 signing_key: 
 specification_version: 4
 summary: Code generation tool for configuration and status registers

data/lib/rggen/default.rb

@@ -1,7 +0,0 @@
-# frozen_string_literal: true
-
-require 'rggen/default_register_map/setup'
-require 'rggen/systemverilog/rtl/setup'
-require 'rggen/systemverilog/ral/setup'
-require 'rggen/markdown/setup'
-require 'rggen/spreadsheet_loader/setup'

data/lib/rggen/default_setup_file.rb

@@ -1,5 +0,0 @@
-# frozen_string_literal: true
-
-module RgGen
-  DEFAULT_SETUP_FILE = File.join(__dir__, 'default.rb').freeze
-end