rggen 0.21.0 → 0.23.2
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- checksums.yaml +4 -4
- data/README.md +15 -14
- data/lib/rggen.rb +0 -1
- data/lib/rggen/setup.rb +7 -0
- data/lib/rggen/version.rb +1 -1
- metadata +13 -14
- data/lib/rggen/default.rb +0 -7
- data/lib/rggen/default_setup_file.rb +0 -5
checksums.yaml
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SHA256:
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metadata.gz:
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data.tar.gz: 112f1b770914e61068a08bc7dbb6dd3920bfcc41f028a24e61b00974364b6818
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metadata.gz: 66120e4621041673ee2aacc7f4dd44b00377734afee4d5b93e615982b9bb6dad71f31ae2d07d57896395acb5af2aa4fad3ffa51ec7367ea6ce32952d0045f723
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data/README.md
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@@ -7,20 +7,23 @@
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# RgGen
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RgGen is a code generation tool for ASIC/IP/FPGA/RTL engineers. It will automatically generate soruce code related to configuration and status registers (CSR), e.g. SytemVerilog RTL, UVM
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RgGen is a code generation tool for ASIC/IP/FPGA/RTL engineers. It will automatically generate soruce code related to configuration and status registers (CSR), e.g. SytemVerilog RTL, UVM register model (UVM RAL), Wiki documents, from human readable register map specifications.
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RgGen has following features:
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* Generate source files related to CSR from register map specifications
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* SystemVerilog RTL
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*
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* Verilog RTL
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* Need [rggen-verilog](https://github.com/rggen/rggen-verilog) plugin
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* UVM register model (UVM RAL)
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* Register map documents written in Markdown
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* Register map specifications can be written in human readable format
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*
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* Ruby with APIs to describe register map information
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* YAML
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* JSON
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* Spreadsheet (XLSX, XLS, OSD, CSV)
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* [SiFive DUH](https://github.com/sifive/duh)
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* Need [rggen-duh](https://github.com/rggen/rggen-duh) plugin
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* Costomize RgGen for you environment
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* E.g. add special bit field types
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@@ -77,7 +80,7 @@ Following EDA tools can accept the generated source files.
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* Cadence Xcelium
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* Xilinx Vivado Simulator
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* Confirmed RTL only
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* Not sure if
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* Not sure if UVM register models are accepted
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* Verilator
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* Need `-Wno-fatal` switch
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* Synthesis tools
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@@ -101,17 +104,15 @@ By using these example files, you can try to use RgGen. Hit command below:
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$ rggen -c config.yml -o out block_0.yml block_1.yml
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```
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* `-c
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* `-o`
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* Specify path to the directory where generated files will be written to
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* `-c`: Specify path to your configuration file
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* `-o`: Specify path to the directory where generated files will be written to
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Then, generated files listed below will be written to `out` directory.
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* SystemVerilog RTL
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* https://github.com/rggen/rggen-sample/blob/master/block_0.sv
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* https://github.com/rggen/rggen-sample/blob/master/block_1.sv
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* UVM
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* UVM register model
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* https://github.com/rggen/rggen-sample/blob/master/block_0_ral_pkg.sv
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* https://github.com/rggen/rggen-sample/blob/master/block_1_ral_pkg.sv
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* Markdown document
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@@ -134,7 +135,7 @@ Feedbacks, bug reports, questions and etc. are wellcome! You can post them by us
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* https://github.com/rggen/rggen-systemverilog
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* https://github.com/rggen/rggen-markdown
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* https://github.com/rggen/rggen-spreadsheet-loader
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* https://github.com/rggen/rggen-duh
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## Copyright & License
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data/lib/rggen.rb
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data/lib/rggen/setup.rb
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data/lib/rggen/version.rb
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metadata
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@@ -1,14 +1,14 @@
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--- !ruby/object:Gem::Specification
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name: rggen
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version: !ruby/object:Gem::Version
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version: 0.
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version: 0.23.2
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platform: ruby
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authors:
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- Taichi Ishitani
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autorequire:
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bindir: bin
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cert_chain: []
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date: 2020-
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date: 2020-10-31 00:00:00.000000000 Z
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dependencies:
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- !ruby/object:Gem::Dependency
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name: rggen-core
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requirements:
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- - "~>"
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- !ruby/object:Gem::Version
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version: 0.
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version: 0.23.1
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type: :runtime
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prerelease: false
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version_requirements: !ruby/object:Gem::Requirement
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requirements:
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- - "~>"
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- !ruby/object:Gem::Version
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version: 0.
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version: 0.23.1
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- !ruby/object:Gem::Dependency
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name: rggen-default-register-map
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requirement: !ruby/object:Gem::Requirement
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requirements:
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- - "~>"
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- !ruby/object:Gem::Version
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version: 0.
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version: 0.23.0
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type: :runtime
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prerelease: false
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version_requirements: !ruby/object:Gem::Requirement
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requirements:
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- - "~>"
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- !ruby/object:Gem::Version
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version: 0.
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version: 0.23.0
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- !ruby/object:Gem::Dependency
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name: rggen-markdown
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requirement: !ruby/object:Gem::Requirement
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requirements:
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- - "~>"
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- !ruby/object:Gem::Version
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version: 0.
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version: 0.19.0
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type: :runtime
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prerelease: false
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version_requirements: !ruby/object:Gem::Requirement
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requirements:
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- - "~>"
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- !ruby/object:Gem::Version
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version: 0.
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version: 0.19.0
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- !ruby/object:Gem::Dependency
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name: rggen-spreadsheet-loader
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requirement: !ruby/object:Gem::Requirement
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requirements:
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- - "~>"
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- !ruby/object:Gem::Version
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version: 0.
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version: 0.18.2
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type: :runtime
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prerelease: false
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version_requirements: !ruby/object:Gem::Requirement
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requirements:
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- - "~>"
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- !ruby/object:Gem::Version
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version: 0.
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version: 0.18.2
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- !ruby/object:Gem::Dependency
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name: rggen-systemverilog
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requirement: !ruby/object:Gem::Requirement
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requirements:
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- - "~>"
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- !ruby/object:Gem::Version
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version: 0.
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version: 0.23.1
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type: :runtime
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prerelease: false
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version_requirements: !ruby/object:Gem::Requirement
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requirements:
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- - "~>"
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- !ruby/object:Gem::Version
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version: 0.
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version: 0.23.1
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- !ruby/object:Gem::Dependency
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name: bundler
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requirement: !ruby/object:Gem::Requirement
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@@ -108,8 +108,7 @@ files:
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- LICENSE
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- README.md
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- lib/rggen.rb
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-
- lib/rggen/
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- lib/rggen/default_setup_file.rb
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- lib/rggen/setup.rb
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- lib/rggen/version.rb
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homepage: https://github.com/rggen/rggen
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licenses:
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data/lib/rggen/default.rb
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