rggen 0.17.0 → 0.18.0

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Files changed (3) hide show
  1. checksums.yaml +4 -4
  2. data/lib/rggen/version.rb +1 -1
  3. metadata +10 -10
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data/lib/rggen/version.rb CHANGED
@@ -1,5 +1,5 @@
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  # frozen_string_literal: true
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  module RgGen
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- VERSION = '0.17.0'
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+ VERSION = '0.18.0'
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  end
metadata CHANGED
@@ -1,14 +1,14 @@
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  --- !ruby/object:Gem::Specification
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  name: rggen
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  version: !ruby/object:Gem::Version
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- version: 0.17.0
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+ version: 0.18.0
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  platform: ruby
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  authors:
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  - Taichi Ishitani
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  autorequire:
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  bindir: bin
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  cert_chain: []
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- date: 2019-11-13 00:00:00.000000000 Z
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+ date: 2019-11-19 00:00:00.000000000 Z
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  dependencies:
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  - !ruby/object:Gem::Dependency
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  name: rggen-core
@@ -16,28 +16,28 @@ dependencies:
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  requirements:
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  - - "~>"
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  - !ruby/object:Gem::Version
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- version: '0.17'
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+ version: '0.18'
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  type: :runtime
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  prerelease: false
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  version_requirements: !ruby/object:Gem::Requirement
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  requirements:
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  - - "~>"
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  - !ruby/object:Gem::Version
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- version: '0.17'
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+ version: '0.18'
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  - !ruby/object:Gem::Dependency
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  name: rggen-default-register-map
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  requirement: !ruby/object:Gem::Requirement
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  requirements:
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  - - "~>"
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  - !ruby/object:Gem::Version
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- version: '0.17'
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+ version: '0.18'
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  type: :runtime
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  prerelease: false
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  version_requirements: !ruby/object:Gem::Requirement
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  requirements:
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  - - "~>"
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  - !ruby/object:Gem::Version
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- version: '0.17'
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+ version: '0.18'
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  - !ruby/object:Gem::Dependency
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  name: rggen-markdown
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  requirement: !ruby/object:Gem::Requirement
@@ -72,14 +72,14 @@ dependencies:
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  requirements:
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  - - "~>"
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  - !ruby/object:Gem::Version
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- version: '0.17'
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+ version: '0.18'
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  type: :runtime
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  prerelease: false
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  version_requirements: !ruby/object:Gem::Requirement
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  requirements:
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  - - "~>"
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  - !ruby/object:Gem::Version
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- version: '0.17'
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+ version: '0.18'
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  - !ruby/object:Gem::Dependency
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  name: bundler
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  requirement: !ruby/object:Gem::Requirement
@@ -96,7 +96,7 @@ dependencies:
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  version: '0'
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  description: |
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  RgGen is a code generation tool for ASIC/IP/FPGA/RTL engineers.
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- It will automatically generate soruce code related to control/status registers (CSR),
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+ It will automatically generate soruce code related to configuration and status registers (CSR),
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  e.g. SytemVerilog RTL, UVM RAL model, Wiki documents, from human readable register map specifications.
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  email:
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  - rggen@googlegroups.com
@@ -137,5 +137,5 @@ requirements: []
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  rubygems_version: 3.0.3
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  signing_key:
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  specification_version: 4
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- summary: Code generation tool for control/status registers
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+ summary: Code generation tool for configuration and status registers
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  test_files: []