rggen-vhdl 0.9.0 → 0.10.1

checksums.yaml

@@ -1,7 +1,7 @@
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-  data.tar.gz: be850f4ac1b090d779803da9e01f3204e8f852aef9238b2589130ded97782a84
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+  data.tar.gz: d3b5529f4247a8b1118859542328402bfc025290c1139b40c7d93ab62d6d4c2c
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+  data.tar.gz: 76f2b1ac8d10a91750b1ea5c24ab5b75ba78d5ef54e8d9ad178b32dfbe7b73fab0551733281d3ebf808ccb3640fff5bc8cf17695bc1a38cf4ea89e06f2835821

data/lib/rggen/vhdl/bit_field/type/custom.erb

@@ -1,4 +1,4 @@
-u_bit_field: entity work.rggen_bit_field
+u_bit_field: entity <%= library_name %>.rggen_bit_field
   generic map (
     WIDTH               => <%= width %>,
     INITIAL_VALUE       => <%= initial_value %>,

data/lib/rggen/vhdl/bit_field/type/rc_w0c_w1c_wc_woc.erb

@@ -1,4 +1,4 @@
-u_bit_field: entity work.rggen_bit_field
+u_bit_field: entity <%= library_name %>.rggen_bit_field
   generic map (
     WIDTH           => <%= width %>,
     INITIAL_VALUE   => <%= initial_value %>,

data/lib/rggen/vhdl/bit_field/type/ro_rotrg.erb

@@ -1,4 +1,4 @@
-u_bit_field: entity work.rggen_bit_field
+u_bit_field: entity <%= library_name %>.rggen_bit_field
   generic map (
     WIDTH               => <%= width %>,
     STORAGE             => false,

data/lib/rggen/vhdl/bit_field/type/rof.erb

@@ -1,4 +1,4 @@
-u_bit_field: entity work.rggen_bit_field
+u_bit_field: entity <%= library_name %>.rggen_bit_field
   generic map (
     WIDTH               => <%= width %>,
     STORAGE             => false,

data/lib/rggen/vhdl/bit_field/type/rohw.erb

@@ -1,4 +1,4 @@
-u_bit_field: entity work.rggen_bit_field
+u_bit_field: entity <%= library_name %>.rggen_bit_field
   generic map (
     WIDTH           => <%= width %>,
     INITIAL_VALUE   => <%= initial_value %>,

data/lib/rggen/vhdl/bit_field/type/row0trg_row1trg.erb

@@ -1,4 +1,4 @@
-u_bit_field: entity work.rggen_bit_field_w01trg
+u_bit_field: entity <%= library_name %>.rggen_bit_field_w01trg
   generic map (
     WRITE_ONE_TRIGGER => <%= write_one_trigger? %>,
     WIDTH             => <%= width %>

data/lib/rggen/vhdl/bit_field/type/rowo_rowotrg.erb

@@ -1,4 +1,4 @@
-u_bit_field: entity work.rggen_bit_field
+u_bit_field: entity <%= library_name %>.rggen_bit_field
   generic map (
     WIDTH               => <%= width %>,
     INITIAL_VALUE       => <%= initial_value %>,

data/lib/rggen/vhdl/bit_field/type/rs_w0s_w1s_ws_wos.erb

@@ -1,4 +1,4 @@
-u_bit_field: entity work.rggen_bit_field
+u_bit_field: entity <%= library_name %>.rggen_bit_field
   generic map (
     WIDTH           => <%= width %>,
     INITIAL_VALUE   => <%= initial_value %>,

data/lib/rggen/vhdl/bit_field/type/rw_rwtrg_w1.erb

@@ -1,4 +1,4 @@
-u_bit_field: entity work.rggen_bit_field
+u_bit_field: entity <%= library_name %>.rggen_bit_field
   generic map (
     WIDTH           => <%= width %>,
     INITIAL_VALUE   => <%= initial_value %>,

data/lib/rggen/vhdl/bit_field/type/rwc.erb

@@ -1,4 +1,4 @@
-u_bit_field: entity work.rggen_bit_field
+u_bit_field: entity <%= library_name %>.rggen_bit_field
   generic map (
     WIDTH           => <%= width %>,
     INITIAL_VALUE   => <%= initial_value %>,

data/lib/rggen/vhdl/bit_field/type/rwe_rwl.erb

@@ -1,4 +1,4 @@
-u_bit_field: entity work.rggen_bit_field
+u_bit_field: entity <%= library_name %>.rggen_bit_field
   generic map (
     WIDTH                     => <%= width %>,
     INITIAL_VALUE             => <%= initial_value %>,

data/lib/rggen/vhdl/bit_field/type/rwhw.erb

@@ -1,4 +1,4 @@
-u_bit_field: entity work.rggen_bit_field
+u_bit_field: entity <%= library_name %>.rggen_bit_field
   generic map (
     WIDTH         => <%= width %>,
     INITIAL_VALUE => <%= initial_value %>

data/lib/rggen/vhdl/bit_field/type/rws.erb

@@ -1,4 +1,4 @@
-u_bit_field: entity work.rggen_bit_field
+u_bit_field: entity <%= library_name %>.rggen_bit_field
   generic map (
     WIDTH         => <%= width %>,
     INITIAL_VALUE => <%= initial_value %>,

data/lib/rggen/vhdl/bit_field/type/w0crs_w0src_w1crs_w1src_wcrs_wsrc.erb

@@ -1,4 +1,4 @@
-u_bit_field: entity work.rggen_bit_field
+u_bit_field: entity <%= library_name %>.rggen_bit_field
   generic map (
     WIDTH           => <%= width %>,
     INITIAL_VALUE   => <%= initial_value %>,

data/lib/rggen/vhdl/bit_field/type/w0t_w1t.erb

@@ -1,4 +1,4 @@
-u_bit_field: entity work.rggen_bit_field
+u_bit_field: entity <%= library_name %>.rggen_bit_field
   generic map (
     WIDTH           => <%= width %>,
     INITIAL_VALUE   => <%= initial_value %>,

data/lib/rggen/vhdl/bit_field/type/w0trg_w1trg.erb

@@ -1,4 +1,4 @@
-u_bit_field: entity work.rggen_bit_field_w01trg
+u_bit_field: entity <%= library_name %>.rggen_bit_field_w01trg
   generic map (
     WRITE_ONE_TRIGGER => <%= write_one_trigger? %>,
     WIDTH             => <%= width %>

data/lib/rggen/vhdl/bit_field/type/wo_wo1_wotrg.erb

@@ -1,4 +1,4 @@
-u_bit_field: entity work.rggen_bit_field
+u_bit_field: entity <%= library_name %>.rggen_bit_field
   generic map (
     WIDTH           => <%= width %>,
     INITIAL_VALUE   => <%= initial_value %>,

data/lib/rggen/vhdl/bit_field/type/wrc_wrs.erb

@@ -1,4 +1,4 @@
-u_bit_field: entity work.rggen_bit_field
+u_bit_field: entity <%= library_name %>.rggen_bit_field
   generic map (
     WIDTH           => <%= width %>,
     INITIAL_VALUE   => <%= initial_value %>,

data/lib/rggen/vhdl/bit_field/type.rb

@@ -5,6 +5,10 @@ RgGen.define_list_feature(:bit_field, :type) do
     base_feature do
       private
 
+      def library_name
+        configuration.library_name
+      end
+
       def full_name
         bit_field.full_name('_')
       end

data/lib/rggen/vhdl/global/library_name.rb

@@ -0,0 +1,16 @@
+# frozen_string_literal: true
+
+RgGen.define_simple_feature(:global, :library_name) do
+  configuration do
+    property :library_name, default: 'work'
+    property :use_default_library?, body: -> { library_name.casecmp?('work') }
+
+    input_pattern variable_name
+
+    build do |value|
+      pattern_matched? ||
+        (error "illegal input value for library name: #{value.inspect}")
+      @library_name = match_data.to_s
+    end
+  end
+end

data/lib/rggen/vhdl/register/type/default.erb

@@ -1,4 +1,4 @@
-u_register: entity work.rggen_default_register
+u_register: entity <%= library_name %>.rggen_default_register
   generic map (
     READABLE        => <%= readable? %>,
     WRITABLE        => <%= writable? %>,

data/lib/rggen/vhdl/register/type/external.erb

@@ -1,4 +1,4 @@
-u_register: entity work.rggen_external_register
+u_register: entity <%= library_name %>.rggen_external_register
   generic map (
     ADDRESS_WIDTH => <%= address_width %>,
     BUS_WIDTH     => <%= bus_width %>,

data/lib/rggen/vhdl/register/type/indirect.erb

@@ -1,7 +1,4 @@
-<% index_fields_and_values.each_with_index do |(field, value), i| %>
-<%= indirect_match[i] %> <= '1' when unsigned(<%= field %>) = <%= value %> else '0';
-<% end %>
-u_register: entity work.rggen_indirect_register
+u_register: entity <%= library_name %>.rggen_indirect_register
   generic map (
     READABLE              => <%= readable? %>,
     WRITABLE              => <%= writable? %>,
@@ -9,7 +6,7 @@ u_register: entity work.rggen_indirect_register
     OFFSET_ADDRESS        => <%= offset_address %>,
     BUS_WIDTH             => <%= bus_width %>,
     DATA_WIDTH            => <%= width %>,
-    INDIRECT_MATCH_WIDTH  => <%= match_width %>
+    INDIRECT_MATCH_WIDTH  => <%= index_match_width %>
   )
   port map (
     i_clk                   => <%= clock %>,

data/lib/rggen/vhdl/register/type/indirect.rb

@@ -2,33 +2,33 @@
 
 RgGen.define_list_item_feature(:register, :type, :indirect) do
   vhdl do
+    include RgGen::SystemVerilog::RTL::IndirectIndex
+
     build do
-      signal :indirect_match, { width: match_width }
+      signal :indirect_match, { width: index_match_width }
     end
 
-    main_code :register, from_template: true
+    main_code :register do |code|
+      indirect_index_matches(code)
+      code << process_template
+    end
 
     private
 
-    def match_width
-      register.index_entries.size
+    def array_index_value(value, _width)
+      value
     end
 
-    def index_fields
-      register
-        .collect_index_fields(register_block.bit_fields)
-        .map(&:value)
+    def fixed_index_value(value, _width)
+      value
     end
 
-    def index_values
-      loop_variables = register.local_loop_variables
-      register.index_entries.map do |entry|
-        entry.array_index? && loop_variables.shift || entry.value
-      end
+    def index_match_rhs(index)
+      indirect_match[index]
     end
 
-    def index_fields_and_values
-      index_fields.zip(index_values)
+    def index_match_lhs(field, value)
+      "'1' when unsigned(#{field}) = #{value} else '0'"
     end
   end
 end

data/lib/rggen/vhdl/register/type/rw.erb

@@ -1,4 +1,4 @@
-u_register: entity work.rggen_default_register
+u_register: entity <%= library_name %>.rggen_default_register
   generic map (
     READABLE        => true,
     WRITABLE        => true,

data/lib/rggen/vhdl/register/type.rb

@@ -20,6 +20,10 @@ RgGen.define_list_feature(:register, :type) do
         register.writable?
       end
 
+      def library_name
+        configuration.library_name
+      end
+
       def clock
         register_block.clock
       end
@@ -91,6 +95,14 @@ RgGen.define_list_feature(:register, :type) do
       def bit_field_value
         register.bit_field_value
       end
+
+      def format_offsets(offsets)
+        if integer?(offsets.first)
+          super(offsets)
+        else
+          super([0, *offsets])
+        end
+      end
     end
 
     default_feature do

data/lib/rggen/vhdl/register_block/protocol/apb.erb

@@ -1,4 +1,4 @@
-u_adapter: entity work.rggen_apb_adaper
+u_adapter: entity <%= library_name %>.rggen_apb_adaper
   generic map (
     ADDRESS_WIDTH       => <%= address_width %>,
     LOCAL_ADDRESS_WIDTH => <%= local_address_width %>,

data/lib/rggen/vhdl/register_block/protocol/axi4lite.erb

@@ -1,4 +1,4 @@
-u_adapter: entity work.rggen_axi4lite_adapter
+u_adapter: entity <%= library_name %>.rggen_axi4lite_adapter
   generic map (
     ID_WIDTH            => <%= id_width %>,
     ADDRESS_WIDTH       => <%= address_width %>,

data/lib/rggen/vhdl/register_block/protocol/wishbone.erb

@@ -1,4 +1,4 @@
-u_adapter: entity work.rggen_wishbone_adapter
+u_adapter: entity <%= library_name %>.rggen_wishbone_adapter
   generic map (
     ADDRESS_WIDTH       => <%= address_width %>,
     LOCAL_ADDRESS_WIDTH => <%= local_address_width %>,

data/lib/rggen/vhdl/register_block/protocol.rb

@@ -25,6 +25,10 @@ RgGen.define_list_feature(:register_block, :protocol) do
 
       private
 
+      def library_name
+        configuration.library_name
+      end
+
       def bus_width
         configuration.bus_width
       end

data/lib/rggen/vhdl/register_block/vhdl_top.erb

@@ -2,7 +2,10 @@ library ieee;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;
 
-use work.rggen_rtl.all;
+<% unless use_default_library? %>
+library <%= library_name %>;
+<% end %>
+use <%= library_name %>.rggen_rtl.all;
 
 entity <%= register_block.name %> is
   generic (

data/lib/rggen/vhdl/register_block/vhdl_top.rb

@@ -42,6 +42,14 @@ RgGen.define_simple_feature(:register_block, :vhdl_top) do
 
     private
 
+    def use_default_library?
+      configuration.use_default_library?
+    end
+
+    def library_name
+      configuration.library_name
+    end
+
     def total_registers
       register_block.files_and_registers.sum(&:count)
     end

data/lib/rggen/vhdl/version.rb

@@ -2,6 +2,6 @@
 
 module RgGen
   module VHDL
-    VERSION = '0.9.0'
+    VERSION = '0.10.1'
   end
 end

data/lib/rggen/vhdl.rb

@@ -21,6 +21,7 @@ RgGen.setup_plugin :'rggen-vhdl' do |plugin|
   end
 
   plugin.files [
+    'vhdl/global/library_name',
     'vhdl/register_block/vhdl_top',
     'vhdl/register_block/protocol',
     'vhdl/register_block/protocol/apb',

metadata

@@ -1,14 +1,14 @@
 --- !ruby/object:Gem::Specification
 name: rggen-vhdl
 version: !ruby/object:Gem::Version
-  version: 0.9.0
+  version: 0.10.1
 platform: ruby
 authors:
 - Taichi Ishitani
 autorequire: 
 bindir: bin
 cert_chain: []
-date: 2024-01-22 00:00:00.000000000 Z
+date: 2024-11-28 00:00:00.000000000 Z
 dependencies:
 - !ruby/object:Gem::Dependency
   name: rggen-systemverilog
@@ -16,14 +16,14 @@ dependencies:
     requirements:
     - - ">="
       - !ruby/object:Gem::Version
-        version: 0.33.0
+        version: 0.33.1
   type: :runtime
   prerelease: false
   version_requirements: !ruby/object:Gem::Requirement
     requirements:
     - - ">="
       - !ruby/object:Gem::Version
-        version: 0.33.0
+        version: 0.33.1
 description: VHDL writer plugin for RgGen
 email:
 - rggen@googlegroups.com
@@ -76,6 +76,7 @@ files:
 - lib/rggen/vhdl/component.rb
 - lib/rggen/vhdl/factories.rb
 - lib/rggen/vhdl/feature.rb
+- lib/rggen/vhdl/global/library_name.rb
 - lib/rggen/vhdl/register/tie_off_unused_signals.erb
 - lib/rggen/vhdl/register/type.rb
 - lib/rggen/vhdl/register/type/default.erb
@@ -125,8 +126,8 @@ required_rubygems_version: !ruby/object:Gem::Requirement
     - !ruby/object:Gem::Version
       version: '0'
 requirements: []
-rubygems_version: 3.5.3
+rubygems_version: 3.5.16
 signing_key: 
 specification_version: 4
-summary: rggen-vhdl-0.9.0
+summary: rggen-vhdl-0.10.1
 test_files: []