rggen-vhdl 0.9.0 → 0.10.0
This diff represents the content of publicly available package versions that have been released to one of the supported registries. The information contained in this diff is provided for informational purposes only and reflects changes between package versions as they appear in their respective public registries.
- checksums.yaml +4 -4
- data/lib/rggen/vhdl/bit_field/type/custom.erb +1 -1
- data/lib/rggen/vhdl/bit_field/type/rc_w0c_w1c_wc_woc.erb +1 -1
- data/lib/rggen/vhdl/bit_field/type/ro_rotrg.erb +1 -1
- data/lib/rggen/vhdl/bit_field/type/rof.erb +1 -1
- data/lib/rggen/vhdl/bit_field/type/rohw.erb +1 -1
- data/lib/rggen/vhdl/bit_field/type/row0trg_row1trg.erb +1 -1
- data/lib/rggen/vhdl/bit_field/type/rowo_rowotrg.erb +1 -1
- data/lib/rggen/vhdl/bit_field/type/rs_w0s_w1s_ws_wos.erb +1 -1
- data/lib/rggen/vhdl/bit_field/type/rw_rwtrg_w1.erb +1 -1
- data/lib/rggen/vhdl/bit_field/type/rwc.erb +1 -1
- data/lib/rggen/vhdl/bit_field/type/rwe_rwl.erb +1 -1
- data/lib/rggen/vhdl/bit_field/type/rwhw.erb +1 -1
- data/lib/rggen/vhdl/bit_field/type/rws.erb +1 -1
- data/lib/rggen/vhdl/bit_field/type/w0crs_w0src_w1crs_w1src_wcrs_wsrc.erb +1 -1
- data/lib/rggen/vhdl/bit_field/type/w0t_w1t.erb +1 -1
- data/lib/rggen/vhdl/bit_field/type/w0trg_w1trg.erb +1 -1
- data/lib/rggen/vhdl/bit_field/type/wo_wo1_wotrg.erb +1 -1
- data/lib/rggen/vhdl/bit_field/type/wrc_wrs.erb +1 -1
- data/lib/rggen/vhdl/bit_field/type.rb +4 -0
- data/lib/rggen/vhdl/global/library_name.rb +16 -0
- data/lib/rggen/vhdl/register/type/default.erb +1 -1
- data/lib/rggen/vhdl/register/type/external.erb +1 -1
- data/lib/rggen/vhdl/register/type/indirect.erb +1 -1
- data/lib/rggen/vhdl/register/type/rw.erb +1 -1
- data/lib/rggen/vhdl/register/type.rb +12 -0
- data/lib/rggen/vhdl/register_block/protocol/apb.erb +1 -1
- data/lib/rggen/vhdl/register_block/protocol/axi4lite.erb +1 -1
- data/lib/rggen/vhdl/register_block/protocol/wishbone.erb +1 -1
- data/lib/rggen/vhdl/register_block/protocol.rb +4 -0
- data/lib/rggen/vhdl/register_block/vhdl_top.erb +4 -1
- data/lib/rggen/vhdl/register_block/vhdl_top.rb +8 -0
- data/lib/rggen/vhdl/version.rb +1 -1
- data/lib/rggen/vhdl.rb +1 -0
- metadata +5 -4
checksums.yaml
CHANGED
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---
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SHA256:
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metadata.gz:
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data.tar.gz:
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metadata.gz: e9872f0da195fb312788f08dd53b41e3336cc5ce3b2ad38faa8e91c20320a263
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data.tar.gz: 75bcb850c0004427eb846bbc21fb44f6745a15f1e9ad3b0f31ba91e0b242fb6e
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SHA512:
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metadata.gz:
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data.tar.gz:
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metadata.gz: f0df2d72d345c9e4b81dc0955f8424d0d3706f0128fa9ea5789c2be6b5ae90dc9fb149a916fdee54a0765ab0b036bc7730fdfcd65487a6fa0b9c53b208212ffe
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data.tar.gz: d84282983bf6b39be7c753fc1de6195d3f4d35457903a81896562ae759c02dd30c41fd5da637458b784aa5ee5de0bc015773f267b464f244db80036b10016e21
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# frozen_string_literal: true
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RgGen.define_simple_feature(:global, :library_name) do
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configuration do
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property :library_name, default: 'work'
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property :use_default_library?, body: -> { library_name.casecmp?('work') }
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input_pattern variable_name
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build do |value|
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pattern_matched? ||
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(error "illegal input value for library name: #{value.inspect}")
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@library_name = match_data.to_s
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end
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end
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end
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<% index_fields_and_values.each_with_index do |(field, value), i| %>
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<%= indirect_match[i] %> <= '1' when unsigned(<%= field %>) = <%= value %> else '0';
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<% end %>
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u_register: entity
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u_register: entity <%= library_name %>.rggen_indirect_register
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generic map (
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READABLE => <%= readable? %>,
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WRITABLE => <%= writable? %>,
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register.writable?
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end
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def library_name
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configuration.library_name
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end
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def clock
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register_block.clock
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end
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def bit_field_value
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register.bit_field_value
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end
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def format_offsets(offsets)
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if integer?(offsets.first)
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super(offsets)
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else
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super([0, *offsets])
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end
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end
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end
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default_feature do
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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<% unless use_default_library? %>
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library <%= library_name %>;
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<% end %>
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use <%= library_name %>.rggen_rtl.all;
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entity <%= register_block.name %> is
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generic (
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private
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def use_default_library?
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configuration.use_default_library?
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end
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def library_name
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configuration.library_name
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end
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def total_registers
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register_block.files_and_registers.sum(&:count)
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end
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data/lib/rggen/vhdl/version.rb
CHANGED
data/lib/rggen/vhdl.rb
CHANGED
metadata
CHANGED
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--- !ruby/object:Gem::Specification
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name: rggen-vhdl
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version: !ruby/object:Gem::Version
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version: 0.
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version: 0.10.0
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platform: ruby
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authors:
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- Taichi Ishitani
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autorequire:
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bindir: bin
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cert_chain: []
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date: 2024-
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date: 2024-02-28 00:00:00.000000000 Z
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dependencies:
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- !ruby/object:Gem::Dependency
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name: rggen-systemverilog
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@@ -76,6 +76,7 @@ files:
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- lib/rggen/vhdl/component.rb
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- lib/rggen/vhdl/factories.rb
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- lib/rggen/vhdl/feature.rb
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- lib/rggen/vhdl/global/library_name.rb
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- lib/rggen/vhdl/register/tie_off_unused_signals.erb
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- lib/rggen/vhdl/register/type.rb
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- lib/rggen/vhdl/register/type/default.erb
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- !ruby/object:Gem::Version
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version: '0'
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requirements: []
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rubygems_version: 3.5.
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rubygems_version: 3.5.5
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signing_key:
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specification_version: 4
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summary: rggen-vhdl-0.
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summary: rggen-vhdl-0.10.0
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test_files: []
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