rggen-vhdl 0.8.0 → 0.9.0

checksums.yaml

@@ -1,7 +1,7 @@
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data/LICENSE

@@ -1,6 +1,6 @@
 The MIT License (MIT)
 
-Copyright (c) 2021-2023 Taichi Ishitani
+Copyright (c) 2021-2024 Taichi Ishitani
 
 Permission is hereby granted, free of charge, to any person obtaining a copy
 of this software and associated documentation files (the "Software"), to deal

data/README.md

@@ -68,7 +68,7 @@ Feedbacks, bus reports, questions and etc. are welcome! You can post them bu usi
 
 ## Copyright & License
 
-Copyright © 2021-2023 Taichi Ishitani. RgGen::VHDL is licensed under the [MIT License](https://opensource.org/licenses/MIT), see [LICENSE](LICENSE) for futher details.
+Copyright © 2021-2024 Taichi Ishitani. RgGen::VHDL is licensed under the [MIT License](https://opensource.org/licenses/MIT), see [LICENSE](LICENSE) for futher details.
 
 ## Code of Conduct
 

data/lib/rggen/vhdl/bit_field/type/{rol.erb → rohw.erb}

@@ -16,7 +16,7 @@ u_bit_field: entity work.rggen_bit_field
     o_sw_value        => <%= bit_field_value %>,
     o_write_trigger   => open,
     o_read_trigger    => open,
-    i_hw_write_enable => <%= latch_signal %>,
+    i_hw_write_enable => <%= valid_signal %>,
     i_hw_write_data   => <%= value_in[loop_variables] %>,
     i_hw_set          => (others => '0'),
     i_hw_clear        => (others => '0'),

data/lib/rggen/vhdl/bit_field/type/{rol.rb → rohw.rb}

@@ -1,11 +1,11 @@
 # frozen_string_literal: true
 
-RgGen.define_list_item_feature(:bit_field, :type, :rol) do
+RgGen.define_list_item_feature(:bit_field, :type, :rohw) do
   vhdl do
     build do
       unless bit_field.reference?
-        input :latch, {
-          name: "i_#{full_name}_latch", width: 1, array_size: array_size
+        input :valid, {
+          name: "i_#{full_name}_valid", width: 1, array_size: array_size
         }
       end
       input :value_in, {
@@ -20,8 +20,8 @@ RgGen.define_list_item_feature(:bit_field, :type, :rol) do
 
     private
 
-    def latch_signal
-      reference_bit_field || latch[loop_variables]
+    def valid_signal
+      reference_bit_field || valid[loop_variables]
     end
   end
 end

data/lib/rggen/vhdl/bit_field/type/rwhw.erb

@@ -0,0 +1,26 @@
+u_bit_field: entity work.rggen_bit_field
+  generic map (
+    WIDTH         => <%= width %>,
+    INITIAL_VALUE => <%= initial_value %>
+  )
+  port map (
+    i_clk             => <%= clock %>,
+    i_rst_n           => <%= reset %>,
+    i_sw_valid        => <%= bit_field_valid %>,
+    i_sw_read_mask    => <%= bit_field_read_mask %>,
+    i_sw_write_enable => "1",
+    i_sw_write_mask   => <%= bit_field_write_mask %>,
+    i_sw_write_data   => <%= bit_field_write_data %>,
+    o_sw_read_data    => <%= bit_field_read_data %>,
+    o_sw_value        => <%= bit_field_value %>,
+    o_write_trigger   => open,
+    o_read_trigger    => open,
+    i_hw_write_enable => <%= valid_signal %>,
+    i_hw_write_data   => <%= value_in[loop_variables] %>,
+    i_hw_set          => (others => '0'),
+    i_hw_clear        => (others => '0'),
+    i_value           => (others => '0'),
+    i_mask            => (others => '1'),
+    o_value           => <%= value_out[loop_variables] %>,
+    o_value_unmasked  => open
+  );

data/lib/rggen/vhdl/bit_field/type/rwhw.rb

@@ -0,0 +1,27 @@
+# frozen_string_literal: true
+
+RgGen.define_list_item_feature(:bit_field, :type, :rwhw) do
+  vhdl do
+    build do
+      unless bit_field.reference?
+        input :valid, {
+          name: "i_#{full_name}_valid", width: 1, array_size: array_size
+        }
+      end
+      input :value_in, {
+        name: "i_#{full_name}", width: width, array_size: array_size
+      }
+      output :value_out, {
+        name: "o_#{full_name}", width: width, array_size: array_size
+      }
+    end
+
+    main_code :bit_field, from_template: true
+
+    private
+
+    def valid_signal
+      reference_bit_field || valid[loop_variables]
+    end
+  end
+end

data/lib/rggen/vhdl/bit_field/type/rws.erb

@@ -1,7 +1,8 @@
 u_bit_field: entity work.rggen_bit_field
   generic map (
     WIDTH         => <%= width %>,
-    INITIAL_VALUE => <%= initial_value %>
+    INITIAL_VALUE => <%= initial_value %>,
+    HW_SET_WIDTH  => 1
   )
   port map (
     i_clk             => <%= clock %>,
@@ -15,9 +16,9 @@ u_bit_field: entity work.rggen_bit_field
     o_sw_value        => <%= bit_field_value %>,
     o_write_trigger   => open,
     o_read_trigger    => open,
-    i_hw_write_enable => <%= set_signal %>,
-    i_hw_write_data   => <%= value_in[loop_variables] %>,
-    i_hw_set          => (others => '0'),
+    i_hw_write_enable => "0",
+    i_hw_write_data   => (others => '0'),
+    i_hw_set          => <%= set_signal %>,
     i_hw_clear        => (others => '0'),
     i_value           => (others => '0'),
     i_mask            => (others => '1'),

data/lib/rggen/vhdl/bit_field/type/rws.rb

@@ -8,9 +8,6 @@ RgGen.define_list_item_feature(:bit_field, :type, :rws) do
           name: "i_#{full_name}_set", width: 1, array_size: array_size
         }
       end
-      input :value_in, {
-        name: "i_#{full_name}", width: width, array_size: array_size
-      }
       output :value_out, {
         name: "o_#{full_name}", width: width, array_size: array_size
       }

data/lib/rggen/vhdl/version.rb

@@ -2,6 +2,6 @@
 
 module RgGen
   module VHDL
-    VERSION = '0.8.0'
+    VERSION = '0.9.0'
   end
 end

data/lib/rggen/vhdl.rb

@@ -38,13 +38,14 @@ RgGen.setup_plugin :'rggen-vhdl' do |plugin|
     'vhdl/bit_field/type/rc_w0c_w1c_wc_woc',
     'vhdl/bit_field/type/ro_rotrg',
     'vhdl/bit_field/type/rof',
-    'vhdl/bit_field/type/rol',
+    'vhdl/bit_field/type/rohw',
     'vhdl/bit_field/type/row0trg_row1trg',
     'vhdl/bit_field/type/rowo_rowotrg',
     'vhdl/bit_field/type/rs_w0s_w1s_ws_wos',
     'vhdl/bit_field/type/rw_rwtrg_w1',
     'vhdl/bit_field/type/rwc',
     'vhdl/bit_field/type/rwe_rwl',
+    'vhdl/bit_field/type/rwhw',
     'vhdl/bit_field/type/rws',
     'vhdl/bit_field/type/w0crs_w0src_w1crs_w1src_wcrs_wsrc',
     'vhdl/bit_field/type/w0t_w1t',

metadata

@@ -1,14 +1,14 @@
 --- !ruby/object:Gem::Specification
 name: rggen-vhdl
 version: !ruby/object:Gem::Version
-  version: 0.8.0
+  version: 0.9.0
 platform: ruby
 authors:
 - Taichi Ishitani
 autorequire: 
 bindir: bin
 cert_chain: []
-date: 2023-12-28 00:00:00.000000000 Z
+date: 2024-01-22 00:00:00.000000000 Z
 dependencies:
 - !ruby/object:Gem::Dependency
   name: rggen-systemverilog
@@ -16,14 +16,14 @@ dependencies:
     requirements:
     - - ">="
       - !ruby/object:Gem::Version
-        version: 0.32.0
+        version: 0.33.0
   type: :runtime
   prerelease: false
   version_requirements: !ruby/object:Gem::Requirement
     requirements:
     - - ">="
       - !ruby/object:Gem::Version
-        version: 0.32.0
+        version: 0.33.0
 description: VHDL writer plugin for RgGen
 email:
 - rggen@googlegroups.com
@@ -44,8 +44,8 @@ files:
 - lib/rggen/vhdl/bit_field/type/ro_rotrg.rb
 - lib/rggen/vhdl/bit_field/type/rof.erb
 - lib/rggen/vhdl/bit_field/type/rof.rb
-- lib/rggen/vhdl/bit_field/type/rol.erb
-- lib/rggen/vhdl/bit_field/type/rol.rb
+- lib/rggen/vhdl/bit_field/type/rohw.erb
+- lib/rggen/vhdl/bit_field/type/rohw.rb
 - lib/rggen/vhdl/bit_field/type/row0trg_row1trg.erb
 - lib/rggen/vhdl/bit_field/type/row0trg_row1trg.rb
 - lib/rggen/vhdl/bit_field/type/rowo_rowotrg.erb
@@ -58,6 +58,8 @@ files:
 - lib/rggen/vhdl/bit_field/type/rwc.rb
 - lib/rggen/vhdl/bit_field/type/rwe_rwl.erb
 - lib/rggen/vhdl/bit_field/type/rwe_rwl.rb
+- lib/rggen/vhdl/bit_field/type/rwhw.erb
+- lib/rggen/vhdl/bit_field/type/rwhw.rb
 - lib/rggen/vhdl/bit_field/type/rws.erb
 - lib/rggen/vhdl/bit_field/type/rws.rb
 - lib/rggen/vhdl/bit_field/type/w0crs_w0src_w1crs_w1src_wcrs_wsrc.erb
@@ -126,5 +128,5 @@ requirements: []
 rubygems_version: 3.5.3
 signing_key: 
 specification_version: 4
-summary: rggen-vhdl-0.8.0
+summary: rggen-vhdl-0.9.0
 test_files: []