rggen-vhdl 0.8.0 → 0.10.0

checksums.yaml

@@ -1,7 +1,7 @@
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data/LICENSE

@@ -1,6 +1,6 @@
 The MIT License (MIT)
 
-Copyright (c) 2021-2023 Taichi Ishitani
+Copyright (c) 2021-2024 Taichi Ishitani
 
 Permission is hereby granted, free of charge, to any person obtaining a copy
 of this software and associated documentation files (the "Software"), to deal

data/README.md

@@ -68,7 +68,7 @@ Feedbacks, bus reports, questions and etc. are welcome! You can post them bu usi
 
 ## Copyright & License
 
-Copyright © 2021-2023 Taichi Ishitani. RgGen::VHDL is licensed under the [MIT License](https://opensource.org/licenses/MIT), see [LICENSE](LICENSE) for futher details.
+Copyright © 2021-2024 Taichi Ishitani. RgGen::VHDL is licensed under the [MIT License](https://opensource.org/licenses/MIT), see [LICENSE](LICENSE) for futher details.
 
 ## Code of Conduct
 

data/lib/rggen/vhdl/bit_field/type/custom.erb

@@ -1,4 +1,4 @@
-u_bit_field: entity work.rggen_bit_field
+u_bit_field: entity <%= library_name %>.rggen_bit_field
   generic map (
     WIDTH               => <%= width %>,
     INITIAL_VALUE       => <%= initial_value %>,

data/lib/rggen/vhdl/bit_field/type/rc_w0c_w1c_wc_woc.erb

@@ -1,4 +1,4 @@
-u_bit_field: entity work.rggen_bit_field
+u_bit_field: entity <%= library_name %>.rggen_bit_field
   generic map (
     WIDTH           => <%= width %>,
     INITIAL_VALUE   => <%= initial_value %>,

data/lib/rggen/vhdl/bit_field/type/ro_rotrg.erb

@@ -1,4 +1,4 @@
-u_bit_field: entity work.rggen_bit_field
+u_bit_field: entity <%= library_name %>.rggen_bit_field
   generic map (
     WIDTH               => <%= width %>,
     STORAGE             => false,

data/lib/rggen/vhdl/bit_field/type/rof.erb

@@ -1,4 +1,4 @@
-u_bit_field: entity work.rggen_bit_field
+u_bit_field: entity <%= library_name %>.rggen_bit_field
   generic map (
     WIDTH               => <%= width %>,
     STORAGE             => false,

data/lib/rggen/vhdl/bit_field/type/{rol.erb → rohw.erb}

@@ -1,4 +1,4 @@
-u_bit_field: entity work.rggen_bit_field
+u_bit_field: entity <%= library_name %>.rggen_bit_field
   generic map (
     WIDTH           => <%= width %>,
     INITIAL_VALUE   => <%= initial_value %>,
@@ -16,7 +16,7 @@ u_bit_field: entity work.rggen_bit_field
     o_sw_value        => <%= bit_field_value %>,
     o_write_trigger   => open,
     o_read_trigger    => open,
-    i_hw_write_enable => <%= latch_signal %>,
+    i_hw_write_enable => <%= valid_signal %>,
     i_hw_write_data   => <%= value_in[loop_variables] %>,
     i_hw_set          => (others => '0'),
     i_hw_clear        => (others => '0'),

data/lib/rggen/vhdl/bit_field/type/{rol.rb → rohw.rb}

@@ -1,11 +1,11 @@
 # frozen_string_literal: true
 
-RgGen.define_list_item_feature(:bit_field, :type, :rol) do
+RgGen.define_list_item_feature(:bit_field, :type, :rohw) do
   vhdl do
     build do
       unless bit_field.reference?
-        input :latch, {
-          name: "i_#{full_name}_latch", width: 1, array_size: array_size
+        input :valid, {
+          name: "i_#{full_name}_valid", width: 1, array_size: array_size
         }
       end
       input :value_in, {
@@ -20,8 +20,8 @@ RgGen.define_list_item_feature(:bit_field, :type, :rol) do
 
     private
 
-    def latch_signal
-      reference_bit_field || latch[loop_variables]
+    def valid_signal
+      reference_bit_field || valid[loop_variables]
     end
   end
 end

data/lib/rggen/vhdl/bit_field/type/row0trg_row1trg.erb

@@ -1,4 +1,4 @@
-u_bit_field: entity work.rggen_bit_field_w01trg
+u_bit_field: entity <%= library_name %>.rggen_bit_field_w01trg
   generic map (
     WRITE_ONE_TRIGGER => <%= write_one_trigger? %>,
     WIDTH             => <%= width %>

data/lib/rggen/vhdl/bit_field/type/rowo_rowotrg.erb

@@ -1,4 +1,4 @@
-u_bit_field: entity work.rggen_bit_field
+u_bit_field: entity <%= library_name %>.rggen_bit_field
   generic map (
     WIDTH               => <%= width %>,
     INITIAL_VALUE       => <%= initial_value %>,

data/lib/rggen/vhdl/bit_field/type/rs_w0s_w1s_ws_wos.erb

@@ -1,4 +1,4 @@
-u_bit_field: entity work.rggen_bit_field
+u_bit_field: entity <%= library_name %>.rggen_bit_field
   generic map (
     WIDTH           => <%= width %>,
     INITIAL_VALUE   => <%= initial_value %>,

data/lib/rggen/vhdl/bit_field/type/rw_rwtrg_w1.erb

@@ -1,4 +1,4 @@
-u_bit_field: entity work.rggen_bit_field
+u_bit_field: entity <%= library_name %>.rggen_bit_field
   generic map (
     WIDTH           => <%= width %>,
     INITIAL_VALUE   => <%= initial_value %>,

data/lib/rggen/vhdl/bit_field/type/rwc.erb

@@ -1,4 +1,4 @@
-u_bit_field: entity work.rggen_bit_field
+u_bit_field: entity <%= library_name %>.rggen_bit_field
   generic map (
     WIDTH           => <%= width %>,
     INITIAL_VALUE   => <%= initial_value %>,

data/lib/rggen/vhdl/bit_field/type/rwe_rwl.erb

@@ -1,4 +1,4 @@
-u_bit_field: entity work.rggen_bit_field
+u_bit_field: entity <%= library_name %>.rggen_bit_field
   generic map (
     WIDTH                     => <%= width %>,
     INITIAL_VALUE             => <%= initial_value %>,

data/lib/rggen/vhdl/bit_field/type/rwhw.erb

@@ -0,0 +1,26 @@
+u_bit_field: entity <%= library_name %>.rggen_bit_field
+  generic map (
+    WIDTH         => <%= width %>,
+    INITIAL_VALUE => <%= initial_value %>
+  )
+  port map (
+    i_clk             => <%= clock %>,
+    i_rst_n           => <%= reset %>,
+    i_sw_valid        => <%= bit_field_valid %>,
+    i_sw_read_mask    => <%= bit_field_read_mask %>,
+    i_sw_write_enable => "1",
+    i_sw_write_mask   => <%= bit_field_write_mask %>,
+    i_sw_write_data   => <%= bit_field_write_data %>,
+    o_sw_read_data    => <%= bit_field_read_data %>,
+    o_sw_value        => <%= bit_field_value %>,
+    o_write_trigger   => open,
+    o_read_trigger    => open,
+    i_hw_write_enable => <%= valid_signal %>,
+    i_hw_write_data   => <%= value_in[loop_variables] %>,
+    i_hw_set          => (others => '0'),
+    i_hw_clear        => (others => '0'),
+    i_value           => (others => '0'),
+    i_mask            => (others => '1'),
+    o_value           => <%= value_out[loop_variables] %>,
+    o_value_unmasked  => open
+  );

data/lib/rggen/vhdl/bit_field/type/rwhw.rb

@@ -0,0 +1,27 @@
+# frozen_string_literal: true
+
+RgGen.define_list_item_feature(:bit_field, :type, :rwhw) do
+  vhdl do
+    build do
+      unless bit_field.reference?
+        input :valid, {
+          name: "i_#{full_name}_valid", width: 1, array_size: array_size
+        }
+      end
+      input :value_in, {
+        name: "i_#{full_name}", width: width, array_size: array_size
+      }
+      output :value_out, {
+        name: "o_#{full_name}", width: width, array_size: array_size
+      }
+    end
+
+    main_code :bit_field, from_template: true
+
+    private
+
+    def valid_signal
+      reference_bit_field || valid[loop_variables]
+    end
+  end
+end

data/lib/rggen/vhdl/bit_field/type/rws.erb

@@ -1,7 +1,8 @@
-u_bit_field: entity work.rggen_bit_field
+u_bit_field: entity <%= library_name %>.rggen_bit_field
   generic map (
     WIDTH         => <%= width %>,
-    INITIAL_VALUE => <%= initial_value %>
+    INITIAL_VALUE => <%= initial_value %>,
+    HW_SET_WIDTH  => 1
   )
   port map (
     i_clk             => <%= clock %>,
@@ -15,9 +16,9 @@ u_bit_field: entity work.rggen_bit_field
     o_sw_value        => <%= bit_field_value %>,
     o_write_trigger   => open,
     o_read_trigger    => open,
-    i_hw_write_enable => <%= set_signal %>,
-    i_hw_write_data   => <%= value_in[loop_variables] %>,
-    i_hw_set          => (others => '0'),
+    i_hw_write_enable => "0",
+    i_hw_write_data   => (others => '0'),
+    i_hw_set          => <%= set_signal %>,
     i_hw_clear        => (others => '0'),
     i_value           => (others => '0'),
     i_mask            => (others => '1'),

data/lib/rggen/vhdl/bit_field/type/rws.rb

@@ -8,9 +8,6 @@ RgGen.define_list_item_feature(:bit_field, :type, :rws) do
           name: "i_#{full_name}_set", width: 1, array_size: array_size
         }
       end
-      input :value_in, {
-        name: "i_#{full_name}", width: width, array_size: array_size
-      }
       output :value_out, {
         name: "o_#{full_name}", width: width, array_size: array_size
       }

data/lib/rggen/vhdl/bit_field/type/w0crs_w0src_w1crs_w1src_wcrs_wsrc.erb

@@ -1,4 +1,4 @@
-u_bit_field: entity work.rggen_bit_field
+u_bit_field: entity <%= library_name %>.rggen_bit_field
   generic map (
     WIDTH           => <%= width %>,
     INITIAL_VALUE   => <%= initial_value %>,

data/lib/rggen/vhdl/bit_field/type/w0t_w1t.erb

@@ -1,4 +1,4 @@
-u_bit_field: entity work.rggen_bit_field
+u_bit_field: entity <%= library_name %>.rggen_bit_field
   generic map (
     WIDTH           => <%= width %>,
     INITIAL_VALUE   => <%= initial_value %>,

data/lib/rggen/vhdl/bit_field/type/w0trg_w1trg.erb

@@ -1,4 +1,4 @@
-u_bit_field: entity work.rggen_bit_field_w01trg
+u_bit_field: entity <%= library_name %>.rggen_bit_field_w01trg
   generic map (
     WRITE_ONE_TRIGGER => <%= write_one_trigger? %>,
     WIDTH             => <%= width %>

data/lib/rggen/vhdl/bit_field/type/wo_wo1_wotrg.erb

@@ -1,4 +1,4 @@
-u_bit_field: entity work.rggen_bit_field
+u_bit_field: entity <%= library_name %>.rggen_bit_field
   generic map (
     WIDTH           => <%= width %>,
     INITIAL_VALUE   => <%= initial_value %>,

data/lib/rggen/vhdl/bit_field/type/wrc_wrs.erb

@@ -1,4 +1,4 @@
-u_bit_field: entity work.rggen_bit_field
+u_bit_field: entity <%= library_name %>.rggen_bit_field
   generic map (
     WIDTH           => <%= width %>,
     INITIAL_VALUE   => <%= initial_value %>,

data/lib/rggen/vhdl/bit_field/type.rb

@@ -5,6 +5,10 @@ RgGen.define_list_feature(:bit_field, :type) do
     base_feature do
       private
 
+      def library_name
+        configuration.library_name
+      end
+
       def full_name
         bit_field.full_name('_')
       end

data/lib/rggen/vhdl/global/library_name.rb

@@ -0,0 +1,16 @@
+# frozen_string_literal: true
+
+RgGen.define_simple_feature(:global, :library_name) do
+  configuration do
+    property :library_name, default: 'work'
+    property :use_default_library?, body: -> { library_name.casecmp?('work') }
+
+    input_pattern variable_name
+
+    build do |value|
+      pattern_matched? ||
+        (error "illegal input value for library name: #{value.inspect}")
+      @library_name = match_data.to_s
+    end
+  end
+end

data/lib/rggen/vhdl/register/type/default.erb

@@ -1,4 +1,4 @@
-u_register: entity work.rggen_default_register
+u_register: entity <%= library_name %>.rggen_default_register
   generic map (
     READABLE        => <%= readable? %>,
     WRITABLE        => <%= writable? %>,

data/lib/rggen/vhdl/register/type/external.erb

@@ -1,4 +1,4 @@
-u_register: entity work.rggen_external_register
+u_register: entity <%= library_name %>.rggen_external_register
   generic map (
     ADDRESS_WIDTH => <%= address_width %>,
     BUS_WIDTH     => <%= bus_width %>,

data/lib/rggen/vhdl/register/type/indirect.erb

@@ -1,7 +1,7 @@
 <% index_fields_and_values.each_with_index do |(field, value), i| %>
 <%= indirect_match[i] %> <= '1' when unsigned(<%= field %>) = <%= value %> else '0';
 <% end %>
-u_register: entity work.rggen_indirect_register
+u_register: entity <%= library_name %>.rggen_indirect_register
   generic map (
     READABLE              => <%= readable? %>,
     WRITABLE              => <%= writable? %>,

data/lib/rggen/vhdl/register/type/rw.erb

@@ -1,4 +1,4 @@
-u_register: entity work.rggen_default_register
+u_register: entity <%= library_name %>.rggen_default_register
   generic map (
     READABLE        => true,
     WRITABLE        => true,

data/lib/rggen/vhdl/register/type.rb

@@ -20,6 +20,10 @@ RgGen.define_list_feature(:register, :type) do
         register.writable?
       end
 
+      def library_name
+        configuration.library_name
+      end
+
       def clock
         register_block.clock
       end
@@ -91,6 +95,14 @@ RgGen.define_list_feature(:register, :type) do
       def bit_field_value
         register.bit_field_value
       end
+
+      def format_offsets(offsets)
+        if integer?(offsets.first)
+          super(offsets)
+        else
+          super([0, *offsets])
+        end
+      end
     end
 
     default_feature do

data/lib/rggen/vhdl/register_block/protocol/apb.erb

@@ -1,4 +1,4 @@
-u_adapter: entity work.rggen_apb_adaper
+u_adapter: entity <%= library_name %>.rggen_apb_adaper
   generic map (
     ADDRESS_WIDTH       => <%= address_width %>,
     LOCAL_ADDRESS_WIDTH => <%= local_address_width %>,

data/lib/rggen/vhdl/register_block/protocol/axi4lite.erb

@@ -1,4 +1,4 @@
-u_adapter: entity work.rggen_axi4lite_adapter
+u_adapter: entity <%= library_name %>.rggen_axi4lite_adapter
   generic map (
     ID_WIDTH            => <%= id_width %>,
     ADDRESS_WIDTH       => <%= address_width %>,

data/lib/rggen/vhdl/register_block/protocol/wishbone.erb

@@ -1,4 +1,4 @@
-u_adapter: entity work.rggen_wishbone_adapter
+u_adapter: entity <%= library_name %>.rggen_wishbone_adapter
   generic map (
     ADDRESS_WIDTH       => <%= address_width %>,
     LOCAL_ADDRESS_WIDTH => <%= local_address_width %>,

data/lib/rggen/vhdl/register_block/protocol.rb

@@ -25,6 +25,10 @@ RgGen.define_list_feature(:register_block, :protocol) do
 
       private
 
+      def library_name
+        configuration.library_name
+      end
+
       def bus_width
         configuration.bus_width
       end

data/lib/rggen/vhdl/register_block/vhdl_top.erb

@@ -2,7 +2,10 @@ library ieee;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;
 
-use work.rggen_rtl.all;
+<% unless use_default_library? %>
+library <%= library_name %>;
+<% end %>
+use <%= library_name %>.rggen_rtl.all;
 
 entity <%= register_block.name %> is
   generic (

data/lib/rggen/vhdl/register_block/vhdl_top.rb

@@ -42,6 +42,14 @@ RgGen.define_simple_feature(:register_block, :vhdl_top) do
 
     private
 
+    def use_default_library?
+      configuration.use_default_library?
+    end
+
+    def library_name
+      configuration.library_name
+    end
+
     def total_registers
       register_block.files_and_registers.sum(&:count)
     end

data/lib/rggen/vhdl/version.rb

@@ -2,6 +2,6 @@
 
 module RgGen
   module VHDL
-    VERSION = '0.8.0'
+    VERSION = '0.10.0'
   end
 end

data/lib/rggen/vhdl.rb

@@ -21,6 +21,7 @@ RgGen.setup_plugin :'rggen-vhdl' do |plugin|
   end
 
   plugin.files [
+    'vhdl/global/library_name',
     'vhdl/register_block/vhdl_top',
     'vhdl/register_block/protocol',
     'vhdl/register_block/protocol/apb',
@@ -38,13 +39,14 @@ RgGen.setup_plugin :'rggen-vhdl' do |plugin|
     'vhdl/bit_field/type/rc_w0c_w1c_wc_woc',
     'vhdl/bit_field/type/ro_rotrg',
     'vhdl/bit_field/type/rof',
-    'vhdl/bit_field/type/rol',
+    'vhdl/bit_field/type/rohw',
     'vhdl/bit_field/type/row0trg_row1trg',
     'vhdl/bit_field/type/rowo_rowotrg',
     'vhdl/bit_field/type/rs_w0s_w1s_ws_wos',
     'vhdl/bit_field/type/rw_rwtrg_w1',
     'vhdl/bit_field/type/rwc',
     'vhdl/bit_field/type/rwe_rwl',
+    'vhdl/bit_field/type/rwhw',
     'vhdl/bit_field/type/rws',
     'vhdl/bit_field/type/w0crs_w0src_w1crs_w1src_wcrs_wsrc',
     'vhdl/bit_field/type/w0t_w1t',

metadata

@@ -1,14 +1,14 @@
 --- !ruby/object:Gem::Specification
 name: rggen-vhdl
 version: !ruby/object:Gem::Version
-  version: 0.8.0
+  version: 0.10.0
 platform: ruby
 authors:
 - Taichi Ishitani
 autorequire: 
 bindir: bin
 cert_chain: []
-date: 2023-12-28 00:00:00.000000000 Z
+date: 2024-02-28 00:00:00.000000000 Z
 dependencies:
 - !ruby/object:Gem::Dependency
   name: rggen-systemverilog
@@ -16,14 +16,14 @@ dependencies:
     requirements:
     - - ">="
       - !ruby/object:Gem::Version
-        version: 0.32.0
+        version: 0.33.0
   type: :runtime
   prerelease: false
   version_requirements: !ruby/object:Gem::Requirement
     requirements:
     - - ">="
       - !ruby/object:Gem::Version
-        version: 0.32.0
+        version: 0.33.0
 description: VHDL writer plugin for RgGen
 email:
 - rggen@googlegroups.com
@@ -44,8 +44,8 @@ files:
 - lib/rggen/vhdl/bit_field/type/ro_rotrg.rb
 - lib/rggen/vhdl/bit_field/type/rof.erb
 - lib/rggen/vhdl/bit_field/type/rof.rb
-- lib/rggen/vhdl/bit_field/type/rol.erb
-- lib/rggen/vhdl/bit_field/type/rol.rb
+- lib/rggen/vhdl/bit_field/type/rohw.erb
+- lib/rggen/vhdl/bit_field/type/rohw.rb
 - lib/rggen/vhdl/bit_field/type/row0trg_row1trg.erb
 - lib/rggen/vhdl/bit_field/type/row0trg_row1trg.rb
 - lib/rggen/vhdl/bit_field/type/rowo_rowotrg.erb
@@ -58,6 +58,8 @@ files:
 - lib/rggen/vhdl/bit_field/type/rwc.rb
 - lib/rggen/vhdl/bit_field/type/rwe_rwl.erb
 - lib/rggen/vhdl/bit_field/type/rwe_rwl.rb
+- lib/rggen/vhdl/bit_field/type/rwhw.erb
+- lib/rggen/vhdl/bit_field/type/rwhw.rb
 - lib/rggen/vhdl/bit_field/type/rws.erb
 - lib/rggen/vhdl/bit_field/type/rws.rb
 - lib/rggen/vhdl/bit_field/type/w0crs_w0src_w1crs_w1src_wcrs_wsrc.erb
@@ -74,6 +76,7 @@ files:
 - lib/rggen/vhdl/component.rb
 - lib/rggen/vhdl/factories.rb
 - lib/rggen/vhdl/feature.rb
+- lib/rggen/vhdl/global/library_name.rb
 - lib/rggen/vhdl/register/tie_off_unused_signals.erb
 - lib/rggen/vhdl/register/type.rb
 - lib/rggen/vhdl/register/type/default.erb
@@ -123,8 +126,8 @@ required_rubygems_version: !ruby/object:Gem::Requirement
     - !ruby/object:Gem::Version
       version: '0'
 requirements: []
-rubygems_version: 3.5.3
+rubygems_version: 3.5.5
 signing_key: 
 specification_version: 4
-summary: rggen-vhdl-0.8.0
+summary: rggen-vhdl-0.10.0
 test_files: []