rggen-vhdl 0.6.1 → 0.8.0

checksums.yaml

@@ -1,7 +1,7 @@
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data/lib/rggen/vhdl/register/type/external.erb

@@ -2,6 +2,7 @@ u_register: entity work.rggen_external_register
   generic map (
     ADDRESS_WIDTH => <%= address_width %>,
     BUS_WIDTH     => <%= bus_width %>,
+    STROBE_WIDTH  => <%= strobe_width %>,
     START_ADDRESS => <%= start_address %>,
     BYTE_SIZE     => <%= byte_size %>
   )

data/lib/rggen/vhdl/register/type/external.rb

@@ -3,6 +3,10 @@
 RgGen.define_list_item_feature(:register, :type, :external) do
   vhdl do
     build do
+      generic :strobe_width, {
+        name: "#{register.name}_STROBE_WIDTH".upcase,
+        type: :positive, default: configuration.bus_width / 8
+      }
       output :external_valid, {
         name: "o_#{register.name}_valid"
       }
@@ -16,7 +20,7 @@ RgGen.define_list_item_feature(:register, :type, :external) do
         name: "o_#{register.name}_data", width: bus_width
       }
       output :external_strobe, {
-        name: "o_#{register.name}_strobe", width: bus_width / 8
+        name: "o_#{register.name}_strobe", width: strobe_width
       }
       input :external_ready, {
         name: "i_#{register.name}_ready"

data/lib/rggen/vhdl/register/type/rw.erb

@@ -0,0 +1,29 @@
+u_register: entity work.rggen_default_register
+  generic map (
+    READABLE        => true,
+    WRITABLE        => true,
+    ADDRESS_WIDTH   => <%= address_width %>,
+    OFFSET_ADDRESS  => <%= offset_address %>,
+    BUS_WIDTH       => <%= bus_width %>,
+    DATA_WIDTH      => <%= width %>
+  )
+  port map (
+    i_clk                   => <%= clock %>,
+    i_rst_n                 => <%= reset %>,
+    i_register_valid        => <%= register_valid %>,
+    i_register_access       => <%= register_access %>,
+    i_register_address      => <%= register_address %>,
+    i_register_write_data   => <%= register_write_data %>,
+    i_register_strobe       => <%= register_strobe %>,
+    o_register_active       => <%= register_active %>,
+    o_register_ready        => <%= register_ready %>,
+    o_register_status       => <%= register_status %>,
+    o_register_read_data    => <%= register_read_data %>,
+    o_register_value        => <%= register_value %>,
+    o_bit_field_valid       => <%= bit_field_valid %>,
+    o_bit_field_read_mask   => <%= bit_field_read_mask %>,
+    o_bit_field_write_mask  => <%= bit_field_write_mask %>,
+    o_bit_field_write_data  => <%= bit_field_write_data %>,
+    i_bit_field_read_data   => <%= bit_field_read_data %>,
+    i_bit_field_value       => <%= bit_field_value %>
+  );

data/lib/rggen/vhdl/register/type/rw.rb

@@ -0,0 +1,7 @@
+# frozen_string_literal: true
+
+RgGen.define_list_item_feature(:register, :type, :rw) do
+  vhdl do
+    main_code :register, from_template: true
+  end
+end

data/lib/rggen/vhdl/register_block/vhdl_top.rb

@@ -17,7 +17,7 @@ RgGen.define_simple_feature(:register_block, :vhdl_top) do
         width: bus_width
       }
       signal :register_strobe, {
-        width: bus_width / 8
+        width: bus_width
       }
       signal :register_active, {
         array_size: [total_registers]

data/lib/rggen/vhdl/version.rb

@@ -2,6 +2,6 @@
 
 module RgGen
   module VHDL
-    VERSION = '0.6.1'
+    VERSION = '0.8.0'
   end
 end

data/lib/rggen/vhdl.rb

@@ -31,6 +31,7 @@ RgGen.setup_plugin :'rggen-vhdl' do |plugin|
     'vhdl/register/type',
     'vhdl/register/type/external',
     'vhdl/register/type/indirect',
+    'vhdl/register/type/rw',
     'vhdl/bit_field/vhdl_top',
     'vhdl/bit_field/type',
     'vhdl/bit_field/type/custom',

metadata

@@ -1,14 +1,14 @@
 --- !ruby/object:Gem::Specification
 name: rggen-vhdl
 version: !ruby/object:Gem::Version
-  version: 0.6.1
+  version: 0.8.0
 platform: ruby
 authors:
 - Taichi Ishitani
 autorequire: 
 bindir: bin
 cert_chain: []
-date: 2023-06-09 00:00:00.000000000 Z
+date: 2023-12-28 00:00:00.000000000 Z
 dependencies:
 - !ruby/object:Gem::Dependency
   name: rggen-systemverilog
@@ -16,28 +16,14 @@ dependencies:
     requirements:
     - - ">="
       - !ruby/object:Gem::Version
-        version: 0.30.1
+        version: 0.32.0
   type: :runtime
   prerelease: false
   version_requirements: !ruby/object:Gem::Requirement
     requirements:
     - - ">="
       - !ruby/object:Gem::Version
-        version: 0.30.1
-- !ruby/object:Gem::Dependency
-  name: bundler
-  requirement: !ruby/object:Gem::Requirement
-    requirements:
-    - - ">="
-      - !ruby/object:Gem::Version
-        version: '0'
-  type: :development
-  prerelease: false
-  version_requirements: !ruby/object:Gem::Requirement
-    requirements:
-    - - ">="
-      - !ruby/object:Gem::Version
-        version: '0'
+        version: 0.32.0
 description: VHDL writer plugin for RgGen
 email:
 - rggen@googlegroups.com
@@ -95,6 +81,8 @@ files:
 - lib/rggen/vhdl/register/type/external.rb
 - lib/rggen/vhdl/register/type/indirect.erb
 - lib/rggen/vhdl/register/type/indirect.rb
+- lib/rggen/vhdl/register/type/rw.erb
+- lib/rggen/vhdl/register/type/rw.rb
 - lib/rggen/vhdl/register/vhdl_top.rb
 - lib/rggen/vhdl/register_block/protocol.rb
 - lib/rggen/vhdl/register_block/protocol/apb.erb
@@ -128,15 +116,15 @@ required_ruby_version: !ruby/object:Gem::Requirement
   requirements:
   - - ">="
     - !ruby/object:Gem::Version
-      version: 2.7.0
+      version: 3.0.0
 required_rubygems_version: !ruby/object:Gem::Requirement
   requirements:
   - - ">="
     - !ruby/object:Gem::Version
       version: '0'
 requirements: []
-rubygems_version: 3.4.10
+rubygems_version: 3.5.3
 signing_key: 
 specification_version: 4
-summary: rggen-vhdl-0.6.1
+summary: rggen-vhdl-0.8.0
 test_files: []