rggen-vhdl 0.6.1 → 0.7.0

checksums.yaml

@@ -1,7 +1,7 @@
 ---
 SHA256:
-  metadata.gz: 8a722ba50ddeb4d183734a880ecae7b0f8677d2314c6a192381602423d792727
-  data.tar.gz: 88c8b14b0e942aaae285bd114c2a8d6b2f9c985d7ac375aa1f323428a9cafebe
+  metadata.gz: 4faaef428fbba048c4000898fc4bb25625d9734eec168da0b7e276250fd1458a
+  data.tar.gz: 01b24c92db5237ce7e6e712323b344fc1b99dcac793344d776a1dbe4eef6af25
 SHA512:
-  metadata.gz: 7965c9b5838750fefcf84ca7b3b2c4318687588368ec8b3d2c564fd73b23c3272a0059410c037a370fbd1c7f49e7d8e12931f9ac5c2fa13f6cb9a99ebebe5a79
-  data.tar.gz: ca18b18a63b826b2114e485eca9b14edc75175b62e433815f94ebafc8218a00cbe1b07dc9ffc028e625e774fb865e4475dd4b19cb9912fd881f885d1c735a280
+  metadata.gz: 9a8e30cc40d73c1f74be2c121e4730c8d79fcae51ff9404e8815d16d1e719d5089b418493a973899c8263c0873fe55c5d3139fa0ef3808f083707edd4374d7b9
+  data.tar.gz: 894de4ef4fda8f945455fb1555ff8583abb84cadaf47cdf1552b1e048020de544f4682617ace6cea1979f3d8628ee50fb72c2cbdad483f9216ec9dfb91dd77b3

data/lib/rggen/vhdl/register/type/external.erb

@@ -2,6 +2,7 @@ u_register: entity work.rggen_external_register
   generic map (
     ADDRESS_WIDTH => <%= address_width %>,
     BUS_WIDTH     => <%= bus_width %>,
+    STROBE_WIDTH  => <%= strobe_width %>,
     START_ADDRESS => <%= start_address %>,
     BYTE_SIZE     => <%= byte_size %>
   )

data/lib/rggen/vhdl/register/type/external.rb

@@ -3,6 +3,10 @@
 RgGen.define_list_item_feature(:register, :type, :external) do
   vhdl do
     build do
+      generic :strobe_width, {
+        name: "#{register.name}_STROBE_WIDTH".upcase,
+        type: :positive, default: configuration.bus_width / 8
+      }
       output :external_valid, {
         name: "o_#{register.name}_valid"
       }
@@ -16,7 +20,7 @@ RgGen.define_list_item_feature(:register, :type, :external) do
         name: "o_#{register.name}_data", width: bus_width
       }
       output :external_strobe, {
-        name: "o_#{register.name}_strobe", width: bus_width / 8
+        name: "o_#{register.name}_strobe", width: strobe_width
       }
       input :external_ready, {
         name: "i_#{register.name}_ready"

data/lib/rggen/vhdl/register/type/rw.erb

@@ -0,0 +1,29 @@
+u_register: entity work.rggen_default_register
+  generic map (
+    READABLE        => true,
+    WRITABLE        => true,
+    ADDRESS_WIDTH   => <%= address_width %>,
+    OFFSET_ADDRESS  => <%= offset_address %>,
+    BUS_WIDTH       => <%= bus_width %>,
+    DATA_WIDTH      => <%= width %>
+  )
+  port map (
+    i_clk                   => <%= clock %>,
+    i_rst_n                 => <%= reset %>,
+    i_register_valid        => <%= register_valid %>,
+    i_register_access       => <%= register_access %>,
+    i_register_address      => <%= register_address %>,
+    i_register_write_data   => <%= register_write_data %>,
+    i_register_strobe       => <%= register_strobe %>,
+    o_register_active       => <%= register_active %>,
+    o_register_ready        => <%= register_ready %>,
+    o_register_status       => <%= register_status %>,
+    o_register_read_data    => <%= register_read_data %>,
+    o_register_value        => <%= register_value %>,
+    o_bit_field_valid       => <%= bit_field_valid %>,
+    o_bit_field_read_mask   => <%= bit_field_read_mask %>,
+    o_bit_field_write_mask  => <%= bit_field_write_mask %>,
+    o_bit_field_write_data  => <%= bit_field_write_data %>,
+    i_bit_field_read_data   => <%= bit_field_read_data %>,
+    i_bit_field_value       => <%= bit_field_value %>
+  );

data/lib/rggen/vhdl/register/type/rw.rb

@@ -0,0 +1,7 @@
+# frozen_string_literal: true
+
+RgGen.define_list_item_feature(:register, :type, :rw) do
+  vhdl do
+    main_code :register, from_template: true
+  end
+end

data/lib/rggen/vhdl/register_block/vhdl_top.rb

@@ -17,7 +17,7 @@ RgGen.define_simple_feature(:register_block, :vhdl_top) do
         width: bus_width
       }
       signal :register_strobe, {
-        width: bus_width / 8
+        width: bus_width
       }
       signal :register_active, {
         array_size: [total_registers]

data/lib/rggen/vhdl/version.rb

@@ -2,6 +2,6 @@
 
 module RgGen
   module VHDL
-    VERSION = '0.6.1'
+    VERSION = '0.7.0'
   end
 end

data/lib/rggen/vhdl.rb

@@ -31,6 +31,7 @@ RgGen.setup_plugin :'rggen-vhdl' do |plugin|
     'vhdl/register/type',
     'vhdl/register/type/external',
     'vhdl/register/type/indirect',
+    'vhdl/register/type/rw',
     'vhdl/bit_field/vhdl_top',
     'vhdl/bit_field/type',
     'vhdl/bit_field/type/custom',

metadata

@@ -1,14 +1,14 @@
 --- !ruby/object:Gem::Specification
 name: rggen-vhdl
 version: !ruby/object:Gem::Version
-  version: 0.6.1
+  version: 0.7.0
 platform: ruby
 authors:
 - Taichi Ishitani
 autorequire: 
 bindir: bin
 cert_chain: []
-date: 2023-06-09 00:00:00.000000000 Z
+date: 2023-09-12 00:00:00.000000000 Z
 dependencies:
 - !ruby/object:Gem::Dependency
   name: rggen-systemverilog
@@ -16,14 +16,14 @@ dependencies:
     requirements:
     - - ">="
       - !ruby/object:Gem::Version
-        version: 0.30.1
+        version: 0.31.0
   type: :runtime
   prerelease: false
   version_requirements: !ruby/object:Gem::Requirement
     requirements:
     - - ">="
       - !ruby/object:Gem::Version
-        version: 0.30.1
+        version: 0.31.0
 - !ruby/object:Gem::Dependency
   name: bundler
   requirement: !ruby/object:Gem::Requirement
@@ -95,6 +95,8 @@ files:
 - lib/rggen/vhdl/register/type/external.rb
 - lib/rggen/vhdl/register/type/indirect.erb
 - lib/rggen/vhdl/register/type/indirect.rb
+- lib/rggen/vhdl/register/type/rw.erb
+- lib/rggen/vhdl/register/type/rw.rb
 - lib/rggen/vhdl/register/vhdl_top.rb
 - lib/rggen/vhdl/register_block/protocol.rb
 - lib/rggen/vhdl/register_block/protocol/apb.erb
@@ -135,8 +137,8 @@ required_rubygems_version: !ruby/object:Gem::Requirement
     - !ruby/object:Gem::Version
       version: '0'
 requirements: []
-rubygems_version: 3.4.10
+rubygems_version: 3.4.17
 signing_key: 
 specification_version: 4
-summary: rggen-vhdl-0.6.1
+summary: rggen-vhdl-0.7.0
 test_files: []