rggen-vhdl 0.5.0 → 0.6.1

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checksums.yaml CHANGED
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@@ -5,8 +5,7 @@ u_register: entity work.rggen_default_register
5
5
  ADDRESS_WIDTH => <%= address_width %>,
6
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  OFFSET_ADDRESS => <%= offset_address %>,
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  BUS_WIDTH => <%= bus_width %>,
8
- DATA_WIDTH => <%= width %>,
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- REGISTER_INDEX => <%= register_index %>
8
+ DATA_WIDTH => <%= width %>
10
9
  )
11
10
  port map (
12
11
  i_clk => <%= clock %>,
@@ -38,7 +38,7 @@ RgGen.define_list_item_feature(:register, :type, :external) do
38
38
  end
39
39
 
40
40
  def byte_size
41
- register.byte_size
41
+ register.total_byte_size
42
42
  end
43
43
  end
44
44
  end
@@ -7,7 +7,8 @@ u_adapter: entity work.rggen_apb_adaper
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  PRE_DECODE => <%= pre_decode %>,
8
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  BASE_ADDRESS => <%= base_address %>,
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  BYTE_SIZE => <%= byte_size %>,
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- ERROR_STATUS => <%= error_status %>
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+ ERROR_STATUS => <%= error_status %>,
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+ INSERT_SLICER => <%= insert_slicer %>
11
12
  )
12
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  port map (
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  i_clk => <%= register_block.clock %>,
@@ -9,6 +9,7 @@ u_adapter: entity work.rggen_axi4lite_adapter
9
9
  BASE_ADDRESS => <%= base_address %>,
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10
  BYTE_SIZE => <%= byte_size %>,
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11
  ERROR_STATUS => <%= error_status %>,
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+ INSERT_SLICER => <%= insert_slicer %>,
12
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  WRITE_FIRST => <%= write_first %>
13
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  )
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  port map (
@@ -8,6 +8,7 @@ u_adapter: entity work.rggen_wishbone_adapter
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  BASE_ADDRESS => <%= base_address %>,
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  BYTE_SIZE => <%= byte_size %>,
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10
  ERROR_STATUS => <%= error_status %>,
11
+ INSERT_SLICER => <%= insert_slicer %>,
11
12
  USE_STALL => <%= use_stall %>
12
13
  )
13
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  port map (
@@ -18,6 +18,9 @@ RgGen.define_list_feature(:register_block, :protocol) do
18
18
  generic :error_status, {
19
19
  name: 'ERROR_STATUS', type: :boolean, default: false
20
20
  }
21
+ generic :insert_slicer, {
22
+ name: 'INSERT_SLICER', type: :boolean, default: false
23
+ }
21
24
  end
22
25
 
23
26
  private
@@ -20,6 +20,10 @@ module RgGen
20
20
  format('x"%0*x"', print_width, value)
21
21
  end
22
22
 
23
+ def width_cast(expression, _width)
24
+ expression
25
+ end
26
+
23
27
  def local_scope(scope_name, attributes = {}, &block)
24
28
  LocalScope.new(attributes.merge(name: scope_name), &block).to_code
25
29
  end
@@ -2,6 +2,6 @@
2
2
 
3
3
  module RgGen
4
4
  module VHDL
5
- VERSION = '0.5.0'
5
+ VERSION = '0.6.1'
6
6
  end
7
7
  end
metadata CHANGED
@@ -1,14 +1,14 @@
1
1
  --- !ruby/object:Gem::Specification
2
2
  name: rggen-vhdl
3
3
  version: !ruby/object:Gem::Version
4
- version: 0.5.0
4
+ version: 0.6.1
5
5
  platform: ruby
6
6
  authors:
7
7
  - Taichi Ishitani
8
8
  autorequire:
9
9
  bindir: bin
10
10
  cert_chain: []
11
- date: 2023-01-02 00:00:00.000000000 Z
11
+ date: 2023-06-09 00:00:00.000000000 Z
12
12
  dependencies:
13
13
  - !ruby/object:Gem::Dependency
14
14
  name: rggen-systemverilog
@@ -16,14 +16,14 @@ dependencies:
16
16
  requirements:
17
17
  - - ">="
18
18
  - !ruby/object:Gem::Version
19
- version: 0.29.0
19
+ version: 0.30.1
20
20
  type: :runtime
21
21
  prerelease: false
22
22
  version_requirements: !ruby/object:Gem::Requirement
23
23
  requirements:
24
24
  - - ">="
25
25
  - !ruby/object:Gem::Version
26
- version: 0.29.0
26
+ version: 0.30.1
27
27
  - !ruby/object:Gem::Dependency
28
28
  name: bundler
29
29
  requirement: !ruby/object:Gem::Requirement
@@ -135,8 +135,8 @@ required_rubygems_version: !ruby/object:Gem::Requirement
135
135
  - !ruby/object:Gem::Version
136
136
  version: '0'
137
137
  requirements: []
138
- rubygems_version: 3.4.1
138
+ rubygems_version: 3.4.10
139
139
  signing_key:
140
140
  specification_version: 4
141
- summary: rggen-vhdl-0.5.0
141
+ summary: rggen-vhdl-0.6.1
142
142
  test_files: []