rggen-vhdl 0.3.0 → 0.5.0

checksums.yaml

@@ -1,7 +1,7 @@
 ---
 SHA256:
-  metadata.gz: a3fe2a4f117ebddd32c38f4e65d042c845f81e85f6130d7f85ebf94f7b12868f
-  data.tar.gz: 55c35ac2e82232c2fba80da4ec23ad0bb417cb35c228b3e94a76ee134f747f54
+  metadata.gz: bfbc3e77df9967bad391f1ba28fa45fd661d5e6ee25fb83ecd2761b1ccd6360b
+  data.tar.gz: '0486ecfb64a79e84d12b9ddd12168ae4c2324e8339505462c95fb2019b6e7432'
 SHA512:
-  metadata.gz: 1e1d50c4f6eea7cfd80de27beac4e2f451d8913d13b77976776e0c021252dc53da2aa1227ed5b587f905d30aa54d66437e4af795bc15cea9626f8a7076bc521f
-  data.tar.gz: 0fa49c35d10ddfe2c4d680780dd3f40ef0a8dc64aa4808cc352c55261ccf9d8d754aa450643bdacf1072b86f88ce880050851afcf09001a091ea25f0439353e3
+  metadata.gz: b6d6363e00f0ab0cb9100422b4471ea3584476565c277d26c82ffce58613cdaa1802f3e9a28f6289f3acf705a4a856b47aa0afb9a5c9ce47748d7521b6646251
+  data.tar.gz: 854335f3af36c2ee567928f3c130b00d41a6786a8ae301cd6c70f578320885b63e63336580a5d810b6018adfd3b28003050173817fc1ac7760a2589ced86c930

data/LICENSE

@@ -1,6 +1,6 @@
 The MIT License (MIT)
 
-Copyright (c) 2021 - 2022 Taichi Ishitani
+Copyright (c) 2021-2023 Taichi Ishitani
 
 Permission is hereby granted, free of charge, to any person obtaining a copy
 of this software and associated documentation files (the "Software"), to deal

data/README.md

@@ -68,7 +68,7 @@ Feedbacks, bus reports, questions and etc. are welcome! You can post them bu usi
 
 ## Copyright & License
 
-Copyright © 2021 - 2022 Taichi Ishitani. RgGen::VHDL is licensed under the [MIT License](https://opensource.org/licenses/MIT), see [LICENSE](LICENSE) for futher details.
+Copyright © 2021-2023 Taichi Ishitani. RgGen::VHDL is licensed under the [MIT License](https://opensource.org/licenses/MIT), see [LICENSE](LICENSE) for futher details.
 
 ## Code of Conduct
 

data/lib/rggen/vhdl/bit_field/type/custom.erb

@@ -0,0 +1,34 @@
+u_bit_field: entity work.rggen_bit_field
+  generic map (
+    WIDTH               => <%= width %>,
+    INITIAL_VALUE       => <%= initial_value %>,
+    SW_READ_ACTION      => <%= sw_read_action %>,
+    SW_WRITE_ACTION     => <%= sw_write_action %>,
+    SW_WRITE_ONCE       => <%= bit_field.sw_write_once? %>,
+    HW_SET_WIDTH        => <%= width %>,
+    HW_CLEAR_WIDTH      => <%= width %>,
+    STORAGE             => <%= storage? %>,
+    EXTERNAL_READ_DATA  => <%= external_read_data? %>,
+    TRIGGER             => <%= trigger? %>
+  )
+  port map (
+    i_clk             => <%= clock %>,
+    i_rst_n           => <%= reset %>,
+    i_sw_valid        => <%= bit_field_valid %>,
+    i_sw_read_mask    => <%= bit_field_read_mask %>,
+    i_sw_write_enable => "1",
+    i_sw_write_mask   => <%= bit_field_write_mask %>,
+    i_sw_write_data   => <%= bit_field_write_data %>,
+    o_sw_read_data    => <%= bit_field_read_data %>,
+    o_sw_value        => <%= bit_field_value %>,
+    o_write_trigger   => <%= output_port(:write_trigger) %>,
+    o_read_trigger    => <%= output_port(:read_trigger) %>,
+    i_hw_write_enable => <%= input_port(:hw_write_enable, '"0"') %>,
+    i_hw_write_data   => <%= input_port(:hw_write_data) %>,
+    i_hw_set          => <%= input_port(:hw_set) %>,
+    i_hw_clear        => <%= input_port(:hw_clear) %>,
+    i_value           => <%= input_port(:value_in) %>,
+    i_mask            => (others => '1'),
+    o_value           => <%= output_port(:value_out) %>,
+    o_value_unmasked  => open
+  );

data/lib/rggen/vhdl/bit_field/type/custom.rb

@@ -0,0 +1,106 @@
+# frozen_string_literal: true
+
+RgGen.define_list_item_feature(:bit_field, :type, :custom) do
+  vhdl do
+    build do
+      if external_read_data?
+        input :value_in, {
+          name: "i_#{full_name}", width: width, array_size: array_size
+        }
+      else
+        output :value_out, {
+          name: "o_#{full_name}", width: width, array_size: array_size
+        }
+      end
+      if bit_field.hw_write?
+        input :hw_write_enable, {
+          name: "i_#{full_name}_hw_write_enable", width: 1, array_size: array_size
+        }
+        input :hw_write_data, {
+          name: "i_#{full_name}_hw_write_data", width: width, array_size: array_size
+        }
+      end
+      if bit_field.hw_set?
+        input :hw_set, {
+          name: "i_#{full_name}_hw_set", width: width, array_size: array_size
+        }
+      end
+      if bit_field.hw_clear?
+        input :hw_clear, {
+          name: "i_#{full_name}_hw_clear", width: width, array_size: array_size
+        }
+      end
+      if bit_field.write_trigger?
+        output :write_trigger, {
+          name: "o_#{full_name}_write_trigger", width: 1, array_size: array_size
+        }
+      end
+      if bit_field.read_trigger?
+        output :read_trigger, {
+          name: "o_#{full_name}_read_trigger", width: 1, array_size: array_size
+        }
+      end
+    end
+
+    main_code :bit_field, from_template: true
+
+    private
+
+    def external_read_data?
+      !bit_field.sw_update? && !bit_field.hw_update?
+    end
+
+    def initial_value
+      external_read_data? && default_initial_value || super
+    end
+
+    def default_initial_value
+      value = hex(0, width)
+      "slice(#{value}, #{width}, 0)"
+    end
+
+    def sw_read_action
+      {
+        none: 'RGGEN_READ_NONE',
+        default: 'RGGEN_READ_DEFAULT',
+        set: 'RGGEN_READ_SET',
+        clear: 'RGGEN_READ_CLEAR'
+      }[bit_field.sw_read]
+    end
+
+    def sw_write_action
+      {
+        none: 'RGGEN_WRITE_NONE',
+        default: 'RGGEN_WRITE_DEFAULT',
+        clear_0: 'RGGEN_WRITE_0_CLEAR',
+        clear_1: 'RGGEN_WRITE_1_CLEAR',
+        clear: 'RGGEN_WRITE_CLEAR',
+        set_0: 'RGGEN_WRITE_0_SET',
+        set_1: 'RGGEN_WRITE_1_SET',
+        set: 'RGGEN_WRITE_SET',
+        toggle_0: 'RGGEN_WRITE_0_TOGGLE',
+        toggle_1: 'RGGEN_WRITE_1_TOGGLE'
+      }[bit_field.sw_write]
+    end
+
+    def storage?
+      !external_read_data?
+    end
+
+    def trigger?
+      bit_field.write_trigger? || bit_field.read_trigger?
+    end
+
+    def input_port(name, default = nil)
+      find_port(name, default || '(others => \'0\')')
+    end
+
+    def output_port(name)
+      find_port(name, 'open')
+    end
+
+    def find_port(name, default_value)
+      respond_to?(name) && __send__(name)[loop_variables] || default_value
+    end
+  end
+end

data/lib/rggen/vhdl/bit_field/type/rol.erb

@@ -0,0 +1,27 @@
+u_bit_field: entity work.rggen_bit_field
+  generic map (
+    WIDTH           => <%= width %>,
+    INITIAL_VALUE   => <%= initial_value %>,
+    SW_WRITE_ACTION => RGGEN_WRITE_NONE
+  )
+  port map (
+    i_clk             => <%= clock %>,
+    i_rst_n           => <%= reset %>,
+    i_sw_valid        => <%= bit_field_valid %>,
+    i_sw_read_mask    => <%= bit_field_read_mask %>,
+    i_sw_write_enable => "1",
+    i_sw_write_mask   => <%= bit_field_write_mask %>,
+    i_sw_write_data   => <%= bit_field_write_data %>,
+    o_sw_read_data    => <%= bit_field_read_data %>,
+    o_sw_value        => <%= bit_field_value %>,
+    o_write_trigger   => open,
+    o_read_trigger    => open,
+    i_hw_write_enable => <%= latch_signal %>,
+    i_hw_write_data   => <%= value_in[loop_variables] %>,
+    i_hw_set          => (others => '0'),
+    i_hw_clear        => (others => '0'),
+    i_value           => (others => '0'),
+    i_mask            => (others => '1'),
+    o_value           => <%= value_out[loop_variables] %>,
+    o_value_unmasked  => open
+  );

data/lib/rggen/vhdl/bit_field/type/rol.rb

@@ -0,0 +1,27 @@
+# frozen_string_literal: true
+
+RgGen.define_list_item_feature(:bit_field, :type, :rol) do
+  vhdl do
+    build do
+      unless bit_field.reference?
+        input :latch, {
+          name: "i_#{full_name}_latch", width: 1, array_size: array_size
+        }
+      end
+      input :value_in, {
+        name: "i_#{full_name}", width: width, array_size: array_size
+      }
+      output :value_out, {
+        name: "o_#{full_name}", width: width, array_size: array_size
+      }
+    end
+
+    main_code :bit_field, from_template: true
+
+    private
+
+    def latch_signal
+      reference_bit_field || latch[loop_variables]
+    end
+  end
+end

data/lib/rggen/vhdl/bit_field/type/w0crs_w0src_w1crs_w1src_wcrs_wsrc.rb

@@ -19,7 +19,7 @@ RgGen.define_list_item_feature(
     end
 
     def read_set?
-      [:w0crs, :w1crs, :wcrs].include?(bit_field.type)
+      [:w0crs, :w1crs, :wcrs].any? { |type| bit_field.type == type }
     end
 
     def write_action

data/lib/rggen/vhdl/register_block/vhdl_top.rb

@@ -61,14 +61,14 @@ RgGen.define_simple_feature(:register_block, :vhdl_top) do
     def generic_declarations
       register_block
         .declarations[:generic]
-        .yield_self(&method(:add_terminator))
+        .then(&method(:add_terminator))
     end
 
     def port_declarations
       register_block
         .declarations[:port]
-        .yield_self(&method(:sort_port_declarations))
-        .yield_self(&method(:add_terminator))
+        .then(&method(:sort_port_declarations))
+        .then(&method(:add_terminator))
     end
 
     def signal_declarations

data/lib/rggen/vhdl/version.rb

@@ -2,6 +2,6 @@
 
 module RgGen
   module VHDL
-    VERSION = '0.3.0'
+    VERSION = '0.5.0'
   end
 end

data/lib/rggen/vhdl.rb

@@ -33,9 +33,11 @@ RgGen.setup_plugin :'rggen-vhdl' do |plugin|
     'vhdl/register/type/indirect',
     'vhdl/bit_field/vhdl_top',
     'vhdl/bit_field/type',
+    'vhdl/bit_field/type/custom',
     'vhdl/bit_field/type/rc_w0c_w1c_wc_woc',
     'vhdl/bit_field/type/ro_rotrg',
     'vhdl/bit_field/type/rof',
+    'vhdl/bit_field/type/rol',
     'vhdl/bit_field/type/row0trg_row1trg',
     'vhdl/bit_field/type/rowo_rowotrg',
     'vhdl/bit_field/type/rs_w0s_w1s_ws_wos',

metadata

@@ -1,14 +1,14 @@
 --- !ruby/object:Gem::Specification
 name: rggen-vhdl
 version: !ruby/object:Gem::Version
-  version: 0.3.0
+  version: 0.5.0
 platform: ruby
 authors:
 - Taichi Ishitani
 autorequire: 
 bindir: bin
 cert_chain: []
-date: 2022-07-05 00:00:00.000000000 Z
+date: 2023-01-02 00:00:00.000000000 Z
 dependencies:
 - !ruby/object:Gem::Dependency
   name: rggen-systemverilog
@@ -16,14 +16,14 @@ dependencies:
     requirements:
     - - ">="
       - !ruby/object:Gem::Version
-        version: 0.27.0
+        version: 0.29.0
   type: :runtime
   prerelease: false
   version_requirements: !ruby/object:Gem::Requirement
     requirements:
     - - ">="
       - !ruby/object:Gem::Version
-        version: 0.27.0
+        version: 0.29.0
 - !ruby/object:Gem::Dependency
   name: bundler
   requirement: !ruby/object:Gem::Requirement
@@ -50,12 +50,16 @@ files:
 - README.md
 - lib/rggen/vhdl.rb
 - lib/rggen/vhdl/bit_field/type.rb
+- lib/rggen/vhdl/bit_field/type/custom.erb
+- lib/rggen/vhdl/bit_field/type/custom.rb
 - lib/rggen/vhdl/bit_field/type/rc_w0c_w1c_wc_woc.erb
 - lib/rggen/vhdl/bit_field/type/rc_w0c_w1c_wc_woc.rb
 - lib/rggen/vhdl/bit_field/type/ro_rotrg.erb
 - lib/rggen/vhdl/bit_field/type/ro_rotrg.rb
 - lib/rggen/vhdl/bit_field/type/rof.erb
 - lib/rggen/vhdl/bit_field/type/rof.rb
+- lib/rggen/vhdl/bit_field/type/rol.erb
+- lib/rggen/vhdl/bit_field/type/rol.rb
 - lib/rggen/vhdl/bit_field/type/row0trg_row1trg.erb
 - lib/rggen/vhdl/bit_field/type/row0trg_row1trg.rb
 - lib/rggen/vhdl/bit_field/type/rowo_rowotrg.erb
@@ -124,15 +128,15 @@ required_ruby_version: !ruby/object:Gem::Requirement
   requirements:
   - - ">="
     - !ruby/object:Gem::Version
-      version: 2.6.0
+      version: 2.7.0
 required_rubygems_version: !ruby/object:Gem::Requirement
   requirements:
   - - ">="
     - !ruby/object:Gem::Version
       version: '0'
 requirements: []
-rubygems_version: 3.3.3
+rubygems_version: 3.4.1
 signing_key: 
 specification_version: 4
-summary: rggen-vhdl-0.3.0
+summary: rggen-vhdl-0.5.0
 test_files: []