rggen-vhdl 0.3.0 → 0.4.0

This diff represents the content of publicly available package versions that have been released to one of the supported registries. The information contained in this diff is provided for informational purposes only and reflects changes between package versions as they appear in their respective public registries.
checksums.yaml CHANGED
@@ -1,7 +1,7 @@
1
1
  ---
2
2
  SHA256:
3
- metadata.gz: a3fe2a4f117ebddd32c38f4e65d042c845f81e85f6130d7f85ebf94f7b12868f
4
- data.tar.gz: 55c35ac2e82232c2fba80da4ec23ad0bb417cb35c228b3e94a76ee134f747f54
3
+ metadata.gz: aa8c8c46d699ebd0a2fb1e9f6e2b3ef54f4ad73102fce9a5e354de923d7b7d1e
4
+ data.tar.gz: ac14f9c1a8c9889a7b242e4d13d074f543d297241475198293ce36271f92e2e9
5
5
  SHA512:
6
- metadata.gz: 1e1d50c4f6eea7cfd80de27beac4e2f451d8913d13b77976776e0c021252dc53da2aa1227ed5b587f905d30aa54d66437e4af795bc15cea9626f8a7076bc521f
7
- data.tar.gz: 0fa49c35d10ddfe2c4d680780dd3f40ef0a8dc64aa4808cc352c55261ccf9d8d754aa450643bdacf1072b86f88ce880050851afcf09001a091ea25f0439353e3
6
+ metadata.gz: bd6cc0cf02deba72a1cfbe5a8bb9d095c6c2b1e8020c4add4f3c7ecd30a959f0a4c90422381fa36d10cdd0438fa70a74f8b79b5a128356dfadcec95035c0e0bf
7
+ data.tar.gz: b90261ea9057b8dfef7d73f774a54d7a409ac7ab6741a04e646d60195fe1d9cef2342c4feef9c89524ad690328bcb6c43280feaaf1c8c8b7087ea0be800c2564
@@ -0,0 +1,34 @@
1
+ u_bit_field: entity work.rggen_bit_field
2
+ generic map (
3
+ WIDTH => <%= width %>,
4
+ INITIAL_VALUE => <%= initial_value %>,
5
+ SW_READ_ACTION => <%= sw_read_action %>,
6
+ SW_WRITE_ACTION => <%= sw_write_action %>,
7
+ SW_WRITE_ONCE => <%= bit_field.sw_write_once? %>,
8
+ HW_SET_WIDTH => <%= width %>,
9
+ HW_CLEAR_WIDTH => <%= width %>,
10
+ STORAGE => <%= storage? %>,
11
+ EXTERNAL_READ_DATA => <%= external_read_data? %>,
12
+ TRIGGER => <%= trigger? %>
13
+ )
14
+ port map (
15
+ i_clk => <%= clock %>,
16
+ i_rst_n => <%= reset %>,
17
+ i_sw_valid => <%= bit_field_valid %>,
18
+ i_sw_read_mask => <%= bit_field_read_mask %>,
19
+ i_sw_write_enable => "1",
20
+ i_sw_write_mask => <%= bit_field_write_mask %>,
21
+ i_sw_write_data => <%= bit_field_write_data %>,
22
+ o_sw_read_data => <%= bit_field_read_data %>,
23
+ o_sw_value => <%= bit_field_value %>,
24
+ o_write_trigger => <%= output_port(:write_trigger) %>,
25
+ o_read_trigger => <%= output_port(:read_trigger) %>,
26
+ i_hw_write_enable => <%= input_port(:hw_write_enable, '"0"') %>,
27
+ i_hw_write_data => <%= input_port(:hw_write_data) %>,
28
+ i_hw_set => <%= input_port(:hw_set) %>,
29
+ i_hw_clear => <%= input_port(:hw_clear) %>,
30
+ i_value => <%= input_port(:value_in) %>,
31
+ i_mask => (others => '1'),
32
+ o_value => <%= output_port(:value_out) %>,
33
+ o_value_unmasked => open
34
+ );
@@ -0,0 +1,106 @@
1
+ # frozen_string_literal: true
2
+
3
+ RgGen.define_list_item_feature(:bit_field, :type, :custom) do
4
+ vhdl do
5
+ build do
6
+ if external_read_data?
7
+ input :value_in, {
8
+ name: "i_#{full_name}", width: width, array_size: array_size
9
+ }
10
+ else
11
+ output :value_out, {
12
+ name: "o_#{full_name}", width: width, array_size: array_size
13
+ }
14
+ end
15
+ if bit_field.hw_write?
16
+ input :hw_write_enable, {
17
+ name: "i_#{full_name}_hw_write_enable", width: 1, array_size: array_size
18
+ }
19
+ input :hw_write_data, {
20
+ name: "i_#{full_name}_hw_write_data", width: width, array_size: array_size
21
+ }
22
+ end
23
+ if bit_field.hw_set?
24
+ input :hw_set, {
25
+ name: "i_#{full_name}_hw_set", width: width, array_size: array_size
26
+ }
27
+ end
28
+ if bit_field.hw_clear?
29
+ input :hw_clear, {
30
+ name: "i_#{full_name}_hw_clear", width: width, array_size: array_size
31
+ }
32
+ end
33
+ if bit_field.write_trigger?
34
+ output :write_trigger, {
35
+ name: "o_#{full_name}_write_trigger", width: 1, array_size: array_size
36
+ }
37
+ end
38
+ if bit_field.read_trigger?
39
+ output :read_trigger, {
40
+ name: "o_#{full_name}_read_trigger", width: 1, array_size: array_size
41
+ }
42
+ end
43
+ end
44
+
45
+ main_code :bit_field, from_template: true
46
+
47
+ private
48
+
49
+ def external_read_data?
50
+ !bit_field.sw_update? && !bit_field.hw_update?
51
+ end
52
+
53
+ def initial_value
54
+ external_read_data? && default_initial_value || super
55
+ end
56
+
57
+ def default_initial_value
58
+ value = hex(0, width)
59
+ "slice(#{value}, #{width}, 0)"
60
+ end
61
+
62
+ def sw_read_action
63
+ {
64
+ none: 'RGGEN_READ_NONE',
65
+ default: 'RGGEN_READ_DEFAULT',
66
+ set: 'RGGEN_READ_SET',
67
+ clear: 'RGGEN_READ_CLEAR'
68
+ }[bit_field.sw_read]
69
+ end
70
+
71
+ def sw_write_action
72
+ {
73
+ none: 'RGGEN_WRITE_NONE',
74
+ default: 'RGGEN_WRITE_DEFAULT',
75
+ clear_0: 'RGGEN_WRITE_0_CLEAR',
76
+ clear_1: 'RGGEN_WRITE_1_CLEAR',
77
+ clear: 'RGGEN_WRITE_CLEAR',
78
+ set_0: 'RGGEN_WRITE_0_SET',
79
+ set_1: 'RGGEN_WRITE_1_SET',
80
+ set: 'RGGEN_WRITE_SET',
81
+ toggle_0: 'RGGEN_WRITE_0_TOGGLE',
82
+ toggle_1: 'RGGEN_WRITE_1_TOGGLE'
83
+ }[bit_field.sw_write]
84
+ end
85
+
86
+ def storage?
87
+ !external_read_data?
88
+ end
89
+
90
+ def trigger?
91
+ bit_field.write_trigger? || bit_field.read_trigger?
92
+ end
93
+
94
+ def input_port(name, default = nil)
95
+ find_port(name, default || '(others => \'0\')')
96
+ end
97
+
98
+ def output_port(name)
99
+ find_port(name, 'open')
100
+ end
101
+
102
+ def find_port(name, default_value)
103
+ respond_to?(name) && __send__(name)[loop_variables] || default_value
104
+ end
105
+ end
106
+ end
@@ -0,0 +1,27 @@
1
+ u_bit_field: entity work.rggen_bit_field
2
+ generic map (
3
+ WIDTH => <%= width %>,
4
+ INITIAL_VALUE => <%= initial_value %>,
5
+ SW_WRITE_ACTION => RGGEN_WRITE_NONE
6
+ )
7
+ port map (
8
+ i_clk => <%= clock %>,
9
+ i_rst_n => <%= reset %>,
10
+ i_sw_valid => <%= bit_field_valid %>,
11
+ i_sw_read_mask => <%= bit_field_read_mask %>,
12
+ i_sw_write_enable => "1",
13
+ i_sw_write_mask => <%= bit_field_write_mask %>,
14
+ i_sw_write_data => <%= bit_field_write_data %>,
15
+ o_sw_read_data => <%= bit_field_read_data %>,
16
+ o_sw_value => <%= bit_field_value %>,
17
+ o_write_trigger => open,
18
+ o_read_trigger => open,
19
+ i_hw_write_enable => <%= latch_signal %>,
20
+ i_hw_write_data => <%= value_in[loop_variables] %>,
21
+ i_hw_set => (others => '0'),
22
+ i_hw_clear => (others => '0'),
23
+ i_value => (others => '0'),
24
+ i_mask => (others => '1'),
25
+ o_value => <%= value_out[loop_variables] %>,
26
+ o_value_unmasked => open
27
+ );
@@ -0,0 +1,27 @@
1
+ # frozen_string_literal: true
2
+
3
+ RgGen.define_list_item_feature(:bit_field, :type, :rol) do
4
+ vhdl do
5
+ build do
6
+ unless bit_field.reference?
7
+ input :latch, {
8
+ name: "i_#{full_name}_latch", width: 1, array_size: array_size
9
+ }
10
+ end
11
+ input :value_in, {
12
+ name: "i_#{full_name}", width: width, array_size: array_size
13
+ }
14
+ output :value_out, {
15
+ name: "o_#{full_name}", width: width, array_size: array_size
16
+ }
17
+ end
18
+
19
+ main_code :bit_field, from_template: true
20
+
21
+ private
22
+
23
+ def latch_signal
24
+ reference_bit_field || latch[loop_variables]
25
+ end
26
+ end
27
+ end
@@ -19,7 +19,7 @@ RgGen.define_list_item_feature(
19
19
  end
20
20
 
21
21
  def read_set?
22
- [:w0crs, :w1crs, :wcrs].include?(bit_field.type)
22
+ [:w0crs, :w1crs, :wcrs].any? { |type| bit_field.type == type }
23
23
  end
24
24
 
25
25
  def write_action
@@ -61,14 +61,14 @@ RgGen.define_simple_feature(:register_block, :vhdl_top) do
61
61
  def generic_declarations
62
62
  register_block
63
63
  .declarations[:generic]
64
- .yield_self(&method(:add_terminator))
64
+ .then(&method(:add_terminator))
65
65
  end
66
66
 
67
67
  def port_declarations
68
68
  register_block
69
69
  .declarations[:port]
70
- .yield_self(&method(:sort_port_declarations))
71
- .yield_self(&method(:add_terminator))
70
+ .then(&method(:sort_port_declarations))
71
+ .then(&method(:add_terminator))
72
72
  end
73
73
 
74
74
  def signal_declarations
@@ -2,6 +2,6 @@
2
2
 
3
3
  module RgGen
4
4
  module VHDL
5
- VERSION = '0.3.0'
5
+ VERSION = '0.4.0'
6
6
  end
7
7
  end
data/lib/rggen/vhdl.rb CHANGED
@@ -33,9 +33,11 @@ RgGen.setup_plugin :'rggen-vhdl' do |plugin|
33
33
  'vhdl/register/type/indirect',
34
34
  'vhdl/bit_field/vhdl_top',
35
35
  'vhdl/bit_field/type',
36
+ 'vhdl/bit_field/type/custom',
36
37
  'vhdl/bit_field/type/rc_w0c_w1c_wc_woc',
37
38
  'vhdl/bit_field/type/ro_rotrg',
38
39
  'vhdl/bit_field/type/rof',
40
+ 'vhdl/bit_field/type/rol',
39
41
  'vhdl/bit_field/type/row0trg_row1trg',
40
42
  'vhdl/bit_field/type/rowo_rowotrg',
41
43
  'vhdl/bit_field/type/rs_w0s_w1s_ws_wos',
metadata CHANGED
@@ -1,14 +1,14 @@
1
1
  --- !ruby/object:Gem::Specification
2
2
  name: rggen-vhdl
3
3
  version: !ruby/object:Gem::Version
4
- version: 0.3.0
4
+ version: 0.4.0
5
5
  platform: ruby
6
6
  authors:
7
7
  - Taichi Ishitani
8
8
  autorequire:
9
9
  bindir: bin
10
10
  cert_chain: []
11
- date: 2022-07-05 00:00:00.000000000 Z
11
+ date: 2022-10-10 00:00:00.000000000 Z
12
12
  dependencies:
13
13
  - !ruby/object:Gem::Dependency
14
14
  name: rggen-systemverilog
@@ -16,14 +16,14 @@ dependencies:
16
16
  requirements:
17
17
  - - ">="
18
18
  - !ruby/object:Gem::Version
19
- version: 0.27.0
19
+ version: 0.28.0
20
20
  type: :runtime
21
21
  prerelease: false
22
22
  version_requirements: !ruby/object:Gem::Requirement
23
23
  requirements:
24
24
  - - ">="
25
25
  - !ruby/object:Gem::Version
26
- version: 0.27.0
26
+ version: 0.28.0
27
27
  - !ruby/object:Gem::Dependency
28
28
  name: bundler
29
29
  requirement: !ruby/object:Gem::Requirement
@@ -50,12 +50,16 @@ files:
50
50
  - README.md
51
51
  - lib/rggen/vhdl.rb
52
52
  - lib/rggen/vhdl/bit_field/type.rb
53
+ - lib/rggen/vhdl/bit_field/type/custom.erb
54
+ - lib/rggen/vhdl/bit_field/type/custom.rb
53
55
  - lib/rggen/vhdl/bit_field/type/rc_w0c_w1c_wc_woc.erb
54
56
  - lib/rggen/vhdl/bit_field/type/rc_w0c_w1c_wc_woc.rb
55
57
  - lib/rggen/vhdl/bit_field/type/ro_rotrg.erb
56
58
  - lib/rggen/vhdl/bit_field/type/ro_rotrg.rb
57
59
  - lib/rggen/vhdl/bit_field/type/rof.erb
58
60
  - lib/rggen/vhdl/bit_field/type/rof.rb
61
+ - lib/rggen/vhdl/bit_field/type/rol.erb
62
+ - lib/rggen/vhdl/bit_field/type/rol.rb
59
63
  - lib/rggen/vhdl/bit_field/type/row0trg_row1trg.erb
60
64
  - lib/rggen/vhdl/bit_field/type/row0trg_row1trg.rb
61
65
  - lib/rggen/vhdl/bit_field/type/rowo_rowotrg.erb
@@ -131,8 +135,8 @@ required_rubygems_version: !ruby/object:Gem::Requirement
131
135
  - !ruby/object:Gem::Version
132
136
  version: '0'
133
137
  requirements: []
134
- rubygems_version: 3.3.3
138
+ rubygems_version: 3.3.7
135
139
  signing_key:
136
140
  specification_version: 4
137
- summary: rggen-vhdl-0.3.0
141
+ summary: rggen-vhdl-0.4.0
138
142
  test_files: []