rggen-vhdl 0.2.0 → 0.2.1

checksums.yaml

@@ -1,7 +1,7 @@
 ---
 SHA256:
-  metadata.gz: e152dbacccc9958c0062f2c904e83f467d5d5c1e424954b14074d1bce04d20d7
-  data.tar.gz: fac552a7d2706f89903fdcd8e7c16c9a50927ad9925b5c1a024d38f18383ec47
+  metadata.gz: c74cc68ef729bcf49af9fbfb49184006e2f145408fa67d77adf96cd85ab07510
+  data.tar.gz: e113dc0c84be1b6646ae0d876e4f0cb920680c0bba12d71d434fbd6d168e6f42
 SHA512:
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-  data.tar.gz: b1df3e81e394b417505150dc6757be37b643dba6e42406245983d08819abcaf7202f94f09bc596aa14cd86b4b356c291a59670e306bde791d8573dfe0df94e2d
+  metadata.gz: fc44aaaafada6892281fc6f608af510e051bfb46aa00331dd4f1ac727c551d49d27dff01fd5f775cf5dc998c552553b1d30c682764e730696306c4ccf6ee2901
+  data.tar.gz: d378636891636a4609d1a40a4878ffd4a2edde73c5c30335d9e2a45265203de768db5f34d42a2dbbc8cea9b46e6b2f82416d9f43d2d185dc5d7c9d9204f7513b

data/lib/rggen/vhdl/register/tie_off_unused_signals.erb

@@ -0,0 +1,6 @@
+\g_tie_off\: for \__i\ in 0 to <%= width - 1 %> generate
+  g: if (bit_slice(<%= valid_bits %>, \__i\) = '0') generate
+    <%= bit_field_read_data %>(\__i\) <= '0';
+    <%= bit_field_value %>(\__i\) <= '0';
+  end generate;
+end generate;

data/lib/rggen/vhdl/register/type/default.erb

@@ -6,7 +6,6 @@ u_register: entity work.rggen_default_register
     OFFSET_ADDRESS  => <%= offset_address %>,
     BUS_WIDTH       => <%= bus_width %>,
     DATA_WIDTH      => <%= width %>,
-    VALID_BITS      => <%= valid_bits %>,
     REGISTER_INDEX  => <%= register_index %>
   )
   port map (

data/lib/rggen/vhdl/register/type/indirect.erb

@@ -9,7 +9,6 @@ u_register: entity work.rggen_indirect_register
     OFFSET_ADDRESS        => <%= offset_address %>,
     BUS_WIDTH             => <%= bus_width %>,
     DATA_WIDTH            => <%= width %>,
-    VALID_BITS            => <%= valid_bits %>,
     INDIRECT_MATCH_WIDTH  => <%= match_width %>
   )
   port map (

data/lib/rggen/vhdl/register/type.rb

@@ -5,6 +5,11 @@ RgGen.define_list_feature(:register, :type) do
     base_feature do
       include RgGen::SystemVerilog::RTL::RegisterType
 
+      pre_code :register do |code|
+        register.bit_fields.empty? ||
+          (code << process_template(File.join(__dir__, 'tie_off_unused_signals.erb')))
+      end
+
       private
 
       def readable?

data/lib/rggen/vhdl/version.rb

@@ -2,6 +2,6 @@
 
 module RgGen
   module VHDL
-    VERSION = '0.2.0'
+    VERSION = '0.2.1'
   end
 end

metadata

@@ -1,14 +1,14 @@
 --- !ruby/object:Gem::Specification
 name: rggen-vhdl
 version: !ruby/object:Gem::Version
-  version: 0.2.0
+  version: 0.2.1
 platform: ruby
 authors:
 - Taichi Ishitani
 autorequire: 
 bindir: bin
 cert_chain: []
-date: 2022-03-25 00:00:00.000000000 Z
+date: 2022-06-07 00:00:00.000000000 Z
 dependencies:
 - !ruby/object:Gem::Dependency
   name: rggen-systemverilog
@@ -82,7 +82,7 @@ files:
 - lib/rggen/vhdl/component.rb
 - lib/rggen/vhdl/factories.rb
 - lib/rggen/vhdl/feature.rb
-- lib/rggen/vhdl/register/default.erb
+- lib/rggen/vhdl/register/tie_off_unused_signals.erb
 - lib/rggen/vhdl/register/type.rb
 - lib/rggen/vhdl/register/type/default.erb
 - lib/rggen/vhdl/register/type/external.erb
@@ -133,5 +133,5 @@ requirements: []
 rubygems_version: 3.3.3
 signing_key: 
 specification_version: 4
-summary: rggen-vhdl-0.2.0
+summary: rggen-vhdl-0.2.1
 test_files: []

data/lib/rggen/vhdl/register/default.erb

@@ -1,29 +0,0 @@
-rggen_default_register #(
-  .READABLE       (<%= readable %>),
-  .WRITABLE       (<%= writable %>),
-  .ADDRESS_WIDTH  (<%= address_width %>),
-  .OFFSET_ADDRESS (<%= offset_address %>),
-  .BUS_WIDTH      (<%= bus_width %>),
-  .DATA_WIDTH     (<%= width %>),
-  .VALID_BITS     (<%= valid_bits %>),
-  .REGISTER_INDEX (<%= register_index %>)
-) u_register (
-  .i_clk                  (<%= clock %>),
-  .i_rst_n                (<%= reset %>),
-  .i_register_valid       (<%= register_valid %>),
-  .i_register_access      (<%= register_access %>),
-  .i_register_address     (<%= register_address %>),
-  .i_register_write_data  (<%= register_write_data %>),
-  .i_register_strobe      (<%= register_strobe %>),
-  .o_register_active      (<%= register_active %>),
-  .o_register_ready       (<%= register_ready %>),
-  .o_register_status      (<%= register_status %>),
-  .o_register_read_data   (<%= register_read_data %>),
-  .o_register_value       (<%= register_value %>),
-  .o_bit_field_valid      (<%= bit_field_valid %>),
-  .o_bit_field_read_mask  (<%= bit_field_read_mask %>),
-  .o_bit_field_write_mask (<%= bit_field_write_mask %>),
-  .o_bit_field_write_data (<%= bit_field_write_data %>),
-  .i_bit_field_read_data  (<%= bit_field_read_data %>),
-  .i_bit_field_value      (<%= bit_field_value %>)
-);