rggen-vhdl 0.11.0 → 0.12.0

checksums.yaml

@@ -1,7 +1,7 @@
 ---
 SHA256:
-  metadata.gz: abc5a2ebbca59bbc2bb69a1419edfebf28f65c8649bf51a855fc1131cb211aaf
-  data.tar.gz: '07536832610babc6a8e5dabb3112d452fa9f3e55195e13a618b2ba34cda8880e'
+  metadata.gz: edbd44db38f168ab2cd534bc30faa2293d6bb8dbcd7a7487dc6ce3cbecd2c7b0
+  data.tar.gz: 25e25403b17fc5e0b6e5e496d2b0f8ddd2f98bac26a309b9c1e92b5c13a3e24c
 SHA512:
-  metadata.gz: 72d0c5ce29e1b5b3f0e4ca26dd6ed6b0b3d5eabab011c2b9cf5e4fb56b96def26383f079a187a4a5c3035c2f12d3d717396a9790b7539ec20ccbb757231550b5
-  data.tar.gz: f572366eca82a4b4ed2390cf3253bb037f752e90294ffbda4098dcd06c2334611ce23c51e7e91958b0ccff0e1efad78dfb44c625bbf1e348c3941d2a4603a3c2
+  metadata.gz: 7c5f7516558ff09c5f6bd0420a1c6f2cc0403020a50546c57a40714266d287949b0ce00f4c41ef4dc1963c5e40916dd2f00b3a79792f5d7d99b8aceaf4b1f97e
+  data.tar.gz: 60a4f71b679d097e29458435c5ebeedd45938a89bb8cdbf67d80937324f63aad3d0470800352af9eb9659e35be20ad0b72d2ffdec7a67f39ab35b56efcaad78c

data/README.md

@@ -1,6 +1,6 @@
 [![Gem Version](https://badge.fury.io/rb/rggen-vhdl.svg)](https://badge.fury.io/rb/rggen-vhdl)
 [![CI](https://github.com/rggen/rggen-vhdl/actions/workflows/ci.yml/badge.svg)](https://github.com/rggen/rggen-vhdl/actions/workflows/ci.yml)
-[![Maintainability](https://api.codeclimate.com/v1/badges/d30b2c06ae3d7c0f254a/maintainability)](https://codeclimate.com/github/rggen/rggen-vhdl/maintainability)
+[![Maintainability](https://qlty.sh/badges/d3e167e0-16f0-4170-ae4a-10ccc3dcdcb5/maintainability.svg)](https://qlty.sh/gh/rggen/projects/rggen-vhdl)
 [![codecov](https://codecov.io/gh/rggen/rggen-vhdl/branch/master/graph/badge.svg?token=cyo9R4xCje)](https://codecov.io/gh/rggen/rggen-vhdl)
 [![Gitter](https://badges.gitter.im/rggen/rggen.svg)](https://gitter.im/rggen/rggen?utm_source=badge&utm_medium=badge&utm_campaign=pr-badge)
 

data/lib/rggen/vhdl/bit_field/type.rb

@@ -26,7 +26,7 @@ RgGen.define_list_feature(:bit_field, :type) do
       end
 
       def initial_value
-        index = bit_field.initial_value_array? && bit_field.local_index || 0
+        index = bit_field.initial_value_array? && bit_field.flat_loop_index || 0
         "slice(#{bit_field.initial_value}, #{width}, #{index})"
       end
 
@@ -70,7 +70,7 @@ RgGen.define_list_feature(:bit_field, :type) do
         bit_field.reference? &&
           bit_field
             .find_reference(register_block.bit_fields)
-            .value(bit_field.local_indices, bit_field.reference_width)
+            .value(bit_field.local_indexes, bit_field.reference_width)
       end
 
       def loop_variables

data/lib/rggen/vhdl/bit_field/vhdl_top.rb

@@ -43,15 +43,17 @@ RgGen.define_simple_feature(:bit_field, :vhdl_top) do
 
     def initial_value_width
       width = bit_field.width
-      repeat_size = bit_field.sequence_size || 1
-      width * repeat_size
+      width * initial_value_repeat_size
     end
 
     def default_initial_value
       width = bit_field.width
-      repeat_size = bit_field.sequence_size || 1
       value = initial_value_rhs_default
-      "repeat(#{value}, #{width}, #{repeat_size})"
+      "repeat(#{value}, #{width}, #{initial_value_repeat_size})"
+    end
+
+    def initial_value_repeat_size
+      array_size&.inject(:*) || 1
     end
 
     def define_accessor_for_initial_value
@@ -70,14 +72,15 @@ RgGen.define_simple_feature(:bit_field, :vhdl_top) do
 
     def array_initial_value_rhs
       value =
-        bit_field.initial_values
+        bit_field
+          .initial_values(flatten: true)
           .map.with_index { |v, i| v << bit_field.width * i }
           .inject(:|)
-      hex(value, bit_field.sequence_size * bit_field.width)
+      hex(value, initial_value_width)
     end
 
     def register_value(offsets, lsb, width)
-      index = register.index(offsets || register.local_indices)
+      index = register.index(offsets || register.local_indexes)
       register_block.register_value[[index], lsb, width]
     end
 

data/lib/rggen/vhdl/register_block/protocol/avalon.erb

@@ -0,0 +1,33 @@
+u_adapter: entity <%= library_name %>.rggen_avalon_adapter
+  generic map (
+    ADDRESS_WIDTH       => <%= address_width %>,
+    LOCAL_ADDRESS_WIDTH => <%= local_address_width %>,
+    BUS_WIDTH           => <%= bus_width %>,
+    REGISTERS           => <%= total_registers %>,
+    PRE_DECODE          => <%= pre_decode %>,
+    BASE_ADDRESS        => <%= base_address %>,
+    BYTE_SIZE           => <%= byte_size %>,
+    ERROR_STATUS        => <%= error_status %>,
+    INSERT_SLICER       => <%= insert_slicer %>
+  )
+  port map (
+    i_clk                 => <%= register_block.clock %>,
+    i_rst_n               => <%= register_block.reset %>,
+    i_read                => <%= read %>,
+    i_write               => <%= write %>,
+    i_address             => <%= address %>,
+    i_byteenable          => <%= byteenable %>,
+    i_writedata           => <%= writedata %>,
+    o_waitrequest         => <%= waitrequest %>,
+    o_response            => <%= response %>,
+    o_readdata            => <%= readdata %>,
+    o_register_valid      => <%= register_block.register_valid %>,
+    o_register_access     => <%= register_block.register_access %>,
+    o_register_address    => <%= register_block.register_address %>,
+    o_register_write_data => <%= register_block.register_write_data %>,
+    o_register_strobe     => <%= register_block.register_strobe %>,
+    i_register_active     => <%= register_block.register_active %>,
+    i_register_ready      => <%= register_block.register_ready %>,
+    i_register_status     => <%= register_block.register_status %>,
+    i_register_read_data  => <%= register_block.register_read_data %>
+  );

data/lib/rggen/vhdl/register_block/protocol/avalon.rb

@@ -0,0 +1,34 @@
+# frozen_string_literal: true
+
+RgGen.define_list_item_feature(:register_block, :protocol, :avalon) do
+  vhdl do
+    build do
+      input :read, {
+        name: 'i_read'
+      }
+      input :write, {
+        name: 'i_write'
+      }
+      input :address, {
+        name: 'i_address', width: address_width
+      }
+      input :byteenable, {
+        name: 'i_byteenable', width: bus_width / 8
+      }
+      input :writedata, {
+        name: 'i_writedata', width: bus_width
+      }
+      output :waitrequest, {
+        name: 'o_waitrequest'
+      }
+      output :response, {
+        name: 'o_response', width: 2
+      }
+      output :readdata, {
+        name: 'o_readdata', width: bus_width
+      }
+    end
+
+    main_code :register_block, from_template: true
+  end
+end

data/lib/rggen/vhdl/register_block/protocol/native.erb

@@ -8,6 +8,7 @@ u_adapter: entity <%= library_name %>.rggen_native_adapter
     PRE_DECODE          => <%= pre_decode %>,
     BASE_ADDRESS        => <%= base_address %>,
     BYTE_SIZE           => <%= byte_size %>,
+    USE_READ_STROBE     => <%= use_read_strobe %>,
     ERROR_STATUS        => <%= error_status %>,
     INSERT_SLICER       => <%= insert_slicer %>
   )

data/lib/rggen/vhdl/register_block/protocol/native.rb

@@ -6,6 +6,9 @@ RgGen.define_list_item_feature(:register_block, :protocol, :native) do
       generic :strobe_width, {
         name: 'STROBE_WIDTH', type: :positive, default: bus_width / 8
       }
+      generic :use_read_strobe, {
+        name: 'USE_READ_STROBE', type: :boolean, default: false
+      }
 
       input :valid, { name: 'i_csrbus_valid' }
       input :access, { name: 'i_csrbus_access', width: 2 }

data/lib/rggen/vhdl/version.rb

@@ -2,6 +2,6 @@
 
 module RgGen
   module VHDL
-    VERSION = '0.11.0'
+    VERSION = '0.12.0'
   end
 end

data/lib/rggen/vhdl.rb

@@ -27,6 +27,7 @@ RgGen.setup_plugin :'rggen-vhdl' do |plugin|
     'vhdl/register_block/protocol',
     'vhdl/register_block/protocol/apb',
     'vhdl/register_block/protocol/axi4lite',
+    'vhdl/register_block/protocol/avalon',
     'vhdl/register_block/protocol/wishbone',
     'vhdl/register_block/protocol/native',
     'vhdl/register_file/vhdl_top',

metadata

@@ -1,13 +1,13 @@
 --- !ruby/object:Gem::Specification
 name: rggen-vhdl
 version: !ruby/object:Gem::Version
-  version: 0.11.0
+  version: 0.12.0
 platform: ruby
 authors:
 - Taichi Ishitani
 bindir: bin
 cert_chain: []
-date: 2025-01-23 00:00:00.000000000 Z
+date: 2025-02-19 00:00:00.000000000 Z
 dependencies:
 - !ruby/object:Gem::Dependency
   name: rggen-systemverilog
@@ -15,14 +15,14 @@ dependencies:
     requirements:
     - - ">="
       - !ruby/object:Gem::Version
-        version: 0.34.0
+        version: 0.35.0
   type: :runtime
   prerelease: false
   version_requirements: !ruby/object:Gem::Requirement
     requirements:
     - - ">="
       - !ruby/object:Gem::Version
-        version: 0.34.0
+        version: 0.35.0
 description: VHDL writer plugin for RgGen
 email:
 - rggen@googlegroups.com
@@ -89,6 +89,8 @@ files:
 - lib/rggen/vhdl/register_block/protocol.rb
 - lib/rggen/vhdl/register_block/protocol/apb.erb
 - lib/rggen/vhdl/register_block/protocol/apb.rb
+- lib/rggen/vhdl/register_block/protocol/avalon.erb
+- lib/rggen/vhdl/register_block/protocol/avalon.rb
 - lib/rggen/vhdl/register_block/protocol/axi4lite.erb
 - lib/rggen/vhdl/register_block/protocol/axi4lite.rb
 - lib/rggen/vhdl/register_block/protocol/native.erb
@@ -130,5 +132,5 @@ required_rubygems_version: !ruby/object:Gem::Requirement
 requirements: []
 rubygems_version: 3.6.2
 specification_version: 4
-summary: rggen-vhdl-0.11.0
+summary: rggen-vhdl-0.12.0
 test_files: []