rggen-vhdl 0.10.1 → 0.12.0

checksums.yaml

@@ -1,7 +1,7 @@
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data/LICENSE

@@ -1,6 +1,6 @@
 The MIT License (MIT)
 
-Copyright (c) 2021-2024 Taichi Ishitani
+Copyright (c) 2021-2025 Taichi Ishitani
 
 Permission is hereby granted, free of charge, to any person obtaining a copy
 of this software and associated documentation files (the "Software"), to deal

data/README.md

@@ -1,6 +1,6 @@
 [![Gem Version](https://badge.fury.io/rb/rggen-vhdl.svg)](https://badge.fury.io/rb/rggen-vhdl)
 [![CI](https://github.com/rggen/rggen-vhdl/actions/workflows/ci.yml/badge.svg)](https://github.com/rggen/rggen-vhdl/actions/workflows/ci.yml)
-[![Maintainability](https://api.codeclimate.com/v1/badges/d30b2c06ae3d7c0f254a/maintainability)](https://codeclimate.com/github/rggen/rggen-vhdl/maintainability)
+[![Maintainability](https://qlty.sh/badges/d3e167e0-16f0-4170-ae4a-10ccc3dcdcb5/maintainability.svg)](https://qlty.sh/gh/rggen/projects/rggen-vhdl)
 [![codecov](https://codecov.io/gh/rggen/rggen-vhdl/branch/master/graph/badge.svg?token=cyo9R4xCje)](https://codecov.io/gh/rggen/rggen-vhdl)
 [![Gitter](https://badges.gitter.im/rggen/rggen.svg)](https://gitter.im/rggen/rggen?utm_source=badge&utm_medium=badge&utm_campaign=pr-badge)
 
@@ -68,7 +68,7 @@ Feedbacks, bus reports, questions and etc. are welcome! You can post them bu usi
 
 ## Copyright & License
 
-Copyright © 2021-2024 Taichi Ishitani. RgGen::VHDL is licensed under the [MIT License](https://opensource.org/licenses/MIT), see [LICENSE](LICENSE) for futher details.
+Copyright © 2021-2025 Taichi Ishitani. RgGen::VHDL is licensed under the [MIT License](https://opensource.org/licenses/MIT), see [LICENSE](LICENSE) for futher details.
 
 ## Code of Conduct
 

data/lib/rggen/vhdl/bit_field/type/custom.rb

@@ -5,39 +5,39 @@ RgGen.define_list_item_feature(:bit_field, :type, :custom) do
     build do
       if external_read_data?
         input :value_in, {
-          name: "i_#{full_name}", width: width, array_size: array_size
+          name: "i_#{full_name}", width:, array_size:
         }
       else
         output :value_out, {
-          name: "o_#{full_name}", width: width, array_size: array_size
+          name: "o_#{full_name}", width:, array_size:
         }
       end
       if bit_field.hw_write?
         input :hw_write_enable, {
-          name: "i_#{full_name}_hw_write_enable", width: 1, array_size: array_size
+          name: "i_#{full_name}_hw_write_enable", width: 1, array_size:
         }
         input :hw_write_data, {
-          name: "i_#{full_name}_hw_write_data", width: width, array_size: array_size
+          name: "i_#{full_name}_hw_write_data", width:, array_size:
         }
       end
       if bit_field.hw_set?
         input :hw_set, {
-          name: "i_#{full_name}_hw_set", width: width, array_size: array_size
+          name: "i_#{full_name}_hw_set", width:, array_size:
         }
       end
       if bit_field.hw_clear?
         input :hw_clear, {
-          name: "i_#{full_name}_hw_clear", width: width, array_size: array_size
+          name: "i_#{full_name}_hw_clear", width:, array_size:
         }
       end
       if bit_field.write_trigger?
         output :write_trigger, {
-          name: "o_#{full_name}_write_trigger", width: 1, array_size: array_size
+          name: "o_#{full_name}_write_trigger", width: 1, array_size:
         }
       end
       if bit_field.read_trigger?
         output :read_trigger, {
-          name: "o_#{full_name}_read_trigger", width: 1, array_size: array_size
+          name: "o_#{full_name}_read_trigger", width: 1, array_size:
         }
       end
     end

data/lib/rggen/vhdl/bit_field/type/rc_w0c_w1c_wc_woc.rb

@@ -4,14 +4,14 @@ RgGen.define_list_item_feature(:bit_field, :type, [:rc, :w0c, :w1c, :wc, :woc])
   vhdl do
     build do
       input :set, {
-        name: "i_#{full_name}_set", width: width, array_size: array_size
+        name: "i_#{full_name}_set", width:, array_size:
       }
       output :value_out, {
-        name: "o_#{full_name}", width: width, array_size: array_size
+        name: "o_#{full_name}", width:, array_size:
       }
       if bit_field.reference?
         output :value_unmasked, {
-          name: "o_#{full_name}_unmasked", width: width, array_size: array_size
+          name: "o_#{full_name}_unmasked", width:, array_size:
         }
       end
     end

data/lib/rggen/vhdl/bit_field/type/ro_rotrg.rb

@@ -5,12 +5,12 @@ RgGen.define_list_item_feature(:bit_field, :type, [:ro, :rotrg]) do
     build do
       unless bit_field.reference?
         input :value_in, {
-          name: "i_#{full_name}", width: width, array_size: array_size
+          name: "i_#{full_name}", width:, array_size:
         }
       end
       if rotrg?
         output :read_trigger, {
-          name: "o_#{full_name}_read_trigger", width: 1, array_size: array_size
+          name: "o_#{full_name}_read_trigger", width: 1, array_size:
         }
       end
     end

data/lib/rggen/vhdl/bit_field/type/rohw.rb

@@ -5,14 +5,14 @@ RgGen.define_list_item_feature(:bit_field, :type, :rohw) do
     build do
       unless bit_field.reference?
         input :valid, {
-          name: "i_#{full_name}_valid", width: 1, array_size: array_size
+          name: "i_#{full_name}_valid", width: 1, array_size:
         }
       end
       input :value_in, {
-        name: "i_#{full_name}", width: width, array_size: array_size
+        name: "i_#{full_name}", width:, array_size:
       }
       output :value_out, {
-        name: "o_#{full_name}", width: width, array_size: array_size
+        name: "o_#{full_name}", width:, array_size:
       }
     end
 

data/lib/rggen/vhdl/bit_field/type/row0trg_row1trg.rb

@@ -5,11 +5,11 @@ RgGen.define_list_item_feature(:bit_field, :type, [:row0trg, :row1trg]) do
     build do
       unless bit_field.reference?
         input :value_in, {
-          name: "i_#{full_name}", width: width, array_size: array_size
+          name: "i_#{full_name}", width:, array_size:
         }
       end
       output :trigger, {
-        name: "o_#{full_name}_trigger", width: width, array_size: array_size
+        name: "o_#{full_name}_trigger", width:, array_size:
       }
     end
 

data/lib/rggen/vhdl/bit_field/type/rowo_rowotrg.rb

@@ -4,19 +4,19 @@ RgGen.define_list_item_feature(:bit_field, :type, [:rowo, :rowotrg]) do
   vhdl do
     build do
       output :value_out, {
-        name: "o_#{full_name}", width: width, array_size: array_size
+        name: "o_#{full_name}", width:, array_size:
       }
       unless bit_field.reference?
         input :value_in, {
-          name: "i_#{full_name}", width: width, array_size: array_size
+          name: "i_#{full_name}", width:, array_size:
         }
       end
       if rowotrg?
         output :write_trigger, {
-          name: "o_#{full_name}_write_trigger", width: 1, array_size: array_size
+          name: "o_#{full_name}_write_trigger", width: 1, array_size:
         }
         output :read_trigger, {
-          name: "o_#{full_name}_read_trigger", width: 1, array_size: array_size
+          name: "o_#{full_name}_read_trigger", width: 1, array_size:
         }
       end
     end

data/lib/rggen/vhdl/bit_field/type/rs_w0s_w1s_ws_wos.rb

@@ -4,10 +4,10 @@ RgGen.define_list_item_feature(:bit_field, :type, [:rs, :w0s, :w1s, :ws, :wos])
   vhdl do
     build do
       input :clear, {
-        name: "i_#{full_name}_clear", width: width, array_size: array_size
+        name: "i_#{full_name}_clear", width:, array_size:
       }
       output :value_out, {
-        name: "o_#{full_name}", width: width, array_size: array_size
+        name: "o_#{full_name}", width:, array_size:
       }
     end
 

data/lib/rggen/vhdl/bit_field/type/rw_rwtrg_w1.rb

@@ -4,14 +4,14 @@ RgGen.define_list_item_feature(:bit_field, :type, [:rw, :rwtrg, :w1]) do
   vhdl do
     build do
       output :value_out, {
-        name: "o_#{full_name}", width: width, array_size: array_size
+        name: "o_#{full_name}", width:, array_size:
       }
       if rwtrg?
         output :write_trigger, {
-          name: "o_#{full_name}_write_trigger", width: 1, array_size: array_size
+          name: "o_#{full_name}_write_trigger", width: 1, array_size:
         }
         output :read_trigger, {
-          name: "o_#{full_name}_read_trigger", width: 1, array_size: array_size
+          name: "o_#{full_name}_read_trigger", width: 1, array_size:
         }
       end
     end

data/lib/rggen/vhdl/bit_field/type/rwc.rb

@@ -5,11 +5,11 @@ RgGen.define_list_item_feature(:bit_field, :type, :rwc) do
     build do
       unless bit_field.reference?
         input :clear, {
-          name: "i_#{full_name}_clear", width: 1, array_size: array_size
+          name: "i_#{full_name}_clear", width: 1, array_size:
         }
       end
       output :value_out, {
-        name: "o_#{full_name}", width: width, array_size: array_size
+        name: "o_#{full_name}", width:, array_size:
       }
     end
 

data/lib/rggen/vhdl/bit_field/type/rwe_rwl.rb

@@ -6,11 +6,11 @@ RgGen.define_list_item_feature(:bit_field, :type, [:rwe, :rwl]) do
       unless bit_field.reference?
         input :control, {
           name: "i_#{full_name}_#{enable_or_lock}",
-          width: 1, array_size: array_size
+          width: 1, array_size:
         }
       end
       output :value_out, {
-        name: "o_#{full_name}", width: width, array_size: array_size
+        name: "o_#{full_name}", width:, array_size:
       }
     end
 

data/lib/rggen/vhdl/bit_field/type/rwhw.rb

@@ -5,14 +5,14 @@ RgGen.define_list_item_feature(:bit_field, :type, :rwhw) do
     build do
       unless bit_field.reference?
         input :valid, {
-          name: "i_#{full_name}_valid", width: 1, array_size: array_size
+          name: "i_#{full_name}_valid", width: 1, array_size:
         }
       end
       input :value_in, {
-        name: "i_#{full_name}", width: width, array_size: array_size
+        name: "i_#{full_name}", width:, array_size:
       }
       output :value_out, {
-        name: "o_#{full_name}", width: width, array_size: array_size
+        name: "o_#{full_name}", width:, array_size:
       }
     end
 

data/lib/rggen/vhdl/bit_field/type/rws.rb

@@ -5,11 +5,11 @@ RgGen.define_list_item_feature(:bit_field, :type, :rws) do
     build do
       unless bit_field.reference?
         input :set, {
-          name: "i_#{full_name}_set", width: 1, array_size: array_size
+          name: "i_#{full_name}_set", width: 1, array_size:
         }
       end
       output :value_out, {
-        name: "o_#{full_name}", width: width, array_size: array_size
+        name: "o_#{full_name}", width:, array_size:
       }
     end
 

data/lib/rggen/vhdl/bit_field/type/w0crs_w0src_w1crs_w1src_wcrs_wsrc.rb

@@ -6,7 +6,7 @@ RgGen.define_list_item_feature(
   vhdl do
     build do
       output :value_out, {
-        name: "o_#{full_name}", width: width, array_size: array_size
+        name: "o_#{full_name}", width:, array_size:
       }
     end
 

data/lib/rggen/vhdl/bit_field/type/w0t_w1t.rb

@@ -4,7 +4,7 @@ RgGen.define_list_item_feature(:bit_field, :type, [:w0t, :w1t]) do
   vhdl do
     build do
       output :value_out, {
-        name: "o_#{full_name}", width: width, array_size: array_size
+        name: "o_#{full_name}", width:, array_size:
       }
     end
 

data/lib/rggen/vhdl/bit_field/type/w0trg_w1trg.rb

@@ -4,7 +4,7 @@ RgGen.define_list_item_feature(:bit_field, :type, [:w0trg, :w1trg]) do
   vhdl do
     build do
       output :trigger, {
-        name: "o_#{full_name}_trigger", width: width, array_size: array_size
+        name: "o_#{full_name}_trigger", width:, array_size:
       }
     end
 

data/lib/rggen/vhdl/bit_field/type/wo_wo1_wotrg.rb

@@ -4,11 +4,11 @@ RgGen.define_list_item_feature(:bit_field, :type, [:wo, :wo1, :wotrg]) do
   vhdl do
     build do
       output :value_out, {
-        name: "o_#{full_name}", width: width, array_size: array_size
+        name: "o_#{full_name}", width:, array_size:
       }
       if wotrg?
         output :write_trigger, {
-          name: "o_#{full_name}_write_trigger", width: 1, array_size: array_size
+          name: "o_#{full_name}_write_trigger", width: 1, array_size:
         }
       end
     end

data/lib/rggen/vhdl/bit_field/type/wrc_wrs.rb

@@ -4,7 +4,7 @@ RgGen.define_list_item_feature(:bit_field, :type, [:wrc, :wrs]) do
   vhdl do
     build do
       output :value_out, {
-        name: "o_#{full_name}", width: width, array_size: array_size
+        name: "o_#{full_name}", width:, array_size:
       }
     end
 

data/lib/rggen/vhdl/bit_field/type.rb

@@ -26,7 +26,7 @@ RgGen.define_list_feature(:bit_field, :type) do
       end
 
       def initial_value
-        index = bit_field.initial_value_array? && bit_field.local_index || 0
+        index = bit_field.initial_value_array? && bit_field.flat_loop_index || 0
         "slice(#{bit_field.initial_value}, #{width}, #{index})"
       end
 
@@ -70,7 +70,7 @@ RgGen.define_list_feature(:bit_field, :type) do
         bit_field.reference? &&
           bit_field
             .find_reference(register_block.bit_fields)
-            .value(bit_field.local_indices, bit_field.reference_width)
+            .value(bit_field.local_indexes, bit_field.reference_width)
       end
 
       def loop_variables

data/lib/rggen/vhdl/bit_field/vhdl_top.rb

@@ -43,15 +43,17 @@ RgGen.define_simple_feature(:bit_field, :vhdl_top) do
 
     def initial_value_width
       width = bit_field.width
-      repeat_size = bit_field.sequence_size || 1
-      width * repeat_size
+      width * initial_value_repeat_size
     end
 
     def default_initial_value
       width = bit_field.width
-      repeat_size = bit_field.sequence_size || 1
       value = initial_value_rhs_default
-      "repeat(#{value}, #{width}, #{repeat_size})"
+      "repeat(#{value}, #{width}, #{initial_value_repeat_size})"
+    end
+
+    def initial_value_repeat_size
+      array_size&.inject(:*) || 1
     end
 
     def define_accessor_for_initial_value
@@ -70,14 +72,15 @@ RgGen.define_simple_feature(:bit_field, :vhdl_top) do
 
     def array_initial_value_rhs
       value =
-        bit_field.initial_values
+        bit_field
+          .initial_values(flatten: true)
           .map.with_index { |v, i| v << bit_field.width * i }
           .inject(:|)
-      hex(value, bit_field.sequence_size * bit_field.width)
+      hex(value, initial_value_width)
     end
 
     def register_value(offsets, lsb, width)
-      index = register.index(offsets || register.local_indices)
+      index = register.index(offsets || register.local_indexes)
       register_block.register_value[[index], lsb, width]
     end
 

data/lib/rggen/vhdl/feature.rb

@@ -7,19 +7,19 @@ module RgGen
 
       private
 
-      def create_signal(_, attributes, &block)
-        DataObject.new(:signal, attributes, &block)
+      def create_signal(_, attributes, &)
+        DataObject.new(:signal, attributes, &)
       end
 
-      def create_port(direction, attributes, &block)
+      def create_port(direction, attributes, &)
         attributes =
           attributes
             .merge(direction: { input: :in, output: :out }[direction])
-        DataObject.new(:port, attributes, &block)
+        DataObject.new(:port, attributes, &)
       end
 
-      def create_generic(_, attributes, &block)
-        DataObject.new(:generic, attributes, &block)
+      def create_generic(_, attributes, &)
+        DataObject.new(:generic, attributes, &)
       end
 
       define_entity :signal, :create_signal, :signal, -> { component }

data/lib/rggen/vhdl/register/type/external.rb

@@ -5,7 +5,7 @@ RgGen.define_list_item_feature(:register, :type, :external) do
     build do
       generic :strobe_width, {
         name: "#{register.name}_STROBE_WIDTH".upcase,
-        type: :positive, default: configuration.bus_width / 8
+        type: :positive, default: register_block.byte_width
       }
       output :external_valid, {
         name: "o_#{register.name}_valid"

data/lib/rggen/vhdl/register/type.rb

@@ -98,7 +98,7 @@ RgGen.define_list_feature(:register, :type) do
 
       def format_offsets(offsets)
         if integer?(offsets.first)
-          super(offsets)
+          super
         else
           super([0, *offsets])
         end

data/lib/rggen/vhdl/register_block/protocol/avalon.erb

@@ -0,0 +1,33 @@
+u_adapter: entity <%= library_name %>.rggen_avalon_adapter
+  generic map (
+    ADDRESS_WIDTH       => <%= address_width %>,
+    LOCAL_ADDRESS_WIDTH => <%= local_address_width %>,
+    BUS_WIDTH           => <%= bus_width %>,
+    REGISTERS           => <%= total_registers %>,
+    PRE_DECODE          => <%= pre_decode %>,
+    BASE_ADDRESS        => <%= base_address %>,
+    BYTE_SIZE           => <%= byte_size %>,
+    ERROR_STATUS        => <%= error_status %>,
+    INSERT_SLICER       => <%= insert_slicer %>
+  )
+  port map (
+    i_clk                 => <%= register_block.clock %>,
+    i_rst_n               => <%= register_block.reset %>,
+    i_read                => <%= read %>,
+    i_write               => <%= write %>,
+    i_address             => <%= address %>,
+    i_byteenable          => <%= byteenable %>,
+    i_writedata           => <%= writedata %>,
+    o_waitrequest         => <%= waitrequest %>,
+    o_response            => <%= response %>,
+    o_readdata            => <%= readdata %>,
+    o_register_valid      => <%= register_block.register_valid %>,
+    o_register_access     => <%= register_block.register_access %>,
+    o_register_address    => <%= register_block.register_address %>,
+    o_register_write_data => <%= register_block.register_write_data %>,
+    o_register_strobe     => <%= register_block.register_strobe %>,
+    i_register_active     => <%= register_block.register_active %>,
+    i_register_ready      => <%= register_block.register_ready %>,
+    i_register_status     => <%= register_block.register_status %>,
+    i_register_read_data  => <%= register_block.register_read_data %>
+  );

data/lib/rggen/vhdl/register_block/protocol/avalon.rb

@@ -0,0 +1,34 @@
+# frozen_string_literal: true
+
+RgGen.define_list_item_feature(:register_block, :protocol, :avalon) do
+  vhdl do
+    build do
+      input :read, {
+        name: 'i_read'
+      }
+      input :write, {
+        name: 'i_write'
+      }
+      input :address, {
+        name: 'i_address', width: address_width
+      }
+      input :byteenable, {
+        name: 'i_byteenable', width: bus_width / 8
+      }
+      input :writedata, {
+        name: 'i_writedata', width: bus_width
+      }
+      output :waitrequest, {
+        name: 'o_waitrequest'
+      }
+      output :response, {
+        name: 'o_response', width: 2
+      }
+      output :readdata, {
+        name: 'o_readdata', width: bus_width
+      }
+    end
+
+    main_code :register_block, from_template: true
+  end
+end

data/lib/rggen/vhdl/register_block/protocol/native.erb

@@ -0,0 +1,35 @@
+u_adapter: entity <%= library_name %>.rggen_native_adapter
+  generic map (
+    ADDRESS_WIDTH       => <%= address_width %>,
+    LOCAL_ADDRESS_WIDTH => <%= local_address_width %>,
+    BUS_WIDTH           => <%= bus_width %>,
+    STROBE_WIDTH        => <%= strobe_width %>,
+    REGISTERS           => <%= total_registers %>,
+    PRE_DECODE          => <%= pre_decode %>,
+    BASE_ADDRESS        => <%= base_address %>,
+    BYTE_SIZE           => <%= byte_size %>,
+    USE_READ_STROBE     => <%= use_read_strobe %>,
+    ERROR_STATUS        => <%= error_status %>,
+    INSERT_SLICER       => <%= insert_slicer %>
+  )
+  port map (
+    i_clk                 => <%= register_block.clock %>,
+    i_rst_n               => <%= register_block.reset %>,
+    i_csrbus_valid        => <%= valid %>,
+    i_csrbus_access       => <%= access %>,
+    i_csrbus_address      => <%= address %>,
+    i_csrbus_write_data   => <%= write_data %>,
+    i_csrbus_strobe       => <%= strobe %>,
+    o_csrbus_ready        => <%= ready %>,
+    o_csrbus_status       => <%= status %>,
+    o_csrbus_read_data    => <%= read_data %>,
+    o_register_valid      => <%= register_block.register_valid %>,
+    o_register_access     => <%= register_block.register_access %>,
+    o_register_address    => <%= register_block.register_address %>,
+    o_register_write_data => <%= register_block.register_write_data %>,
+    o_register_strobe     => <%= register_block.register_strobe %>,
+    i_register_active     => <%= register_block.register_active %>,
+    i_register_ready      => <%= register_block.register_ready %>,
+    i_register_status     => <%= register_block.register_status %>,
+    i_register_read_data  => <%= register_block.register_read_data %>
+  );

data/lib/rggen/vhdl/register_block/protocol/native.rb

@@ -0,0 +1,25 @@
+# frozen_string_literal: true
+
+RgGen.define_list_item_feature(:register_block, :protocol, :native) do
+  vhdl do
+    build do
+      generic :strobe_width, {
+        name: 'STROBE_WIDTH', type: :positive, default: bus_width / 8
+      }
+      generic :use_read_strobe, {
+        name: 'USE_READ_STROBE', type: :boolean, default: false
+      }
+
+      input :valid, { name: 'i_csrbus_valid' }
+      input :access, { name: 'i_csrbus_access', width: 2 }
+      input :address, { name: 'i_csrbus_address', width: address_width }
+      input :write_data, { name: 'i_csrbus_write_data', width: bus_width }
+      input :strobe, { name: 'i_csrbus_strobe', width: strobe_width }
+      output :ready, { name: 'o_csrbus_ready' }
+      output :status, { name: 'o_csrbus_status', width: 2 }
+      output :read_data, { name: 'o_csrbus_read_data', width: bus_width }
+    end
+
+    main_code :register_block, from_template: true
+  end
+end

data/lib/rggen/vhdl/register_block/protocol.rb

@@ -30,7 +30,7 @@ RgGen.define_list_feature(:register_block, :protocol) do
       end
 
       def bus_width
-        configuration.bus_width
+        register_block.bus_width
       end
 
       def local_address_width
@@ -47,8 +47,8 @@ RgGen.define_list_feature(:register_block, :protocol) do
     end
 
     factory do
-      def target_feature_key(configuration, _register_block)
-        configuration.protocol
+      def target_feature_key(_configuration, register_block)
+        register_block.protocol
       end
     end
   end

data/lib/rggen/vhdl/register_block/vhdl_top.rb

@@ -59,7 +59,7 @@ RgGen.define_simple_feature(:register_block, :vhdl_top) do
     end
 
     def bus_width
-      configuration.bus_width
+      register_block.bus_width
     end
 
     def value_width

data/lib/rggen/vhdl/register_map/keyword_checker.rb

@@ -0,0 +1,40 @@
+# frozen_string_literal: true
+
+module RgGen
+  module VHDL
+    module RegisterMap
+      module KeywordChecker
+        VHDL_KEYWORDS = [
+          'abs', 'access', 'after', 'alias', 'all', 'and', 'architecture', 'array',
+          'assert', 'assume', 'attribute', 'begin', 'block', 'body', 'buffer', 'bus',
+          'case', 'component', 'configuration', 'constant', 'context', 'cover', 'default',
+          'disconnect', 'downto', 'else', 'elsif', 'end', 'entity', 'exit', 'fairness',
+          'file', 'for', 'force', 'function', 'generate', 'generic', 'group', 'guarded',
+          'if', 'impure', 'in', 'inertial', 'inout', 'is', 'label', 'library', 'linkage',
+          'literal', 'loop', 'map', 'mod', 'nand', 'new', 'next', 'nor', 'not', 'null',
+          'of', 'on', 'open', 'or', 'others', 'out', 'package', 'parameter', 'port',
+          'postponed', 'procedure', 'process', 'property', 'protected', 'private', 'pure',
+          'range', 'record', 'register', 'reject', 'release', 'rem', 'report', 'restrict',
+          'return', 'rol', 'ror', 'select', 'sequence', 'severity', 'signal', 'shared',
+          'sla', 'sll', 'sra', 'srl', 'strong', 'subtype', 'then', 'to', 'transport',
+          'type', 'unaffected', 'units', 'until', 'use', 'variable', 'view', 'vpkg',
+          'vmode', 'vprop', 'vunit', 'wait', 'when', 'while', 'with', 'xnor', 'xor'
+        ].freeze
+
+        def self.included(klass)
+          klass.class_eval do
+            verify(:feature, prepend: true) do
+              error_condition do
+                @name && VHDL_KEYWORDS.any? { |kw| kw.casecmp?(@name) }
+              end
+              message do
+                layer_name = component.layer.to_s.sub('_', ' ')
+                "vhdl keyword is not allowed for #{layer_name} name: #{@name.downcase}"
+              end
+            end
+          end
+        end
+      end
+    end
+  end
+end

data/lib/rggen/vhdl/register_map/name.rb

@@ -0,0 +1,9 @@
+# frozen_string_literal: true
+
+[:register_block, :register_file, :register, :bit_field].each do |layer|
+  RgGen.modify_simple_feature(layer, :name) do
+    register_map do
+      include RgGen::VHDL::RegisterMap::KeywordChecker
+    end
+  end
+end

data/lib/rggen/vhdl/utility.rb

@@ -24,8 +24,8 @@ module RgGen
         expression
       end
 
-      def local_scope(scope_name, attributes = {}, &block)
-        LocalScope.new(attributes.merge(name: scope_name), &block).to_code
+      def local_scope(scope_name, attributes = {}, &)
+        LocalScope.new(attributes.merge(name: scope_name), &).to_code
       end
     end
   end

data/lib/rggen/vhdl/version.rb

@@ -2,6 +2,6 @@
 
 module RgGen
   module VHDL
-    VERSION = '0.10.1'
+    VERSION = '0.12.0'
   end
 end

data/lib/rggen/vhdl.rb

@@ -9,6 +9,7 @@ require_relative 'vhdl/utility'
 require_relative 'vhdl/component'
 require_relative 'vhdl/feature'
 require_relative 'vhdl/factories'
+require_relative 'vhdl/register_map/keyword_checker'
 
 RgGen.setup_plugin :'rggen-vhdl' do |plugin|
   plugin.version RgGen::VHDL::VERSION
@@ -26,7 +27,9 @@ RgGen.setup_plugin :'rggen-vhdl' do |plugin|
     'vhdl/register_block/protocol',
     'vhdl/register_block/protocol/apb',
     'vhdl/register_block/protocol/axi4lite',
+    'vhdl/register_block/protocol/avalon',
     'vhdl/register_block/protocol/wishbone',
+    'vhdl/register_block/protocol/native',
     'vhdl/register_file/vhdl_top',
     'vhdl/register/vhdl_top',
     'vhdl/register/type',
@@ -54,4 +57,8 @@ RgGen.setup_plugin :'rggen-vhdl' do |plugin|
     'vhdl/bit_field/type/wo_wo1_wotrg',
     'vhdl/bit_field/type/wrc_wrs'
   ]
+
+  plugin.files [
+    'vhdl/register_map/name'
+  ]
 end

metadata

@@ -1,14 +1,13 @@
 --- !ruby/object:Gem::Specification
 name: rggen-vhdl
 version: !ruby/object:Gem::Version
-  version: 0.10.1
+  version: 0.12.0
 platform: ruby
 authors:
 - Taichi Ishitani
-autorequire: 
 bindir: bin
 cert_chain: []
-date: 2024-11-28 00:00:00.000000000 Z
+date: 2025-02-19 00:00:00.000000000 Z
 dependencies:
 - !ruby/object:Gem::Dependency
   name: rggen-systemverilog
@@ -16,14 +15,14 @@ dependencies:
     requirements:
     - - ">="
       - !ruby/object:Gem::Version
-        version: 0.33.1
+        version: 0.35.0
   type: :runtime
   prerelease: false
   version_requirements: !ruby/object:Gem::Requirement
     requirements:
     - - ">="
       - !ruby/object:Gem::Version
-        version: 0.33.1
+        version: 0.35.0
 description: VHDL writer plugin for RgGen
 email:
 - rggen@googlegroups.com
@@ -90,13 +89,19 @@ files:
 - lib/rggen/vhdl/register_block/protocol.rb
 - lib/rggen/vhdl/register_block/protocol/apb.erb
 - lib/rggen/vhdl/register_block/protocol/apb.rb
+- lib/rggen/vhdl/register_block/protocol/avalon.erb
+- lib/rggen/vhdl/register_block/protocol/avalon.rb
 - lib/rggen/vhdl/register_block/protocol/axi4lite.erb
 - lib/rggen/vhdl/register_block/protocol/axi4lite.rb
+- lib/rggen/vhdl/register_block/protocol/native.erb
+- lib/rggen/vhdl/register_block/protocol/native.rb
 - lib/rggen/vhdl/register_block/protocol/wishbone.erb
 - lib/rggen/vhdl/register_block/protocol/wishbone.rb
 - lib/rggen/vhdl/register_block/vhdl_top.erb
 - lib/rggen/vhdl/register_block/vhdl_top.rb
 - lib/rggen/vhdl/register_file/vhdl_top.rb
+- lib/rggen/vhdl/register_map/keyword_checker.rb
+- lib/rggen/vhdl/register_map/name.rb
 - lib/rggen/vhdl/utility.rb
 - lib/rggen/vhdl/utility/data_object.rb
 - lib/rggen/vhdl/utility/identifier.rb
@@ -111,7 +116,6 @@ metadata:
   rubygems_mfa_required: 'true'
   source_code_uri: https://github.com/rggen/rggen-vhdl
   wiki_uri: https://github.com/rggen/rggen/wiki
-post_install_message: 
 rdoc_options: []
 require_paths:
 - lib
@@ -119,15 +123,14 @@ required_ruby_version: !ruby/object:Gem::Requirement
   requirements:
   - - ">="
     - !ruby/object:Gem::Version
-      version: 3.0.0
+      version: '3.1'
 required_rubygems_version: !ruby/object:Gem::Requirement
   requirements:
   - - ">="
     - !ruby/object:Gem::Version
       version: '0'
 requirements: []
-rubygems_version: 3.5.16
-signing_key: 
+rubygems_version: 3.6.2
 specification_version: 4
-summary: rggen-vhdl-0.10.1
+summary: rggen-vhdl-0.12.0
 test_files: []