rggen-vhdl 0.1.0 → 0.3.0

checksums.yaml

@@ -1,7 +1,7 @@
 ---
 SHA256:
-  metadata.gz: 06a1c6755b2a8f179607870c8d2d5a24b770008fce59619c3cdad8364da46161
-  data.tar.gz: 42961741bd866c5e5ed2e4d3e99026214e6dfa499919abda73c3f882b55196f7
+  metadata.gz: a3fe2a4f117ebddd32c38f4e65d042c845f81e85f6130d7f85ebf94f7b12868f
+  data.tar.gz: 55c35ac2e82232c2fba80da4ec23ad0bb417cb35c228b3e94a76ee134f747f54
 SHA512:
-  metadata.gz: 97ea8805f99296c3cabd602164a3c919d54fbb7b19d66685884ce7da31987d14001d944f2e1856216bd059e1d3fa09945532b357e27f7fd22378f8f6633c9c63
-  data.tar.gz: 1cccbac061bd475c8a2af1f9c569c59269274ff91b41da806e77ccc94429c113bdd169f7a668777409e1a127e934bcc76fcdb1689f75b6388c75840eb833f589
+  metadata.gz: 1e1d50c4f6eea7cfd80de27beac4e2f451d8913d13b77976776e0c021252dc53da2aa1227ed5b587f905d30aa54d66437e4af795bc15cea9626f8a7076bc521f
+  data.tar.gz: 0fa49c35d10ddfe2c4d680780dd3f40ef0a8dc64aa4808cc352c55261ccf9d8d754aa450643bdacf1072b86f88ce880050851afcf09001a091ea25f0439353e3

data/LICENSE

@@ -1,6 +1,6 @@
 The MIT License (MIT)
 
-Copyright (c) 2021 Taichi Ishitani
+Copyright (c) 2021 - 2022 Taichi Ishitani
 
 Permission is hereby granted, free of charge, to any person obtaining a copy
 of this software and associated documentation files (the "Software"), to deal

data/README.md

@@ -60,14 +60,15 @@ $ simulator \
 
 Feedbacks, bus reports, questions and etc. are welcome! You can post them bu using following ways:
 
-* [GitHub Issue Tracker](https://github.com/rggen/rggen-vhdl/issues)
+* [GitHub Issue Tracker](https://github.com/rggen/rggen/issues)
+* [GitHub Discussions](https://github.com/rggen/rggen/discussions)
 * [Chat Room](https://gitter.im/rggen/rggen)
 * [Mailing List](https://groups.google.com/d/forum/rggen)
 * [Mail](mailto:rggen@googlegroups.com)
 
 ## Copyright & License
 
-Copyright © 2021 Taichi Ishitani. RgGen::VHDL is licensed under the [MIT License](https://opensource.org/licenses/MIT), see [LICENSE](LICENSE) for futher details.
+Copyright © 2021 - 2022 Taichi Ishitani. RgGen::VHDL is licensed under the [MIT License](https://opensource.org/licenses/MIT), see [LICENSE](LICENSE) for futher details.
 
 ## Code of Conduct
 

data/lib/rggen/vhdl/bit_field/type/rc_w0c_w1c_wc_woc.erb

@@ -16,6 +16,8 @@ u_bit_field: entity work.rggen_bit_field
     i_sw_write_data   => <%= bit_field_write_data %>,
     o_sw_read_data    => <%= bit_field_read_data %>,
     o_sw_value        => <%= bit_field_value %>,
+    o_write_trigger   => open,
+    o_read_trigger    => open,
     i_hw_write_enable => "0",
     i_hw_write_data   => (others => '0'),
     i_hw_set          => <%= set[loop_variables] %>,

data/lib/rggen/vhdl/bit_field/type/{ro.erb → ro_rotrg.erb}

@@ -1,11 +1,13 @@
 u_bit_field: entity work.rggen_bit_field
   generic map (
-    WIDTH   => <%= width %>,
-    STORAGE => false
+    WIDTH               => <%= width %>,
+    STORAGE             => false,
+    EXTERNAL_READ_DATA  => true,
+    TRIGGER             => <%= rotrg? %>
   )
   port map (
-    i_clk             => '0',
-    i_rst_n           => '0',
+    i_clk             => <%= clock %>,
+    i_rst_n           => <%= reset %>,
     i_sw_valid        => <%= bit_field_valid %>,
     i_sw_read_mask    => <%= bit_field_read_mask %>,
     i_sw_write_enable => "0",
@@ -13,6 +15,8 @@ u_bit_field: entity work.rggen_bit_field
     i_sw_write_data   => <%= bit_field_write_data %>,
     o_sw_read_data    => <%= bit_field_read_data %>,
     o_sw_value        => <%= bit_field_value %>,
+    o_write_trigger   => open,
+    o_read_trigger    => <%= read_trigger_signal %>,
     i_hw_write_enable => "0",
     i_hw_write_data   => (others => '0'),
     i_hw_set          => (others => '0'),

data/lib/rggen/vhdl/bit_field/type/ro_rotrg.rb

@@ -0,0 +1,34 @@
+# frozen_string_literal: true
+
+RgGen.define_list_item_feature(:bit_field, :type, [:ro, :rotrg]) do
+  vhdl do
+    build do
+      unless bit_field.reference?
+        input :value_in, {
+          name: "i_#{full_name}", width: width, array_size: array_size
+        }
+      end
+      if rotrg?
+        output :read_trigger, {
+          name: "o_#{full_name}_read_trigger", width: 1, array_size: array_size
+        }
+      end
+    end
+
+    main_code :bit_field, from_template: true
+
+    private
+
+    def rotrg?
+      bit_field.type == :rotrg
+    end
+
+    def read_trigger_signal
+      rotrg? && read_trigger[loop_variables] || 'open'
+    end
+
+    def reference_or_value_in
+      reference_bit_field || value_in[loop_variables]
+    end
+  end
+end

data/lib/rggen/vhdl/bit_field/type/rof.erb

@@ -1,7 +1,8 @@
 u_bit_field: entity work.rggen_bit_field
   generic map (
-    WIDTH   => <%= width %>,
-    STORAGE => false
+    WIDTH               => <%= width %>,
+    STORAGE             => false,
+    EXTERNAL_READ_DATA  => true
   )
   port map (
     i_clk             => '0',
@@ -13,6 +14,8 @@ u_bit_field: entity work.rggen_bit_field
     i_sw_write_data   => <%= bit_field_write_data %>,
     o_sw_read_data    => <%= bit_field_read_data %>,
     o_sw_value        => <%= bit_field_value %>,
+    o_write_trigger   => open,
+    o_read_trigger    => open,
     i_hw_write_enable => "0",
     i_hw_write_data   => (others => '0'),
     i_hw_set          => (others => '0'),

data/lib/rggen/vhdl/bit_field/type/row0trg_row1trg.erb

@@ -0,0 +1,18 @@
+u_bit_field: entity work.rggen_bit_field_w01trg
+  generic map (
+    WRITE_ONE_TRIGGER => <%= write_one_trigger? %>,
+    WIDTH             => <%= width %>
+  )
+  port map (
+    i_clk             => i_clk,
+    i_rst_n           => i_rst_n,
+    i_sw_valid        => <%= bit_field_valid %>,
+    i_sw_read_mask    => <%= bit_field_read_mask %>,
+    i_sw_write_enable => "1",
+    i_sw_write_mask   => <%= bit_field_write_mask %>,
+    i_sw_write_data   => <%= bit_field_write_data %>,
+    o_sw_read_data    => <%= bit_field_read_data %>,
+    o_sw_value        => <%= bit_field_value %>,
+    i_value           => <%= reference_or_value_in %>,
+    o_trigger         => <%= trigger[loop_variables] %>
+  );

data/lib/rggen/vhdl/bit_field/type/{ro.rb → row0trg_row1trg.rb}

@@ -1,6 +1,6 @@
 # frozen_string_literal: true
 
-RgGen.define_list_item_feature(:bit_field, :type, :ro) do
+RgGen.define_list_item_feature(:bit_field, :type, [:row0trg, :row1trg]) do
   vhdl do
     build do
       unless bit_field.reference?
@@ -8,14 +8,21 @@ RgGen.define_list_item_feature(:bit_field, :type, :ro) do
           name: "i_#{full_name}", width: width, array_size: array_size
         }
       end
+      output :trigger, {
+        name: "o_#{full_name}_trigger", width: width, array_size: array_size
+      }
     end
 
     main_code :bit_field, from_template: true
 
     private
 
+    def write_one_trigger?
+      bit_field.type == :row1trg
+    end
+
     def reference_or_value_in
-      bit_field.reference? && reference_bit_field || value_in[loop_variables]
+      reference_bit_field || value_in[loop_variables]
     end
   end
 end

data/lib/rggen/vhdl/bit_field/type/rowo_rowotrg.erb

@@ -0,0 +1,28 @@
+u_bit_field: entity work.rggen_bit_field
+  generic map (
+    WIDTH               => <%= width %>,
+    INITIAL_VALUE       => <%= initial_value %>,
+    EXTERNAL_READ_DATA  => true,
+    TRIGGER             => <%= rowotrg? %>
+  )
+  port map (
+    i_clk             => <%= clock %>,
+    i_rst_n           => <%= reset %>,
+    i_sw_valid        => <%= bit_field_valid %>,
+    i_sw_read_mask    => <%= bit_field_read_mask %>,
+    i_sw_write_enable => "1",
+    i_sw_write_mask   => <%= bit_field_write_mask %>,
+    i_sw_write_data   => <%= bit_field_write_data %>,
+    o_sw_read_data    => <%= bit_field_read_data %>,
+    o_sw_value        => <%= bit_field_value %>,
+    o_write_trigger   => <%= write_trigger_signal %>,
+    o_read_trigger    => <%= read_trigger_signal %>,
+    i_hw_write_enable => "0",
+    i_hw_write_data   => (others => '0'),
+    i_hw_set          => (others => '0'),
+    i_hw_clear        => (others => '0'),
+    i_value           => <%= reference_or_value_in %>,
+    i_mask            => (others => '1'),
+    o_value           => <%= value_out[loop_variables] %>,
+    o_value_unmasked  => open
+  );

data/lib/rggen/vhdl/bit_field/type/rowo_rowotrg.rb

@@ -0,0 +1,44 @@
+# frozen_string_literal: true
+
+RgGen.define_list_item_feature(:bit_field, :type, [:rowo, :rowotrg]) do
+  vhdl do
+    build do
+      output :value_out, {
+        name: "o_#{full_name}", width: width, array_size: array_size
+      }
+      unless bit_field.reference?
+        input :value_in, {
+          name: "i_#{full_name}", width: width, array_size: array_size
+        }
+      end
+      if rowotrg?
+        output :write_trigger, {
+          name: "o_#{full_name}_write_trigger", width: 1, array_size: array_size
+        }
+        output :read_trigger, {
+          name: "o_#{full_name}_read_trigger", width: 1, array_size: array_size
+        }
+      end
+    end
+
+    main_code :bit_field, from_template: true
+
+    private
+
+    def rowotrg?
+      bit_field.type == :rowotrg
+    end
+
+    def write_trigger_signal
+      rowotrg? && write_trigger[loop_variables] || 'open'
+    end
+
+    def read_trigger_signal
+      rowotrg? && read_trigger[loop_variables] || 'open'
+    end
+
+    def reference_or_value_in
+      reference_bit_field || value_in[loop_variables]
+    end
+  end
+end

data/lib/rggen/vhdl/bit_field/type/rs_w0s_w1s_ws_wos.erb

@@ -16,6 +16,8 @@ u_bit_field: entity work.rggen_bit_field
     i_sw_write_data   => <%= bit_field_write_data %>,
     o_sw_read_data    => <%= bit_field_read_data %>,
     o_sw_value        => <%= bit_field_value %>,
+    o_write_trigger   => open,
+    o_read_trigger    => open,
     i_hw_write_enable => "0",
     i_hw_write_data   => (others => '0'),
     i_hw_set          => (others => '0'),

data/lib/rggen/vhdl/bit_field/type/{rw_w1_wo_wo1.erb → rw_rwtrg_w1.erb}

@@ -2,8 +2,8 @@ u_bit_field: entity work.rggen_bit_field
   generic map (
     WIDTH           => <%= width %>,
     INITIAL_VALUE   => <%= initial_value %>,
-    SW_READ_ACTION  => <%= read_action %>,
-    SW_WRITE_ONCE   => <%= write_once %>
+    SW_WRITE_ONCE   => <%= write_once %>,
+    TRIGGER         => <%= rwtrg? %>
   )
   port map (
     i_clk             => <%= clock %>,
@@ -15,6 +15,8 @@ u_bit_field: entity work.rggen_bit_field
     i_sw_write_data   => <%= bit_field_write_data %>,
     o_sw_read_data    => <%= bit_field_read_data %>,
     o_sw_value        => <%= bit_field_value %>,
+    o_write_trigger   => <%= write_trigger_signal %>,
+    o_read_trigger    => <%= read_trigger_signal %>,
     i_hw_write_enable => "0",
     i_hw_write_data   => (others => '0'),
     i_hw_set          => (others => '0'),

data/lib/rggen/vhdl/bit_field/type/rw_rwtrg_w1.rb

@@ -0,0 +1,39 @@
+# frozen_string_literal: true
+
+RgGen.define_list_item_feature(:bit_field, :type, [:rw, :rwtrg, :w1]) do
+  vhdl do
+    build do
+      output :value_out, {
+        name: "o_#{full_name}", width: width, array_size: array_size
+      }
+      if rwtrg?
+        output :write_trigger, {
+          name: "o_#{full_name}_write_trigger", width: 1, array_size: array_size
+        }
+        output :read_trigger, {
+          name: "o_#{full_name}_read_trigger", width: 1, array_size: array_size
+        }
+      end
+    end
+
+    main_code :bit_field, from_template: true
+
+    private
+
+    def rwtrg?
+      bit_field.type == :rwtrg
+    end
+
+    def write_once
+      bit_field.type == :w1
+    end
+
+    def write_trigger_signal
+      rwtrg? && write_trigger[loop_variables] || 'open'
+    end
+
+    def read_trigger_signal
+      rwtrg? && read_trigger[loop_variables] || 'open'
+    end
+  end
+end

data/lib/rggen/vhdl/bit_field/type/rwc.erb

@@ -14,6 +14,8 @@ u_bit_field: entity work.rggen_bit_field
     i_sw_write_data   => <%= bit_field_write_data %>,
     o_sw_read_data    => <%= bit_field_read_data %>,
     o_sw_value        => <%= bit_field_value %>,
+    o_write_trigger   => open,
+    o_read_trigger    => open,
     i_hw_write_enable => "0",
     i_hw_write_data   => (others => '0'),
     i_hw_set          => (others => '0'),

data/lib/rggen/vhdl/bit_field/type/rwe_rwl.erb

@@ -14,6 +14,8 @@ u_bit_field: entity work.rggen_bit_field
     i_sw_write_data   => <%= bit_field_write_data %>,
     o_sw_read_data    => <%= bit_field_read_data %>,
     o_sw_value        => <%= bit_field_value %>,
+    o_write_trigger   => open,
+    o_read_trigger    => open,
     i_hw_write_enable => "0",
     i_hw_write_data   => (others => '0'),
     i_hw_set          => (others => '0'),

data/lib/rggen/vhdl/bit_field/type/rws.erb

@@ -13,6 +13,8 @@ u_bit_field: entity work.rggen_bit_field
     i_sw_write_data   => <%= bit_field_write_data %>,
     o_sw_read_data    => <%= bit_field_read_data %>,
     o_sw_value        => <%= bit_field_value %>,
+    o_write_trigger   => open,
+    o_read_trigger    => open,
     i_hw_write_enable => <%= set_signal %>,
     i_hw_write_data   => <%= value_in[loop_variables] %>,
     i_hw_set          => (others => '0'),

data/lib/rggen/vhdl/bit_field/type/w0crs_w0src_w1crs_w1src_wcrs_wsrc.erb

@@ -15,6 +15,8 @@ u_bit_field: entity work.rggen_bit_field
     i_sw_write_data   => <%= bit_field_write_data %>,
     o_sw_read_data    => <%= bit_field_read_data %>,
     o_sw_value        => <%= bit_field_value %>,
+    o_write_trigger   => open,
+    o_read_trigger    => open,
     i_hw_write_enable => "0",
     i_hw_write_data   => (others => '0'),
     i_hw_set          => (others => '0'),

data/lib/rggen/vhdl/bit_field/type/w0t_w1t.erb

@@ -14,6 +14,8 @@ u_bit_field: entity work.rggen_bit_field
     i_sw_write_data   => <%= bit_field_write_data %>,
     o_sw_read_data    => <%= bit_field_read_data %>,
     o_sw_value        => <%= bit_field_value %>,
+    o_write_trigger   => open,
+    o_read_trigger    => open,
     i_hw_write_enable => "0",
     i_hw_write_data   => (others => '0'),
     i_hw_set          => (others => '0'),

data/lib/rggen/vhdl/bit_field/type/w0trg_w1trg.erb

@@ -13,5 +13,6 @@ u_bit_field: entity work.rggen_bit_field_w01trg
     i_sw_write_data   => <%= bit_field_write_data %>,
     o_sw_read_data    => <%= bit_field_read_data %>,
     o_sw_value        => <%= bit_field_value %>,
+    i_value           => (others => '0'),
     o_trigger         => <%= trigger[loop_variables] %>
   );

data/lib/rggen/vhdl/bit_field/type/wo_wo1_wotrg.erb

@@ -0,0 +1,29 @@
+u_bit_field: entity work.rggen_bit_field
+  generic map (
+    WIDTH           => <%= width %>,
+    INITIAL_VALUE   => <%= initial_value %>,
+    SW_READ_ACTION  => RGGEN_READ_NONE,
+    SW_WRITE_ONCE   => <%= write_once %>,
+    TRIGGER         => <%= wotrg? %>
+  )
+  port map (
+    i_clk             => <%= clock %>,
+    i_rst_n           => <%= reset %>,
+    i_sw_valid        => <%= bit_field_valid %>,
+    i_sw_read_mask    => <%= bit_field_read_mask %>,
+    i_sw_write_enable => "1",
+    i_sw_write_mask   => <%= bit_field_write_mask %>,
+    i_sw_write_data   => <%= bit_field_write_data %>,
+    o_sw_read_data    => <%= bit_field_read_data %>,
+    o_sw_value        => <%= bit_field_value %>,
+    o_write_trigger   => <%= write_trigger_signal %>,
+    o_read_trigger    => open,
+    i_hw_write_enable => "0",
+    i_hw_write_data   => (others => '0'),
+    i_hw_set          => (others => '0'),
+    i_hw_clear        => (others => '0'),
+    i_value           => (others => '0'),
+    i_mask            => (others => '1'),
+    o_value           => <%= value_out[loop_variables] %>,
+    o_value_unmasked  => open
+  );

data/lib/rggen/vhdl/bit_field/type/wo_wo1_wotrg.rb

@@ -0,0 +1,32 @@
+# frozen_string_literal: true
+
+RgGen.define_list_item_feature(:bit_field, :type, [:wo, :wo1, :wotrg]) do
+  vhdl do
+    build do
+      output :value_out, {
+        name: "o_#{full_name}", width: width, array_size: array_size
+      }
+      if wotrg?
+        output :write_trigger, {
+          name: "o_#{full_name}_write_trigger", width: 1, array_size: array_size
+        }
+      end
+    end
+
+    main_code :bit_field, from_template: true
+
+    private
+
+    def wotrg?
+      bit_field.type == :wotrg
+    end
+
+    def write_once
+      bit_field.type == :wo1
+    end
+
+    def write_trigger_signal
+      wotrg? && write_trigger[loop_variables] || 'open'
+    end
+  end
+end

data/lib/rggen/vhdl/bit_field/type/wrc_wrs.erb

@@ -14,6 +14,8 @@ u_bit_field: entity work.rggen_bit_field
     i_sw_write_data   => <%= bit_field_write_data %>,
     o_sw_read_data    => <%= bit_field_read_data %>,
     o_sw_value        => <%= bit_field_value %>,
+    o_write_trigger   => open,
+    o_read_trigger    => open,
     i_hw_write_enable => "0",
     i_hw_write_data   => (others => '0'),
     i_hw_set          => (others => '0'),

data/lib/rggen/vhdl/feature.rb

@@ -14,7 +14,7 @@ module RgGen
       def create_port(direction, attributes, &block)
         attributes =
           attributes
-            .merge(direction: { input: :in, output: :out}[direction])
+            .merge(direction: { input: :in, output: :out }[direction])
         DataObject.new(:port, attributes, &block)
       end
 

data/lib/rggen/vhdl/register/tie_off_unused_signals.erb

@@ -0,0 +1,6 @@
+\g_tie_off\: for \__i\ in 0 to <%= width - 1 %> generate
+  g: if (bit_slice(<%= valid_bits %>, \__i\) = '0') generate
+    <%= bit_field_read_data %>(\__i\) <= '0';
+    <%= bit_field_value %>(\__i\) <= '0';
+  end generate;
+end generate;

data/lib/rggen/vhdl/register/type/default.erb

@@ -6,7 +6,6 @@ u_register: entity work.rggen_default_register
     OFFSET_ADDRESS  => <%= offset_address %>,
     BUS_WIDTH       => <%= bus_width %>,
     DATA_WIDTH      => <%= width %>,
-    VALID_BITS      => <%= valid_bits %>,
     REGISTER_INDEX  => <%= register_index %>
   )
   port map (

data/lib/rggen/vhdl/register/type/indirect.erb

@@ -9,7 +9,6 @@ u_register: entity work.rggen_indirect_register
     OFFSET_ADDRESS        => <%= offset_address %>,
     BUS_WIDTH             => <%= bus_width %>,
     DATA_WIDTH            => <%= width %>,
-    VALID_BITS            => <%= valid_bits %>,
     INDIRECT_MATCH_WIDTH  => <%= match_width %>
   )
   port map (

data/lib/rggen/vhdl/register/type/indirect.rb

@@ -3,7 +3,7 @@
 RgGen.define_list_item_feature(:register, :type, :indirect) do
   vhdl do
     build do
-      signal :indirect_match, {  width: match_width }
+      signal :indirect_match, { width: match_width }
     end
 
     main_code :register, from_template: true

data/lib/rggen/vhdl/register/type.rb

@@ -5,6 +5,11 @@ RgGen.define_list_feature(:register, :type) do
     base_feature do
       include RgGen::SystemVerilog::RTL::RegisterType
 
+      pre_code :register do |code|
+        register.bit_fields.empty? ||
+          (code << process_template(File.join(__dir__, 'tie_off_unused_signals.erb')))
+      end
+
       private
 
       def readable?

data/lib/rggen/vhdl/register_block/protocol/wishbone.erb

@@ -0,0 +1,36 @@
+u_adapter: entity work.rggen_wishbone_adapter
+  generic map (
+    ADDRESS_WIDTH       => <%= address_width %>,
+    LOCAL_ADDRESS_WIDTH => <%= local_address_width %>,
+    BUS_WIDTH           => <%= bus_width %>,
+    REGISTERS           => <%= total_registers %>,
+    PRE_DECODE          => <%= pre_decode %>,
+    BASE_ADDRESS        => <%= base_address %>,
+    BYTE_SIZE           => <%= byte_size %>,
+    ERROR_STATUS        => <%= error_status %>,
+    USE_STALL           => <%= use_stall %>
+  )
+  port map (
+    i_clk                 => <%= register_block.clock %>,
+    i_rst_n               => <%= register_block.reset %>,
+    i_wb_cyc              => <%= wb_cyc %>,
+    i_wb_stb              => <%= wb_stb %>,
+    o_wb_stall            => <%= wb_stall %>,
+    i_wb_adr              => <%= wb_adr %>,
+    i_wb_we               => <%= wb_we %>,
+    i_wb_dat              => <%= wb_dat_i %>,
+    i_wb_sel              => <%= wb_sel %>,
+    o_wb_ack              => <%= wb_ack %>,
+    o_wb_err              => <%= wb_err %>,
+    o_wb_rty              => <%= wb_rty %>,
+    o_wb_dat              => <%= wb_dat_o %>,
+    o_register_valid      => <%= register_block.register_valid %>,
+    o_register_access     => <%= register_block.register_access %>,
+    o_register_address    => <%= register_block.register_address %>,
+    o_register_write_data => <%= register_block.register_write_data %>,
+    o_register_strobe     => <%= register_block.register_strobe %>,
+    i_register_active     => <%= register_block.register_active %>,
+    i_register_ready      => <%= register_block.register_ready %>,
+    i_register_status     => <%= register_block.register_status %>,
+    i_register_read_data  => <%= register_block.register_read_data %>
+  );

data/lib/rggen/vhdl/register_block/protocol/wishbone.rb

@@ -0,0 +1,25 @@
+# frozen_string_literal: true
+
+RgGen.define_list_item_feature(:register_block, :protocol, :wishbone) do
+  vhdl do
+    build do
+      generic :use_stall, {
+        name: 'USE_STALL', type: :boolean, default: true
+      }
+
+      input :wb_cyc, { name: 'i_wb_cyc' }
+      input :wb_stb, { name: 'i_wb_stb' }
+      output :wb_stall, { name: 'o_wb_stall' }
+      input :wb_adr, { name: 'i_wb_adr', width: address_width }
+      input :wb_we, { name: 'i_wb_we' }
+      input :wb_dat_i, { name: 'i_wb_dat', width: bus_width }
+      input :wb_sel, { name: 'i_wb_sel', width: bus_width / 8 }
+      output :wb_ack, { name: 'o_wb_ack' }
+      output :wb_err, { name: 'o_wb_err' }
+      output :wb_rty, { name: 'o_wb_rty' }
+      output :wb_dat_o, { name: 'o_wb_dat', width: bus_width }
+    end
+
+    main_code :register_block, from_template: true
+  end
+end

data/lib/rggen/vhdl/utility.rb

@@ -12,12 +12,12 @@ module RgGen
       end
 
       def bin(value, width = nil)
-        width && format("\"%0*b\"", width, value) || "'#{value[0]}'"
+        width && format('"%0*b"', width, value) || "'#{value[0]}'"
       end
 
       def hex(value, width)
         print_width = (width + 3) / 4
-        format("x\"%0*x\"", print_width, value)
+        format('x"%0*x"', print_width, value)
       end
 
       def local_scope(scope_name, attributes = {}, &block)

data/lib/rggen/vhdl/version.rb

@@ -2,6 +2,6 @@
 
 module RgGen
   module VHDL
-    VERSION = '0.1.0'
+    VERSION = '0.3.0'
   end
 end

data/lib/rggen/vhdl.rb

@@ -10,41 +10,43 @@ require_relative 'vhdl/component'
 require_relative 'vhdl/feature'
 require_relative 'vhdl/factories'
 
-module RgGen
-  module VHDL
-    extend Core::Plugin
+RgGen.setup_plugin :'rggen-vhdl' do |plugin|
+  plugin.version RgGen::VHDL::VERSION
 
-    setup_plugin :'rggen-vhdl' do |plugin|
-      plugin.register_component :vhdl do
-        component Component, ComponentFactory
-        feature Feature, FeatureFactory
-      end
-
-      plugin.files [
-        'vhdl/bit_field/type',
-        'vhdl/bit_field/type/rc_w0c_w1c_wc_woc',
-        'vhdl/bit_field/type/ro',
-        'vhdl/bit_field/type/rof',
-        'vhdl/bit_field/type/rs_w0s_w1s_ws_wos',
-        'vhdl/bit_field/type/rw_w1_wo_wo1',
-        'vhdl/bit_field/type/rwc',
-        'vhdl/bit_field/type/rwe_rwl',
-        'vhdl/bit_field/type/rws',
-        'vhdl/bit_field/type/w0crs_w0src_w1crs_w1src_wcrs_wsrc',
-        'vhdl/bit_field/type/w0t_w1t',
-        'vhdl/bit_field/type/w0trg_w1trg',
-        'vhdl/bit_field/type/wrc_wrs',
-        'vhdl/bit_field/vhdl_top',
-        'vhdl/register/type',
-        'vhdl/register/type/external',
-        'vhdl/register/type/indirect',
-        'vhdl/register/vhdl_top',
-        'vhdl/register_block/protocol',
-        'vhdl/register_block/protocol/apb',
-        'vhdl/register_block/protocol/axi4lite',
-        'vhdl/register_block/vhdl_top',
-        'vhdl/register_file/vhdl_top'
-      ]
-    end
+  plugin.register_component :vhdl do
+    component RgGen::VHDL::Component,
+              RgGen::VHDL::ComponentFactory
+    feature RgGen::VHDL::Feature,
+            RgGen::VHDL::FeatureFactory
   end
+
+  plugin.files [
+    'vhdl/register_block/vhdl_top',
+    'vhdl/register_block/protocol',
+    'vhdl/register_block/protocol/apb',
+    'vhdl/register_block/protocol/axi4lite',
+    'vhdl/register_block/protocol/wishbone',
+    'vhdl/register_file/vhdl_top',
+    'vhdl/register/vhdl_top',
+    'vhdl/register/type',
+    'vhdl/register/type/external',
+    'vhdl/register/type/indirect',
+    'vhdl/bit_field/vhdl_top',
+    'vhdl/bit_field/type',
+    'vhdl/bit_field/type/rc_w0c_w1c_wc_woc',
+    'vhdl/bit_field/type/ro_rotrg',
+    'vhdl/bit_field/type/rof',
+    'vhdl/bit_field/type/row0trg_row1trg',
+    'vhdl/bit_field/type/rowo_rowotrg',
+    'vhdl/bit_field/type/rs_w0s_w1s_ws_wos',
+    'vhdl/bit_field/type/rw_rwtrg_w1',
+    'vhdl/bit_field/type/rwc',
+    'vhdl/bit_field/type/rwe_rwl',
+    'vhdl/bit_field/type/rws',
+    'vhdl/bit_field/type/w0crs_w0src_w1crs_w1src_wcrs_wsrc',
+    'vhdl/bit_field/type/w0t_w1t',
+    'vhdl/bit_field/type/w0trg_w1trg',
+    'vhdl/bit_field/type/wo_wo1_wotrg',
+    'vhdl/bit_field/type/wrc_wrs'
+  ]
 end

metadata

@@ -1,14 +1,14 @@
 --- !ruby/object:Gem::Specification
 name: rggen-vhdl
 version: !ruby/object:Gem::Version
-  version: 0.1.0
+  version: 0.3.0
 platform: ruby
 authors:
 - Taichi Ishitani
 autorequire: 
 bindir: bin
 cert_chain: []
-date: 2021-05-16 00:00:00.000000000 Z
+date: 2022-07-05 00:00:00.000000000 Z
 dependencies:
 - !ruby/object:Gem::Dependency
   name: rggen-systemverilog
@@ -16,14 +16,14 @@ dependencies:
     requirements:
     - - ">="
       - !ruby/object:Gem::Version
-        version: 0.25.1
+        version: 0.27.0
   type: :runtime
   prerelease: false
   version_requirements: !ruby/object:Gem::Requirement
     requirements:
     - - ">="
       - !ruby/object:Gem::Version
-        version: 0.25.1
+        version: 0.27.0
 - !ruby/object:Gem::Dependency
   name: bundler
   requirement: !ruby/object:Gem::Requirement
@@ -52,14 +52,18 @@ files:
 - lib/rggen/vhdl/bit_field/type.rb
 - lib/rggen/vhdl/bit_field/type/rc_w0c_w1c_wc_woc.erb
 - lib/rggen/vhdl/bit_field/type/rc_w0c_w1c_wc_woc.rb
-- lib/rggen/vhdl/bit_field/type/ro.erb
-- lib/rggen/vhdl/bit_field/type/ro.rb
+- lib/rggen/vhdl/bit_field/type/ro_rotrg.erb
+- lib/rggen/vhdl/bit_field/type/ro_rotrg.rb
 - lib/rggen/vhdl/bit_field/type/rof.erb
 - lib/rggen/vhdl/bit_field/type/rof.rb
+- lib/rggen/vhdl/bit_field/type/row0trg_row1trg.erb
+- lib/rggen/vhdl/bit_field/type/row0trg_row1trg.rb
+- lib/rggen/vhdl/bit_field/type/rowo_rowotrg.erb
+- lib/rggen/vhdl/bit_field/type/rowo_rowotrg.rb
 - lib/rggen/vhdl/bit_field/type/rs_w0s_w1s_ws_wos.erb
 - lib/rggen/vhdl/bit_field/type/rs_w0s_w1s_ws_wos.rb
-- lib/rggen/vhdl/bit_field/type/rw_w1_wo_wo1.erb
-- lib/rggen/vhdl/bit_field/type/rw_w1_wo_wo1.rb
+- lib/rggen/vhdl/bit_field/type/rw_rwtrg_w1.erb
+- lib/rggen/vhdl/bit_field/type/rw_rwtrg_w1.rb
 - lib/rggen/vhdl/bit_field/type/rwc.erb
 - lib/rggen/vhdl/bit_field/type/rwc.rb
 - lib/rggen/vhdl/bit_field/type/rwe_rwl.erb
@@ -72,13 +76,15 @@ files:
 - lib/rggen/vhdl/bit_field/type/w0t_w1t.rb
 - lib/rggen/vhdl/bit_field/type/w0trg_w1trg.erb
 - lib/rggen/vhdl/bit_field/type/w0trg_w1trg.rb
+- lib/rggen/vhdl/bit_field/type/wo_wo1_wotrg.erb
+- lib/rggen/vhdl/bit_field/type/wo_wo1_wotrg.rb
 - lib/rggen/vhdl/bit_field/type/wrc_wrs.erb
 - lib/rggen/vhdl/bit_field/type/wrc_wrs.rb
 - lib/rggen/vhdl/bit_field/vhdl_top.rb
 - lib/rggen/vhdl/component.rb
 - lib/rggen/vhdl/factories.rb
 - lib/rggen/vhdl/feature.rb
-- lib/rggen/vhdl/register/default.erb
+- lib/rggen/vhdl/register/tie_off_unused_signals.erb
 - lib/rggen/vhdl/register/type.rb
 - lib/rggen/vhdl/register/type/default.erb
 - lib/rggen/vhdl/register/type/external.erb
@@ -91,10 +97,11 @@ files:
 - lib/rggen/vhdl/register_block/protocol/apb.rb
 - lib/rggen/vhdl/register_block/protocol/axi4lite.erb
 - lib/rggen/vhdl/register_block/protocol/axi4lite.rb
+- lib/rggen/vhdl/register_block/protocol/wishbone.erb
+- lib/rggen/vhdl/register_block/protocol/wishbone.rb
 - lib/rggen/vhdl/register_block/vhdl_top.erb
 - lib/rggen/vhdl/register_block/vhdl_top.rb
 - lib/rggen/vhdl/register_file/vhdl_top.rb
-- lib/rggen/vhdl/setup.rb
 - lib/rggen/vhdl/utility.rb
 - lib/rggen/vhdl/utility/data_object.rb
 - lib/rggen/vhdl/utility/identifier.rb
@@ -104,8 +111,9 @@ homepage: https://github.com/rggen/rggen-vhdl
 licenses:
 - MIT
 metadata:
-  bug_tracker_uri: https://github.com/rggen/rggen-vhdl/issues
+  bug_tracker_uri: https://github.com/rggen/rggen/issues
   mailing_list_uri: https://groups.google.com/d/forum/rggen
+  rubygems_mfa_required: 'true'
   source_code_uri: https://github.com/rggen/rggen-vhdl
   wiki_uri: https://github.com/rggen/rggen/wiki
 post_install_message: 
@@ -116,15 +124,15 @@ required_ruby_version: !ruby/object:Gem::Requirement
   requirements:
   - - ">="
     - !ruby/object:Gem::Version
-      version: 2.5.0
+      version: 2.6.0
 required_rubygems_version: !ruby/object:Gem::Requirement
   requirements:
   - - ">="
     - !ruby/object:Gem::Version
       version: '0'
 requirements: []
-rubygems_version: 3.2.3
+rubygems_version: 3.3.3
 signing_key: 
 specification_version: 4
-summary: rggen-vhdl-0.1.0
+summary: rggen-vhdl-0.3.0
 test_files: []

data/lib/rggen/vhdl/bit_field/type/rw_w1_wo_wo1.rb

@@ -1,23 +0,0 @@
-# frozen_string_literal: true
-
-RgGen.define_list_item_feature(:bit_field, :type, [:rw, :w1, :wo, :wo1]) do
-  vhdl do
-    build do
-      output :value_out, {
-        name: "o_#{full_name}", width: width, array_size: array_size
-      }
-    end
-
-    main_code :bit_field, from_template: true
-
-    private
-
-    def read_action
-      bit_field.readable? && 'RGGEN_READ_DEFAULT' || 'RGGEN_READ_NONE'
-    end
-
-    def write_once
-      [:w1, :wo1].include?(bit_field.type)
-    end
-  end
-end

data/lib/rggen/vhdl/register/default.erb

@@ -1,29 +0,0 @@
-rggen_default_register #(
-  .READABLE       (<%= readable %>),
-  .WRITABLE       (<%= writable %>),
-  .ADDRESS_WIDTH  (<%= address_width %>),
-  .OFFSET_ADDRESS (<%= offset_address %>),
-  .BUS_WIDTH      (<%= bus_width %>),
-  .DATA_WIDTH     (<%= width %>),
-  .VALID_BITS     (<%= valid_bits %>),
-  .REGISTER_INDEX (<%= register_index %>)
-) u_register (
-  .i_clk                  (<%= clock %>),
-  .i_rst_n                (<%= reset %>),
-  .i_register_valid       (<%= register_valid %>),
-  .i_register_access      (<%= register_access %>),
-  .i_register_address     (<%= register_address %>),
-  .i_register_write_data  (<%= register_write_data %>),
-  .i_register_strobe      (<%= register_strobe %>),
-  .o_register_active      (<%= register_active %>),
-  .o_register_ready       (<%= register_ready %>),
-  .o_register_status      (<%= register_status %>),
-  .o_register_read_data   (<%= register_read_data %>),
-  .o_register_value       (<%= register_value %>),
-  .o_bit_field_valid      (<%= bit_field_valid %>),
-  .o_bit_field_read_mask  (<%= bit_field_read_mask %>),
-  .o_bit_field_write_mask (<%= bit_field_write_mask %>),
-  .o_bit_field_write_data (<%= bit_field_write_data %>),
-  .i_bit_field_read_data  (<%= bit_field_read_data %>),
-  .i_bit_field_value      (<%= bit_field_value %>)
-);

data/lib/rggen/vhdl/setup.rb

@@ -1,11 +0,0 @@
-# frozen_string_literal: true
-
-require 'rggen/vhdl'
-
-RgGen.register_plugin RgGen::VHDL do |builder|
-  builder.load_plugin 'rggen/systemverilog/rtl/setup'
-  builder.enable :register_block, [:vhdl_top]
-  builder.enable :register_file, [:vhdl_top]
-  builder.enable :register, [:vhdl_top]
-  builder.enable :bit_field, [:vhdl_top]
-end