rggen-veryl 0.6.0 → 0.7.0

checksums.yaml

@@ -1,7 +1,7 @@
 ---
 SHA256:
-  metadata.gz: a3d8d6de784f9f1a04c15f727a91ffadd9eba064194b95e846c0fea063d2631c
-  data.tar.gz: 94504804cfae6bf5e3554c0d6954beed04e14079eac9af4dd3e2eff775cb9b49
+  metadata.gz: a47c80d1142919e860bc28b472ddc02cdd89a7e754a9b78c7f22fe93e3dc61f5
+  data.tar.gz: f5427babe12355d28fc496a026643205dfee522825895a18271a172740f47c78
 SHA512:
-  metadata.gz: 55ad1782e4c0e6f9689664635921e00c4e2e5f9cc7792ff1390ad5126762b7cf04cac4a11d25294a6638cf1d4c675e18cace2138e974e6cb5fc583bab0ce667b
-  data.tar.gz: 2bd8a3f510901a0caa289e9d654d2be77811f3dd3ee1af12f55ad13a4bd73a785f8bfc3730e06643b732f6bfc5742288462ac25234646da17dd748caf80a132c
+  metadata.gz: 288086355ea542c937f0d9da430535ec5e2f66fda168fc2f760c38eb9961abc77dad05f8ad4e4342932e1c490233a574e776630f43d29db0b8fa3a6f3c0c48fc
+  data.tar.gz: e6362d1bcc9ea49dd52092b26e5c955b1c12a5273b88f727bff469419e7e812be5b0cba3c1d2ba3cb99b9736f3e5c9647e2b36a7a87a7261753255a563da0172

data/README.md

@@ -43,7 +43,7 @@ You need to add this repository to the `[dependencies]` section in your `Veryl.t
 
 ```toml
 [dependencies]
-"rggen" = { github = "rggen/rggen-veryl-rtl", version = "0.6.0" }
+"rggen" = { github = "rggen/rggen-veryl-rtl", version = "0.7.0" }
 ```
 
 ## Contact

data/lib/rggen/veryl/bit_field/type/counter.rb

@@ -10,11 +10,11 @@ RgGen.define_list_item_feature(:bit_field, :type, :counter) do
         name: "#{full_name}_down_width".upcase, type: :u32, default: 1
       }
       param :wrap_around, {
-        name: "#{full_name}_wrap_around".upcase, type: :bool, default: false
+        name: "#{full_name}_wrap_around".upcase, type: :bbool, default: false
       }
       if external_clear?
         param :use_clear, {
-          name: "#{full_name}_use_clear".upcase, type: :bool, default: true
+          name: "#{full_name}_use_clear".upcase, type: :bbool, default: true
         }
       end
 

data/lib/rggen/veryl/register_block/protocol/axi4lite.rb

@@ -7,7 +7,7 @@ RgGen.define_list_item_feature(:register_block, :protocol, :axi4lite) do
         name: 'ID_WIDTH', type: :u32, default: 0
       }
       param :write_first, {
-        name: 'WRITE_FIRST', type: :bool, default: true
+        name: 'WRITE_FIRST', type: :bbool, default: true
       }
       modport :axi4lite_if, {
         name: 'axi4lite_if',

data/lib/rggen/veryl/register_block/protocol/native.rb

@@ -7,7 +7,7 @@ RgGen.define_list_item_feature(:register_block, :protocol, :native) do
         name: 'STROBE_WIDTH', type: :u32, default: bus_width / 8
       }
       param :use_read_strobe, {
-        name: 'USE_READ_STROBE', type: :bool, default: false
+        name: 'USE_READ_STROBE', type: :bbool, default: false
       }
       modport :csrbus_if, {
         name: 'csrbus_if',

data/lib/rggen/veryl/register_block/protocol.rb

@@ -10,19 +10,19 @@ RgGen.define_list_feature(:register_block, :protocol) do
           name: 'ADDRESS_WIDTH', type: :u32, default: local_address_width
         }
         param :pre_decode, {
-          name: 'PRE_DECODE', type: :bool, default: false
+          name: 'PRE_DECODE', type: :bbool, default: false
         }
         param :base_address, {
           name: 'BASE_ADDRESS', type: :bit, width: address_width, default: all_bits_0
         }
         param :error_status, {
-          name: 'ERROR_STATUS', type: :bool, default: false
+          name: 'ERROR_STATUS', type: :bbool, default: false
         }
         param :default_read_data, {
           name: 'DEFAULT_READ_DATA', type: :bit, width: bus_width, default: all_bits_0
         }
         param :insert_slicer, {
-          name: 'INSERT_SLICER', type: :bool, default: false
+          name: 'INSERT_SLICER', type: :bbool, default: false
         }
       end
 

data/lib/rggen/veryl/register_block/veryl_top.rb

@@ -49,7 +49,7 @@ RgGen.define_simple_feature(:register_block, :veryl_top) do
     end
 
     def attributes
-      { fmt: :skip }
+      { fmt: :skip, allow: :unassign_variable }
     end
 
     def packages

data/lib/rggen/veryl/register_map/keyword_checker.rb

@@ -5,16 +5,14 @@ module RgGen
     module RegisterMap
       module KeywordChecker
         VERYL_KEYWORDS = [
-          'alias', 'always_comb', 'always_ff', 'assign', 'as', 'bit', 'bool', 'case',
-          'clock', 'clock_posedge', 'clock_negedge', 'connect', 'const', 'converse',
-          'default', 'else', 'embed', 'enum', 'f32', 'f64', 'false', 'final', 'for',
-          'function', 'i32', 'i64', 'if_reset', 'if', 'import', 'include', 'initial',
-          'inout', 'input', 'inside', 'inst', 'interface', 'in', 'let', 'logic', 'lsb',
-          'modport', 'module', 'msb', 'output', 'outside', 'package', 'param', 'proto',
-          'pub', 'repeat', 'reset', 'reset_async_high', 'reset_async_low',
-          'reset_sync_high', 'reset_sync_low', 'return', 'break', 'same', 'signed',
-          'step', 'string', 'struct', 'switch', 'tri', 'true', 'type', 'u32', 'u64',
-          'union', 'unsafe', 'var'
+          'alias', 'always_comb', 'always_ff', 'assign', 'as', 'bind', 'bit', 'block', 'bbool', 'lbool', 'case',
+          'clock', 'clock_posedge', 'clock_negedge', 'connect', 'const', 'converse', 'default', 'else', 'embed',
+          'enum', 'f32', 'f64', 'false', 'final', 'for', 'function', 'i8', 'i16', 'i32', 'i64', 'if_reset', 'if',
+          'import', 'include', 'initial', 'inout', 'input', 'inside', 'inst', 'interface', 'in', 'let', 'logic',
+          'lsb', 'modport', 'module', 'msb', 'output', 'outside', 'package', 'param', 'proto', 'pub', 'repeat',
+          'reset', 'reset_async_high', 'reset_async_low', 'reset_sync_high', 'reset_sync_low', 'return', 'rev',
+          'break', 'same', 'signed', 'step', 'string', 'struct', 'switch', 'tri', 'true', 'type', 'u8', 'u16', 'u32',
+          'u64', 'union', 'unsafe', 'var'
         ].freeze
 
         def self.included(klass)

data/lib/rggen/veryl/version.rb

@@ -2,6 +2,6 @@
 
 module RgGen
   module Veryl
-    VERSION = '0.6.0'
+    VERSION = '0.7.0'
   end
 end

metadata

@@ -1,7 +1,7 @@
 --- !ruby/object:Gem::Specification
 name: rggen-veryl
 version: !ruby/object:Gem::Version
-  version: 0.6.0
+  version: 0.7.0
 platform: ruby
 authors:
 - Taichi Ishitani
@@ -136,5 +136,5 @@ required_rubygems_version: !ruby/object:Gem::Requirement
 requirements: []
 rubygems_version: 4.0.3
 specification_version: 4
-summary: rggen-veryl-0.6.0
+summary: rggen-veryl-0.7.0
 test_files: []