rggen-veryl 0.5.2 → 0.7.0

checksums.yaml

@@ -1,7 +1,7 @@
 ---
 SHA256:
-  metadata.gz: cad5389b85d457e5d6adc888974bcd91347238caa68270a306680785ebb133c0
-  data.tar.gz: da0507974523b3d60a6abc8505d7c033896d7cff0fc3d81cc0cd7505e514ec19
+  metadata.gz: a47c80d1142919e860bc28b472ddc02cdd89a7e754a9b78c7f22fe93e3dc61f5
+  data.tar.gz: f5427babe12355d28fc496a026643205dfee522825895a18271a172740f47c78
 SHA512:
-  metadata.gz: f179f2b8eaaa0cdea034b0694f8319e2e7ace6d60a737c183fd6fe77da7ad62d84dda21ce942156f22cd3f7c294e1ed684dd14f6a849fc65ec88ccd7e9618ea6
-  data.tar.gz: bc8ba074f1f2e472426a9f84f70f4d60a6ebe014e119fb6304b8315641d260bc8f18fac9f3345e2aeb5f55d2bd685ffd033875a881c5ad0142e13f25db37448a
+  metadata.gz: 288086355ea542c937f0d9da430535ec5e2f66fda168fc2f760c38eb9961abc77dad05f8ad4e4342932e1c490233a574e776630f43d29db0b8fa3a6f3c0c48fc
+  data.tar.gz: e6362d1bcc9ea49dd52092b26e5c955b1c12a5273b88f727bff469419e7e812be5b0cba3c1d2ba3cb99b9736f3e5c9647e2b36a7a87a7261753255a563da0172

data/LICENSE

@@ -1,6 +1,6 @@
 The MIT License (MIT)
 
-Copyright (c) 2024-2025 Taichi Ishitani
+Copyright (c) 2024-2026 Taichi Ishitani
 
 Permission is hereby granted, free of charge, to any person obtaining a copy
 of this software and associated documentation files (the "Software"), to deal

data/README.md

@@ -2,7 +2,7 @@
 [![CI](https://github.com/rggen/rggen-veryl/actions/workflows/ci.yml/badge.svg)](https://github.com/rggen/rggen-veryl/actions/workflows/ci.yml)
 [![Maintainability](https://qlty.sh/badges/7537364e-4631-4c9a-b873-5bceb9418ed0/maintainability.svg)](https://qlty.sh/gh/rggen/projects/rggen-veryl)
 [![codecov](https://codecov.io/gh/rggen/rggen-veryl/graph/badge.svg?token=iYlaqhSjat)](https://codecov.io/gh/rggen/rggen-veryl)
-[![Gitter](https://badges.gitter.im/rggen/rggen.svg)](https://gitter.im/rggen/rggen?utm_source=badge&utm_medium=badge&utm_campaign=pr-badge)
+[![Discord](https://img.shields.io/discord/1406572699467124806?style=flat&logo=discord)](https://discord.com/invite/KWya83ZZxr)
 
 # RgGen::Veryl
 
@@ -43,7 +43,7 @@ You need to add this repository to the `[dependencies]` section in your `Veryl.t
 
 ```toml
 [dependencies]
-"rggen" = { github = "rggen/rggen-veryl-rtl", version = "0.5.0" }
+"rggen" = { github = "rggen/rggen-veryl-rtl", version = "0.7.0" }
 ```
 
 ## Contact
@@ -52,13 +52,13 @@ Feedbacks, bus reports, questions and etc. are welcome! You can post them by usi
 
 * [GitHub Issue Tracker](https://github.com/rggen/rggen/issues)
 * [GitHub Discussions](https://github.com/rggen/rggen/discussions)
-* [Chat Room](https://gitter.im/rggen/rggen)
+* [Discord](https://discord.com/invite/KWya83ZZxr)
 * [Mailing List](https://groups.google.com/d/forum/rggen)
 * [Mail](mailto:rggen@googlegroups.com)
 
 ## Copyright & License
 
-Copyright © 2024-2025 Taichi Ishitani. RgGen::Veryl is licensed under the [MIT License](https://opensource.org/licenses/MIT), see [LICENSE](LICENSE) for futher details.
+Copyright © 2024-2026 Taichi Ishitani. RgGen::Veryl is licensed under the [MIT License](https://opensource.org/licenses/MIT), see [LICENSE](LICENSE) for futher details.
 
 ## Code of Conduct
 

data/lib/rggen/veryl/bit_field/type/counter.erb

@@ -0,0 +1,16 @@
+inst u_bit_field: rggen::rggen_bit_field_counter #(
+  WIDTH        : <%= width %>,
+  INITIAL_VALUE: <%= initial_value %>,
+  UP_WIDTH     : <%= up_width %>,
+  DOWN_WIDTH   : <%= down_width %>,
+  WRAP_AROUND  : <%= wrap_around %>,
+  USE_CLEAR    : <%= use_clear_value %>,
+)(
+  i_clk       : <%= clock %>,
+  i_rst       : <%= reset %>,
+  bit_field_if: <%= bit_field_if %>,
+  i_clear     : <%= clear_signal %>,
+  i_up        : <%= up[loop_variables] %>,
+  i_down      : <%= down[loop_variables] %>,
+  o_count     : <%= count[loop_variables] %>,
+);

data/lib/rggen/veryl/bit_field/type/counter.rb

@@ -0,0 +1,55 @@
+# frozen_string_literal: true
+
+RgGen.define_list_item_feature(:bit_field, :type, :counter) do
+  veryl do
+    build do
+      param :up_width, {
+        name: "#{full_name}_up_width".upcase, type: :u32, default: 1
+      }
+      param :down_width, {
+        name: "#{full_name}_down_width".upcase, type: :u32, default: 1
+      }
+      param :wrap_around, {
+        name: "#{full_name}_wrap_around".upcase, type: :bbool, default: false
+      }
+      if external_clear?
+        param :use_clear, {
+          name: "#{full_name}_use_clear".upcase, type: :bbool, default: true
+        }
+      end
+
+      input :up, {
+        name: "i_#{full_name}_up",
+        width: function_call(:clip_width, [up_width]), array_size:
+      }
+      input :down, {
+        name: "i_#{full_name}_down",
+        width: function_call(:clip_width, [down_width]), array_size:
+      }
+      if external_clear?
+        input :clear, {
+          name: "i_#{full_name}_clear", width: 1, array_size:
+        }
+      end
+      output :count, {
+        name: "o_#{full_name}", width:, array_size:
+      }
+    end
+
+    main_code :bit_field, from_template: true
+
+    private
+
+    def external_clear?
+      !bit_field.reference?
+    end
+
+    def use_clear_value
+      !external_clear? || use_clear
+    end
+
+    def clear_signal
+      reference_bit_field || clear[loop_variables]
+    end
+  end
+end

data/lib/rggen/veryl/register/type/maskable.erb

@@ -0,0 +1,15 @@
+inst u_register: rggen::rggen_maskable_register #(
+  READABLE:       <%= readable? %>,
+  WRITABLE:       <%= writable? %>,
+  ADDRESS_WIDTH:  <%= address_width %>,
+  OFFSET_ADDRESS: <%= offset_address %>,
+  BUS_WIDTH:      <%= bus_width %>,
+  DATA_WIDTH:     <%= width %>,
+  VALUE_WIDTH:    <%= value_width %>,
+  VALID_BITS:     <%= valid_bits %>
+)(
+  i_clk:        <%= register_block.clock %>,
+  i_rst:        <%= register_block.reset %>,
+  register_if:  <%= register_if %>,
+  bit_field_if: <%= bit_field_if %>
+);

data/lib/rggen/veryl/register/type/maskable.rb

@@ -0,0 +1,7 @@
+# frozen_string_literal: true
+
+RgGen.define_list_item_feature(:register, :type, :maskable) do
+  veryl do
+    main_code :register, from_template: true
+  end
+end

data/lib/rggen/veryl/register_block/protocol/axi4lite.rb

@@ -7,7 +7,7 @@ RgGen.define_list_item_feature(:register_block, :protocol, :axi4lite) do
         name: 'ID_WIDTH', type: :u32, default: 0
       }
       param :write_first, {
-        name: 'WRITE_FIRST', type: :bool, default: true
+        name: 'WRITE_FIRST', type: :bbool, default: true
       }
       modport :axi4lite_if, {
         name: 'axi4lite_if',

data/lib/rggen/veryl/register_block/protocol/native.rb

@@ -7,7 +7,7 @@ RgGen.define_list_item_feature(:register_block, :protocol, :native) do
         name: 'STROBE_WIDTH', type: :u32, default: bus_width / 8
       }
       param :use_read_strobe, {
-        name: 'USE_READ_STROBE', type: :bool, default: false
+        name: 'USE_READ_STROBE', type: :bbool, default: false
       }
       modport :csrbus_if, {
         name: 'csrbus_if',

data/lib/rggen/veryl/register_block/protocol.rb

@@ -10,19 +10,19 @@ RgGen.define_list_feature(:register_block, :protocol) do
           name: 'ADDRESS_WIDTH', type: :u32, default: local_address_width
         }
         param :pre_decode, {
-          name: 'PRE_DECODE', type: :bool, default: false
+          name: 'PRE_DECODE', type: :bbool, default: false
         }
         param :base_address, {
           name: 'BASE_ADDRESS', type: :bit, width: address_width, default: all_bits_0
         }
         param :error_status, {
-          name: 'ERROR_STATUS', type: :bool, default: false
+          name: 'ERROR_STATUS', type: :bbool, default: false
         }
         param :default_read_data, {
           name: 'DEFAULT_READ_DATA', type: :bit, width: bus_width, default: all_bits_0
         }
         param :insert_slicer, {
-          name: 'INSERT_SLICER', type: :bool, default: false
+          name: 'INSERT_SLICER', type: :bbool, default: false
         }
       end
 

data/lib/rggen/veryl/register_block/veryl_top.rb

@@ -25,6 +25,7 @@ RgGen.define_simple_feature(:register_block, :veryl_top) do
         code << module_definition(register_block.name) do |m|
           m.attributes attributes
           m.package_imports packages
+          m.generics generics
           m.params params
           m.ports ports
           m.variables variables
@@ -48,13 +49,17 @@ RgGen.define_simple_feature(:register_block, :veryl_top) do
     end
 
     def attributes
-      { fmt: :skip }
+      { fmt: :skip, allow: :unassign_variable }
     end
 
     def packages
       ['rggen::rggen_rtl_pkg', *register_block.package_imports(:register_block)]
     end
 
+    def generics
+      register_block.declarations[:generic]
+    end
+
     def params
       register_block.declarations[:parameter]
     end

data/lib/rggen/veryl/register_map/keyword_checker.rb

@@ -5,16 +5,14 @@ module RgGen
     module RegisterMap
       module KeywordChecker
         VERYL_KEYWORDS = [
-          'alias', 'always_comb', 'always_ff', 'assign', 'as', 'bit', 'bool', 'case',
-          'clock', 'clock_posedge', 'clock_negedge', 'connect', 'const', 'converse',
-          'default', 'else', 'embed', 'enum', 'f32', 'f64', 'false', 'final', 'for',
-          'function', 'i32', 'i64', 'if_reset', 'if', 'import', 'include', 'initial',
-          'inout', 'input', 'inside', 'inst', 'interface', 'in', 'let', 'logic', 'lsb',
-          'modport', 'module', 'msb', 'output', 'outside', 'package', 'param', 'proto',
-          'pub', 'repeat', 'reset', 'reset_async_high', 'reset_async_low',
-          'reset_sync_high', 'reset_sync_low', 'return', 'break', 'same', 'signed',
-          'step', 'string', 'struct', 'switch', 'tri', 'true', 'type', 'u32', 'u64',
-          'union', 'unsafe', 'var'
+          'alias', 'always_comb', 'always_ff', 'assign', 'as', 'bind', 'bit', 'block', 'bbool', 'lbool', 'case',
+          'clock', 'clock_posedge', 'clock_negedge', 'connect', 'const', 'converse', 'default', 'else', 'embed',
+          'enum', 'f32', 'f64', 'false', 'final', 'for', 'function', 'i8', 'i16', 'i32', 'i64', 'if_reset', 'if',
+          'import', 'include', 'initial', 'inout', 'input', 'inside', 'inst', 'interface', 'in', 'let', 'logic',
+          'lsb', 'modport', 'module', 'msb', 'output', 'outside', 'package', 'param', 'proto', 'pub', 'repeat',
+          'reset', 'reset_async_high', 'reset_async_low', 'reset_sync_high', 'reset_sync_low', 'return', 'rev',
+          'break', 'same', 'signed', 'step', 'string', 'struct', 'switch', 'tri', 'true', 'type', 'u8', 'u16', 'u32',
+          'u64', 'union', 'unsafe', 'var'
         ].freeze
 
         def self.included(klass)

data/lib/rggen/veryl/utility/modport.rb

@@ -4,6 +4,8 @@ module RgGen
   module Veryl
     module Utility
       class Modport < SystemVerilog::Common::Utility::InterfacePort
+        define_attribute :generics
+
         def declaration
           [
             "#{name}:",
@@ -15,7 +17,13 @@ module RgGen
         private
 
         def port_type
-          "#{@interface_type}::#{@modport_name}#{array_size_notation}"
+          "#{@interface_type}#{generics_notation}::#{@modport_name}#{array_size_notation}"
+        end
+
+        def generics_notation
+          return unless @generics
+
+          "::<#{@generics.join(', ')}>"
         end
 
         def array_size_notation

data/lib/rggen/veryl/version.rb

@@ -2,6 +2,6 @@
 
 module RgGen
   module Veryl
-    VERSION = '0.5.2'
+    VERSION = '0.7.0'
   end
 end

data/lib/rggen/veryl.rb

@@ -36,9 +36,11 @@ RgGen.setup_plugin :'rggen-veryl' do |plugin|
     'veryl/register/type',
     'veryl/register/type/external',
     'veryl/register/type/indirect',
+    'veryl/register/type/maskable',
     'veryl/register/type/rw',
     'veryl/bit_field/veryl_top',
     'veryl/bit_field/type',
+    'veryl/bit_field/type/counter',
     'veryl/bit_field/type/custom',
     'veryl/bit_field/type/rc_w0c_w1c_wc_woc',
     'veryl/bit_field/type/ro_rotrg',

metadata

@@ -1,13 +1,13 @@
 --- !ruby/object:Gem::Specification
 name: rggen-veryl
 version: !ruby/object:Gem::Version
-  version: 0.5.2
+  version: 0.7.0
 platform: ruby
 authors:
 - Taichi Ishitani
 bindir: bin
 cert_chain: []
-date: 2025-08-04 00:00:00.000000000 Z
+date: 1980-01-02 00:00:00.000000000 Z
 dependencies:
 - !ruby/object:Gem::Dependency
   name: rggen-systemverilog
@@ -15,14 +15,14 @@ dependencies:
     requirements:
     - - ">="
       - !ruby/object:Gem::Version
-        version: 0.35.1
+        version: 0.36.0
   type: :runtime
   prerelease: false
   version_requirements: !ruby/object:Gem::Requirement
     requirements:
     - - ">="
       - !ruby/object:Gem::Version
-        version: 0.35.1
+        version: 0.36.0
 description: Veryl writer plugin for RgGen
 email:
 - rggen@googlegroups.com
@@ -36,6 +36,8 @@ files:
 - lib/rggen/veryl.rb
 - lib/rggen/veryl/bit_field/common.erb
 - lib/rggen/veryl/bit_field/type.rb
+- lib/rggen/veryl/bit_field/type/counter.erb
+- lib/rggen/veryl/bit_field/type/counter.rb
 - lib/rggen/veryl/bit_field/type/custom.erb
 - lib/rggen/veryl/bit_field/type/custom.rb
 - lib/rggen/veryl/bit_field/type/rc_w0c_w1c_wc_woc.erb
@@ -82,6 +84,8 @@ files:
 - lib/rggen/veryl/register/type/external.rb
 - lib/rggen/veryl/register/type/indirect.erb
 - lib/rggen/veryl/register/type/indirect.rb
+- lib/rggen/veryl/register/type/maskable.erb
+- lib/rggen/veryl/register/type/maskable.rb
 - lib/rggen/veryl/register/type/rw.erb
 - lib/rggen/veryl/register/type/rw.rb
 - lib/rggen/veryl/register/veryl_top.rb
@@ -123,14 +127,14 @@ required_ruby_version: !ruby/object:Gem::Requirement
   requirements:
   - - ">="
     - !ruby/object:Gem::Version
-      version: '3.1'
+      version: '3.2'
 required_rubygems_version: !ruby/object:Gem::Requirement
   requirements:
   - - ">="
     - !ruby/object:Gem::Version
       version: '0'
 requirements: []
-rubygems_version: 3.6.2
+rubygems_version: 4.0.3
 specification_version: 4
-summary: rggen-veryl-0.5.2
+summary: rggen-veryl-0.7.0
 test_files: []