rggen-veryl 0.4.0 → 0.5.0

checksums.yaml

@@ -1,7 +1,7 @@
 ---
 SHA256:
-  metadata.gz: d92c6db46e4bebb4c853f1a4a4599eed524a1d77a8cc6f7b62b65f282e032497
-  data.tar.gz: ae35fde024ba27dd80292c61504c39b4535bbea71d406f2bd357df1f4d6a9f51
+  metadata.gz: d404dd20a659011ef8d0ede7dfd7d1d8fac4ccd18114c2d9ace21c97c0890c39
+  data.tar.gz: 3b6b51827c4017ecdb6ec32a68b09160025ecb81fae4411b5536995a6eef11fa
 SHA512:
-  metadata.gz: d5b4c108e8df2ee9773b98c27afd706f6b52a34b519179fbd37e83736bb631915e2145cbb137dd920680fdbb8fa3b866cb5cc3dcaff5215488ab9c6aa869520b
-  data.tar.gz: 2749d7b449e9c7488786c9fda5a45724dd2eedb20255435466934deeb7f3ef0e097020b941f34a7c481736fb4a53a0c12e52e601e006f34c4b220804d003d308
+  metadata.gz: a816d72069a6c69383c3e51a376a4cd0aef352e9fef05b18ad4eac330b30a4408dc8dc910163ef81ea7b44abad38f66260bc3579e70ed1f41d997b6bd79ac315
+  data.tar.gz: 91ac11312a550f5ad7fa094284207f002f8656c5521ec7a92b26ceea858ad32b04003428117f0e4cd39b3d73c956c51b7535e716c0bda9dea09bdb1a15909845

data/README.md

@@ -43,7 +43,7 @@ You need to add this repository to the `[dependencies]` section in your `Veryl.t
 
 ```toml
 [dependencies]
-"rggen" = { github = "rggen/rggen-veryl-rtl", version = "0.4.0" }
+"rggen" = { github = "rggen/rggen-veryl-rtl", version = "0.5.0" }
 ```
 
 ## Contact

data/lib/rggen/veryl/bit_field/common.erb

@@ -1,7 +1,7 @@
 always_comb {
-  <%= bit_field_if.valid %> = <%= register.bit_field_if.valid %>;
-  <%= bit_field_if.read_mask %> = <%= register.bit_field_if.read_mask[lsb, width] %>;
-  <%= bit_field_if.write_mask %> = <%= register.bit_field_if.write_mask[lsb, width] %>;
+  <%= bit_field_if.read_valid %> = <%= register.bit_field_if.read_valid %>;
+  <%= bit_field_if.write_valid %> = <%= register.bit_field_if.write_valid %>;
+  <%= bit_field_if.mask %> = <%= register.bit_field_if.mask[lsb, width] %>;
   <%= bit_field_if.write_data %> = <%= register.bit_field_if.write_data[lsb, width] %>;
   <%= register.bit_field_if.read_data[lsb, width] %> = <%= bit_field_if.read_data %>;
   <%= register.bit_field_if.value[lsb, width] %> = <%= bit_field_if.value %>;

data/lib/rggen/veryl/bit_field/type/custom.erb

@@ -4,6 +4,9 @@ inst u_bit_field: rggen::rggen_bit_field #(
   SW_READ_ACTION:     rggen_sw_action::<%= sw_read_action %>,
   SW_WRITE_ACTION:    rggen_sw_action::<%= sw_write_action %>,
   SW_WRITE_ONCE:      <%= write_once? %>,
+  HW_WRITE:           <%= bit_field.hw_write? %>,
+  HW_SET:             <%= bit_field.hw_set? %>,
+  HW_CLEAR:           <%= bit_field.hw_clear? %>,
   STORAGE:            <%= storage? %>,
   EXTERNAL_READ_DATA: <%= external_read_data? %>,
   TRIGGER:            <%= trigger? %>

data/lib/rggen/veryl/bit_field/type/rc_w0c_w1c_wc_woc.erb

@@ -2,7 +2,9 @@ inst u_bit_field: rggen::rggen_bit_field #(
   WIDTH:            <%= width %>,
   INITIAL_VALUE:    <%= initial_value %>,
   SW_READ_ACTION:   rggen_sw_action::<%= read_action %>,
-  SW_WRITE_ACTION:  rggen_sw_action::<%= write_action %>
+  SW_WRITE_ACTION:  rggen_sw_action::<%= write_action %>,
+  HW_SET:           true,
+  EXTERNAL_MASK:    <%= external_mask %>
 )(
   i_clk:            <%= clock %>,
   i_rst:            <%= reset %>,

data/lib/rggen/veryl/bit_field/type/rc_w0c_w1c_wc_woc.rb

@@ -35,5 +35,9 @@ RgGen.define_list_item_feature(:bit_field, :type, [:rc, :w0c, :w1c, :wc, :woc])
     def value_out_unmasked_singal
       bit_field.reference? && value_unmasked[loop_variables] || unused
     end
+
+    def external_mask
+      bit_field.reference?
+    end
   end
 end

data/lib/rggen/veryl/bit_field/type/rohw.erb

@@ -1,7 +1,8 @@
 inst u_bit_field: rggen::rggen_bit_field #(
   WIDTH:            <%= width %>,
   INITIAL_VALUE:    <%= initial_value %>,
-  SW_WRITE_ACTION:  rggen_sw_action::WRITE_NONE
+  SW_WRITE_ACTION:  rggen_sw_action::WRITE_NONE,
+  HW_WRITE:         true
 )(
   i_clk:              <%= clock %>,
   i_rst:              <%= reset %>,

data/lib/rggen/veryl/bit_field/type/rs_w0s_w1s_ws_wos.erb

@@ -2,7 +2,8 @@ inst u_bit_field: rggen::rggen_bit_field #(
   WIDTH:            <%= width %>,
   INITIAL_VALUE:    <%= initial_value %>,
   SW_READ_ACTION:   rggen_sw_action::<%= read_action %>,
-  SW_WRITE_ACTION:  rggen_sw_action::<%= write_action %>
+  SW_WRITE_ACTION:  rggen_sw_action::<%= write_action %>,
+  HW_CLEAR:         true
 )(
   i_clk:        <%= clock %>,
   i_rst:        <%= reset %>,

data/lib/rggen/veryl/bit_field/type/rwc.erb

@@ -1,6 +1,7 @@
 inst u_bit_field: rggen::rggen_bit_field #(
   WIDTH:          <%= width %>,
   INITIAL_VALUE:  <%= initial_value %>,
+  HW_CLEAR:       true,
   HW_CLEAR_WIDTH: 1
 )(
   i_clk:        <%= clock %>,

data/lib/rggen/veryl/bit_field/type/rwe_rwl.erb

@@ -1,6 +1,7 @@
 inst u_bit_field: rggen::rggen_bit_field #(
   WIDTH:                    <%= width %>,
   INITIAL_VALUE:            <%= initial_value %>,
+  SW_WRITE_CONTROL:         true,
   SW_WRITE_ENABLE_POLARITY: rggen_polarity::<%= polarity %>
 )(
   i_clk:              <%= clock %>,

data/lib/rggen/veryl/bit_field/type/rwhw.erb

@@ -1,6 +1,7 @@
 inst u_bit_field: rggen::rggen_bit_field #(
   WIDTH:          <%= width %>,
-  INITIAL_VALUE:  <%= initial_value %>
+  INITIAL_VALUE:  <%= initial_value %>,
+  HW_WRITE:       true
 )(
   i_clk:              <%= clock %>,
   i_rst:              <%= reset %>,

data/lib/rggen/veryl/bit_field/type/rws.erb

@@ -1,6 +1,7 @@
 inst u_bit_field: rggen::rggen_bit_field #(
   WIDTH:          <%= width %>,
   INITIAL_VALUE:  <%= initial_value %>,
+  HW_SET:         true,
   HW_SET_WIDTH:   1
 )(
   i_clk:        <%= clock %>,

data/lib/rggen/veryl/bit_field/veryl_top.rb

@@ -21,7 +21,7 @@ RgGen.define_simple_feature(:bit_field, :veryl_top) do
         name: 'bit_field_sub_if', interface_type: 'rggen::rggen_bit_field_if',
         param_values: { WIDTH: bit_field.width },
         variables: [
-          'valid', 'read_mask', 'write_mask', 'write_data', 'read_data', 'value'
+          'read_valid', 'write_valid', 'mask', 'write_data', 'read_data', 'value'
         ]
       }
     end

data/lib/rggen/veryl/register/veryl_top.rb

@@ -10,7 +10,7 @@ RgGen.define_simple_feature(:register, :veryl_top) do
           name: 'bit_field_if', interface_type: 'rggen::rggen_bit_field_if',
           param_values: { WIDTH: register.width },
           variables: [
-            'valid', 'read_mask', 'write_mask', 'write_data', 'read_data', 'value'
+            'read_valid', 'write_valid', 'mask', 'write_data', 'read_data', 'value'
           ]
         }
       end

data/lib/rggen/veryl/version.rb

@@ -2,6 +2,6 @@
 
 module RgGen
   module Veryl
-    VERSION = '0.4.0'
+    VERSION = '0.5.0'
   end
 end

metadata

@@ -1,13 +1,13 @@
 --- !ruby/object:Gem::Specification
 name: rggen-veryl
 version: !ruby/object:Gem::Version
-  version: 0.4.0
+  version: 0.5.0
 platform: ruby
 authors:
 - Taichi Ishitani
 bindir: bin
 cert_chain: []
-date: 2025-04-02 00:00:00.000000000 Z
+date: 2025-06-01 00:00:00.000000000 Z
 dependencies:
 - !ruby/object:Gem::Dependency
   name: rggen-systemverilog
@@ -15,14 +15,14 @@ dependencies:
     requirements:
     - - ">="
       - !ruby/object:Gem::Version
-        version: 0.35.0
+        version: 0.35.1
   type: :runtime
   prerelease: false
   version_requirements: !ruby/object:Gem::Requirement
     requirements:
     - - ">="
       - !ruby/object:Gem::Version
-        version: 0.35.0
+        version: 0.35.1
 description: Veryl writer plugin for RgGen
 email:
 - rggen@googlegroups.com
@@ -132,5 +132,5 @@ required_rubygems_version: !ruby/object:Gem::Requirement
 requirements: []
 rubygems_version: 3.6.2
 specification_version: 4
-summary: rggen-veryl-0.4.0
+summary: rggen-veryl-0.5.0
 test_files: []