rggen-veryl 0.2.0 → 0.3.0

checksums.yaml

@@ -1,7 +1,7 @@
 ---
 SHA256:
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-  data.tar.gz: ae23f0f755feec61cc0b737f64d421bb0a7e33cbf1121cbba6b1672127ae816d
+  metadata.gz: 921880c7d144cdd7dbb3c2cc585dc1e4c1bf31031b361708e841ba4865b8f71c
+  data.tar.gz: '06838b3a4664045b2a8a9e2cd03f18aac6abfa587f383b02eb99c77566ec2bd5'
 SHA512:
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data/README.md

@@ -1,6 +1,6 @@
 [![Gem Version](https://badge.fury.io/rb/rggen-veryl.svg)](https://badge.fury.io/rb/rggen-veryl)
 [![CI](https://github.com/rggen/rggen-veryl/actions/workflows/ci.yml/badge.svg)](https://github.com/rggen/rggen-veryl/actions/workflows/ci.yml)
-[![Maintainability](https://api.codeclimate.com/v1/badges/6f93e66d558f43d0693e/maintainability)](https://codeclimate.com/github/rggen/rggen-veryl/maintainability)
+[![Maintainability](https://qlty.sh/badges/7537364e-4631-4c9a-b873-5bceb9418ed0/maintainability.svg)](https://qlty.sh/gh/rggen/projects/rggen-veryl)
 [![codecov](https://codecov.io/gh/rggen/rggen-veryl/graph/badge.svg?token=iYlaqhSjat)](https://codecov.io/gh/rggen/rggen-veryl)
 [![Gitter](https://badges.gitter.im/rggen/rggen.svg)](https://gitter.im/rggen/rggen?utm_source=badge&utm_medium=badge&utm_campaign=pr-badge)
 
@@ -43,7 +43,7 @@ You need to add this repository to the `[dependencies]` section in your `Veryl.t
 
 ```toml
 [dependencies]
-"https://github.com/rggen/rggen-veryl-rtl" = "0.2.0"
+"https://github.com/rggen/rggen-veryl-rtl" = "0.3.0"
 ```
 
 ## Contact

data/lib/rggen/veryl/bit_field/type/custom.erb

@@ -13,13 +13,10 @@ inst u_bit_field: rggen::rggen_bit_field #(
   bit_field_if:       bit_field_sub_if,
   o_write_trigger:    <%= output_port(:write_trigger) %>,
   o_read_trigger:     <%= output_port(:read_trigger) %>,
-  i_sw_write_enable:  '1,
   i_hw_write_enable:  <%= input_port(:hw_write_enable) %>,
   i_hw_write_data:    <%= input_port(:hw_write_data) %>,
   i_hw_set:           <%= input_port(:hw_set) %>,
   i_hw_clear:         <%= input_port(:hw_clear) %>,
   i_value:            <%= input_port(:value_in) %>,
-  i_mask:             '1,
-  o_value:            <%= output_port(:value_out) %>,
-  o_value_unmasked:   _
+  o_value:            <%= output_port(:value_out) %>
 );

data/lib/rggen/veryl/bit_field/type/rc_w0c_w1c_wc_woc.erb

@@ -4,18 +4,11 @@ inst u_bit_field: rggen::rggen_bit_field #(
   SW_READ_ACTION:   rggen_sw_action::<%= read_action %>,
   SW_WRITE_ACTION:  rggen_sw_action::<%= write_action %>
 )(
-  i_clk:              <%= clock %>,
-  i_rst:              <%= reset %>,
-  bit_field_if:       <%= bit_field_if %>,
-  o_write_trigger:    _,
-  o_read_trigger:     _,
-  i_sw_write_enable:  <%= sw_write_enable %>,
-  i_hw_write_enable:  '0,
-  i_hw_write_data:    '0,
-  i_hw_set:           <%= set[loop_variables] %>,
-  i_hw_clear:         '0,
-  i_value:            '0,
-  i_mask:             <%= mask %>,
-  o_value:            <%= value_out[loop_variables] %>,
-  o_value_unmasked:   <%= value_out_unmasked_singal %>
+  i_clk:            <%= clock %>,
+  i_rst:            <%= reset %>,
+  bit_field_if:     <%= bit_field_if %>,
+  i_hw_set:         <%= set[loop_variables] %>,
+  i_mask:           <%= mask %>,
+  o_value:          <%= value_out[loop_variables] %>,
+  o_value_unmasked: <%= value_out_unmasked_singal %>
 );

data/lib/rggen/veryl/bit_field/type/rc_w0c_w1c_wc_woc.rb

@@ -32,10 +32,6 @@ RgGen.define_list_item_feature(:bit_field, :type, [:rc, :w0c, :w1c, :wc, :woc])
       }.fetch(bit_field.type, 'WRITE_CLEAR')
     end
 
-    def sw_write_enable
-      bit_field.type == :rc && all_bits_0 || all_bits_1
-    end
-
     def value_out_unmasked_singal
       bit_field.reference? && value_unmasked[loop_variables] || unused
     end

data/lib/rggen/veryl/bit_field/type/ro_rotrg.erb

@@ -1,21 +1,13 @@
 inst u_bit_field: rggen::rggen_bit_field #(
   WIDTH:              <%= width %>,
+  SW_WRITE_ACTION:    rggen_sw_action::WRITE_NONE,
   STORAGE:            0,
   EXTERNAL_READ_DATA: 1,
   TRIGGER:            <%= trigger %>
 )(
-  i_clk:              <%= clock %>,
-  i_rst:              <%= reset %>,
-  bit_field_if:       <%= bit_field_if %>,
-  o_write_trigger:    _,
-  o_read_trigger:     <%= read_trigger_signal %>,
-  i_sw_write_enable:  '0,
-  i_hw_write_enable:  '0,
-  i_hw_write_data:    '0,
-  i_hw_set:           '0,
-  i_hw_clear:         '0,
-  i_value:            <%= value_in_signal %>,
-  i_mask:             '1,
-  o_value:            _,
-  o_value_unmasked:   _
+  i_clk:          <%= clock %>,
+  i_rst:          <%= reset %>,
+  bit_field_if:   <%= bit_field_if %>,
+  o_read_trigger: <%= read_trigger_signal %>,
+  i_value:        <%= value_in_signal %>
 );

data/lib/rggen/veryl/bit_field/type/rof.erb

@@ -1,20 +1,11 @@
 inst u_bit_field: rggen::rggen_bit_field #(
   WIDTH:              <%= width %>,
+  SW_WRITE_ACTION:    rggen_sw_action::WRITE_NONE,
   STORAGE:            0,
   EXTERNAL_READ_DATA: 1
 )(
-  i_clk:              '0,
-  i_rst:              '0,
-  bit_field_if:       <%= bit_field_if %>,
-  o_write_trigger:    _,
-  o_read_trigger:     _,
-  i_sw_write_enable:  '0,
-  i_hw_write_enable:  '0,
-  i_hw_write_data:    '0,
-  i_hw_set:           '0,
-  i_hw_clear:         '0,
-  i_value:            <%= initial_value %>,
-  i_mask:             '1,
-  o_value:            _,
-  o_value_unmasked:   _
+  i_clk:        '0,
+  i_rst:        '0,
+  bit_field_if: <%= bit_field_if %>,
+  i_value:      <%= initial_value %>
 );

data/lib/rggen/veryl/bit_field/type/rohw.erb

@@ -6,15 +6,7 @@ inst u_bit_field: rggen::rggen_bit_field #(
   i_clk:              <%= clock %>,
   i_rst:              <%= reset %>,
   bit_field_if:       <%= bit_field_if %>,
-  o_write_trigger:    _,
-  o_read_trigger:     _,
-  i_sw_write_enable:  '0,
   i_hw_write_enable:  <%= valid_signal %>,
   i_hw_write_data:    <%= value_in[loop_variables] %>,
-  i_hw_set:           '0,
-  i_hw_clear:         '0,
-  i_value:            '0,
-  i_mask:             '1,
-  o_value:            <%= value_out[loop_variables] %>,
-  o_value_unmasked:   _
+  o_value:            <%= value_out[loop_variables] %>
 );

data/lib/rggen/veryl/bit_field/type/rowo_rowotrg.erb

@@ -4,18 +4,11 @@ inst u_bit_field: rggen::rggen_bit_field #(
   EXTERNAL_READ_DATA: 1,
   TRIGGER:            <%= trigger %>
 )(
-  i_clk:              <%= clock %>,
-  i_rst:              <%= reset %>,
-  bit_field_if:       <%= bit_field_if %>,
-  o_write_trigger:    <%= write_trigger_signal %>,
-  o_read_trigger:     <%= read_trigger_signal %>,
-  i_sw_write_enable:  '1,
-  i_hw_write_enable:  '0,
-  i_hw_write_data:    '0,
-  i_hw_set:           '0,
-  i_hw_clear:         '0,
-  i_value:            <%= value_in_signal %>,
-  i_mask:             '1,
-  o_value:            <%= value_out[loop_variables] %>,
-  o_value_unmasked:   _
+  i_clk:            <%= clock %>,
+  i_rst:            <%= reset %>,
+  bit_field_if:     <%= bit_field_if %>,
+  o_write_trigger:  <%= write_trigger_signal %>,
+  o_read_trigger:   <%= read_trigger_signal %>,
+  i_value:          <%= value_in_signal %>,
+  o_value:          <%= value_out[loop_variables] %>
 );

data/lib/rggen/veryl/bit_field/type/rs_w0s_w1s_ws_wos.erb

@@ -4,18 +4,9 @@ inst u_bit_field: rggen::rggen_bit_field #(
   SW_READ_ACTION:   rggen_sw_action::<%= read_action %>,
   SW_WRITE_ACTION:  rggen_sw_action::<%= write_action %>
 )(
-  i_clk:              <%= clock %>,
-  i_rst:              <%= reset %>,
-  bit_field_if:       <%= bit_field_if %>,
-  o_write_trigger:    _,
-  o_read_trigger:     _,
-  i_sw_write_enable:  <%= sw_write_enable %>,
-  i_hw_write_enable:  '0,
-  i_hw_write_data:    '0,
-  i_hw_set:           '0,
-  i_hw_clear:         <%= clear[loop_variables] %>,
-  i_value:            '0,
-  i_mask:             '1,
-  o_value:            <%= value_out[loop_variables] %>,
-  o_value_unmasked:   _
+  i_clk:        <%= clock %>,
+  i_rst:        <%= reset %>,
+  bit_field_if: <%= bit_field_if %>,
+  i_hw_clear:   <%= clear[loop_variables] %>,
+  o_value:      <%= value_out[loop_variables] %>
 );

data/lib/rggen/veryl/bit_field/type/rs_w0s_w1s_ws_wos.rb

@@ -26,9 +26,5 @@ RgGen.define_list_item_feature(:bit_field, :type, [:rs, :w0s, :w1s, :ws, :wos])
         rs: 'WRITE_NONE', w0s: 'WRITE_0_SET', w1s: 'WRITE_1_SET'
       }.fetch(bit_field.type, 'WRITE_SET')
     end
-
-    def sw_write_enable
-      bit_field.writable? && all_bits_1 || all_bits_0
-    end
   end
 end

data/lib/rggen/veryl/bit_field/type/rw_rwtrg_w1.erb

@@ -4,18 +4,10 @@ inst u_bit_field: rggen::rggen_bit_field #(
   SW_WRITE_ONCE:  <%= write_once %>,
   TRIGGER:        <%= trigger %>
 )(
-  i_clk:              <%= clock %>,
-  i_rst:              <%= reset %>,
-  bit_field_if:       <%= bit_field_if %>,
-  o_write_trigger:    <%= write_trigger_signal %>,
-  o_read_trigger:     <%= read_trigger_signal %>,
-  i_sw_write_enable:  '1,
-  i_hw_write_enable:  '0,
-  i_hw_write_data:    '0,
-  i_hw_set:           '0,
-  i_hw_clear:         '0,
-  i_value:            '0,
-  i_mask:             '1,
-  o_value:            <%= value_out[loop_variables] %>,
-  o_value_unmasked:   _
+  i_clk:            <%= clock %>,
+  i_rst:            <%= reset %>,
+  bit_field_if:     <%= bit_field_if %>,
+  o_write_trigger:  <%= write_trigger_signal %>,
+  o_read_trigger:   <%= read_trigger_signal %>,
+  o_value:          <%= value_out[loop_variables] %>
 );

data/lib/rggen/veryl/bit_field/type/rwc.erb

@@ -3,18 +3,9 @@ inst u_bit_field: rggen::rggen_bit_field #(
   INITIAL_VALUE:  <%= initial_value %>,
   HW_CLEAR_WIDTH: 1
 )(
-  i_clk:              <%= clock %>,
-  i_rst:              <%= reset %>,
-  bit_field_if:       <%= bit_field_if %>,
-  o_write_trigger:    _,
-  o_read_trigger:     _,
-  i_sw_write_enable:  '1,
-  i_hw_write_enable:  '0,
-  i_hw_write_data:    '0,
-  i_hw_set:           '0,
-  i_hw_clear:         <%= clear_signal %>,
-  i_value:            '0,
-  i_mask:             '1,
-  o_value:            <%= value_out[loop_variables] %>,
-  o_value_unmasked:   _
+  i_clk:        <%= clock %>,
+  i_rst:        <%= reset %>,
+  bit_field_if: <%= bit_field_if %>,
+  i_hw_clear:   <%= clear_signal %>,
+  o_value:      <%= value_out[loop_variables] %>
 );

data/lib/rggen/veryl/bit_field/type/rwe_rwl.erb

@@ -6,15 +6,6 @@ inst u_bit_field: rggen::rggen_bit_field #(
   i_clk:              <%= clock %>,
   i_rst:              <%= reset %>,
   bit_field_if:       <%= bit_field_if %>,
-  o_write_trigger:    _,
-  o_read_trigger:     _,
   i_sw_write_enable:  <%= control_signal %>,
-  i_hw_write_enable:  '0,
-  i_hw_write_data:    '0,
-  i_hw_set:           '0,
-  i_hw_clear:         '0,
-  i_value:            '0,
-  i_mask:             '1,
-  o_value:            <%= value_out[loop_variables] %>,
-  o_value_unmasked:   _
+  o_value:            <%= value_out[loop_variables] %>
 );

data/lib/rggen/veryl/bit_field/type/rwhw.erb

@@ -5,15 +5,7 @@ inst u_bit_field: rggen::rggen_bit_field #(
   i_clk:              <%= clock %>,
   i_rst:              <%= reset %>,
   bit_field_if:       <%= bit_field_if %>,
-  o_write_trigger:    _,
-  o_read_trigger:     _,
-  i_sw_write_enable:  '1,
   i_hw_write_enable:  <%= valid_signal %>,
   i_hw_write_data:    <%= value_in[loop_variables] %>,
-  i_hw_set:           '0,
-  i_hw_clear:         '0,
-  i_value:            '0,
-  i_mask:             '1,
-  o_value:            <%= value_out[loop_variables] %>,
-  o_value_unmasked:   _
+  o_value:            <%= value_out[loop_variables] %>
 );

data/lib/rggen/veryl/bit_field/type/rws.erb

@@ -3,18 +3,9 @@ inst u_bit_field: rggen::rggen_bit_field #(
   INITIAL_VALUE:  <%= initial_value %>,
   HW_SET_WIDTH:   1
 )(
-  i_clk:              <%= clock %>,
-  i_rst:              <%= reset %>,
-  bit_field_if:       <%= bit_field_if %>,
-  o_write_trigger:    _,
-  o_read_trigger:     _,
-  i_sw_write_enable:  '1,
-  i_hw_write_enable:  '0,
-  i_hw_write_data:    '0,
-  i_hw_set:           <%= set_signal %>,
-  i_hw_clear:         '0,
-  i_value:            '0,
-  i_mask:             '1,
-  o_value:            <%= value_out[loop_variables] %>,
-  o_value_unmasked:   _
+  i_clk:        <%= clock %>,
+  i_rst:        <%= reset %>,
+  bit_field_if: <%= bit_field_if %>,
+  i_hw_set:     <%= set_signal %>,
+  o_value:      <%= value_out[loop_variables] %>
 );

data/lib/rggen/veryl/bit_field/type/w0crs_w0src_w1crs_w1src_wcrs_wsrc.erb

@@ -4,18 +4,8 @@ inst u_bit_field: rggen::rggen_bit_field #(
   SW_READ_ACTION:   rggen_sw_action::<%= read_action %>,
   SW_WRITE_ACTION:  rggen_sw_action::<%= write_action %>
 )(
-  i_clk:              <%= clock %>,
-  i_rst:              <%= reset %>,
-  bit_field_if:       <%= bit_field_if %>,
-  o_write_trigger:    _,
-  o_read_trigger:     _,
-  i_sw_write_enable:  '1,
-  i_hw_write_enable:  '0,
-  i_hw_write_data:    '0,
-  i_hw_set:           '0,
-  i_hw_clear:         '0,
-  i_value:            '0,
-  i_mask:             '1,
-  o_value:            <%= value_out[loop_variables] %>,
-  o_value_unmasked:   _
+  i_clk:        <%= clock %>,
+  i_rst:        <%= reset %>,
+  bit_field_if: <%= bit_field_if %>,
+  o_value:      <%= value_out[loop_variables] %>
 );

data/lib/rggen/veryl/bit_field/type/w0t_w1t.erb

@@ -3,18 +3,8 @@ inst u_bit_field: rggen::rggen_bit_field #(
   INITIAL_VALUE:    <%= initial_value %>,
   SW_WRITE_ACTION:  rggen_sw_action::<%= write_action %>
 )(
-  i_clk:              <%= clock %>,
-  i_rst:              <%= reset %>,
-  bit_field_if:       <%= bit_field_if %>,
-  o_write_trigger:    _,
-  o_read_trigger:     _,
-  i_sw_write_enable:  '1,
-  i_hw_write_enable:  '0,
-  i_hw_write_data:    '0,
-  i_hw_set:           '0,
-  i_hw_clear:         '0,
-  i_value:            '0,
-  i_mask:             '1,
-  o_value:            <%= value_out[loop_variables] %>,
-  o_value_unmasked:   _
+  i_clk:        <%= clock %>,
+  i_rst:        <%= reset %>,
+  bit_field_if: <%= bit_field_if %>,
+  o_value:      <%= value_out[loop_variables] %>
 );

data/lib/rggen/veryl/bit_field/type/w0trg_w1trg.erb

@@ -5,6 +5,5 @@ inst u_bit_field: rggen::rggen_bit_field_w01trg #(
   i_clk:        <%= clock %>,
   i_rst:        <%= reset %>,
   bit_field_if: <%= bit_field_if %>,
-  i_value:      '0,
   o_trigger:    <%= trigger[loop_variables] %>
 );

data/lib/rggen/veryl/bit_field/type/wo_wo1_wotrg.erb

@@ -5,18 +5,9 @@ inst u_bit_field: rggen::rggen_bit_field #(
   SW_WRITE_ONCE:  <%= write_once %>,
   TRIGGER:        <%= trigger %>
 )(
-  i_clk:              <%= clock %>,
-  i_rst:              <%= reset %>,
-  bit_field_if:       <%= bit_field_if %>,
-  o_write_trigger:    <%= write_trigger_signal %>,
-  o_read_trigger:     _,
-  i_sw_write_enable:  '1,
-  i_hw_write_enable:  '0,
-  i_hw_write_data:    '0,
-  i_hw_set:           '0,
-  i_hw_clear:         '0,
-  i_value:            '0,
-  i_mask:             '1,
-  o_value:            <%= value_out[loop_variables] %>,
-  o_value_unmasked:   _
+  i_clk:            <%= clock %>,
+  i_rst:            <%= reset %>,
+  bit_field_if:     <%= bit_field_if %>,
+  o_write_trigger:  <%= write_trigger_signal %>,
+  o_value:          <%= value_out[loop_variables] %>
 );

data/lib/rggen/veryl/bit_field/type/wrc_wrs.erb

@@ -3,18 +3,8 @@ inst u_bit_field: rggen::rggen_bit_field #(
   INITIAL_VALUE:  <%= initial_value %>,
   SW_READ_ACTION: rggen_sw_action::<%= read_action %>
 )(
-  i_clk:              <%= clock %>,
-  i_rst:              <%= reset %>,
-  bit_field_if:       <%= bit_field_if %>,
-  o_write_trigger:    _,
-  o_read_trigger:     _,
-  i_sw_write_enable:  '1,
-  i_hw_write_enable:  '0,
-  i_hw_write_data:    '0,
-  i_hw_set:           '0,
-  i_hw_clear:         '0,
-  i_value:            '0,
-  i_mask:             '1,
-  o_value:            <%= value_out[loop_variables] %>,
-  o_value_unmasked:   _
+  i_clk:        <%= clock %>,
+  i_rst:        <%= reset %>,
+  bit_field_if: <%= bit_field_if %>,
+  o_value:      <%= value_out[loop_variables] %>
 );

data/lib/rggen/veryl/bit_field/type.rb

@@ -32,8 +32,7 @@ RgGen.define_list_feature(:bit_field, :type) do
       end
 
       def initial_value
-        index =
-          bit_field.initial_value_array? && bit_field.local_index || nil
+        index = bit_field.initial_value_array? && loop_variables || nil
         bit_field.initial_value[index]
       end
 
@@ -46,7 +45,7 @@ RgGen.define_list_feature(:bit_field, :type) do
 
         bit_field
           .find_reference(register_block.bit_fields)
-          .value(bit_field.local_indices, bit_field.reference_width)
+          .value(bit_field.local_indexes, bit_field.reference_width)
       end
 
       def mask

data/lib/rggen/veryl/bit_field/veryl_top.rb

@@ -52,18 +52,17 @@ RgGen.define_simple_feature(:bit_field, :veryl_top) do
     end
 
     def initial_value_size
-      return unless bit_field.initial_value_array?
-
-      [bit_field.sequence_size]
+      bit_field.initial_value_array? && array_size || nil
     end
 
     def initial_value_rhs
       if !bit_field.initial_value_array?
         sized_initial_value
       elsif bit_field.fixed_initial_value?
-        array(sized_initial_values)
+        concat(sized_initial_values)
       else
-        repeat(bit_field.sequence_size, sized_initial_value)
+        size = array_size.inject(:*)
+        repeat(size, sized_initial_value)
       end
     end
 
@@ -72,11 +71,14 @@ RgGen.define_simple_feature(:bit_field, :veryl_top) do
     end
 
     def sized_initial_values
-      bit_field.initial_values.map { |v| hex(v, bit_field.width) }
+      bit_field
+        .initial_values(flatten: true)
+        .map { |v| hex(v, bit_field.width) }
+        .reverse
     end
 
     def register_if(offsets)
-      index = register.index(offsets || register.local_indices)
+      index = register.index(offsets || register.local_indexes)
       register_block.register_if[index]
     end
 

data/lib/rggen/veryl/register_block/protocol/avalon.erb

@@ -0,0 +1,17 @@
+inst u_adapter: rggen::rggen_avalon_adapter #(
+  ADDRESS_WIDTH:        <%= address_width %>,
+  LOCAL_ADDRESS_WIDTH:  <%= local_address_width %>,
+  BUS_WIDTH:            <%= bus_width %>,
+  REGISTERS:            <%= total_registers %>,
+  PRE_DECODE:           <%= pre_decode %>,
+  BASE_ADDRESS:         <%= base_address %>,
+  BYTE_SIZE:            <%= byte_size %>,
+  ERROR_STATUS:         <%= error_status %>,
+  DEFAULT_READ_DATA:    <%= default_read_data %>,
+  INSERT_SLICER:        <%= insert_slicer %>
+)(
+  i_clk:        <%= register_block.clock %>,
+  i_rst:        <%= register_block.reset %>,
+  avalon_if:    <%= avalon_if %>,
+  register_if:  <%= register_block.register_if %>
+);

data/lib/rggen/veryl/register_block/protocol/avalon.rb

@@ -0,0 +1,14 @@
+# frozen_string_literal: true
+
+RgGen.define_list_item_feature(:register_block, :protocol, :avalon) do
+  veryl do
+    build do
+      modport :avalon_if, {
+        name: 'avalon_if',
+        interface_type: 'rggen::rggen_avalon_if', modport: 'agent'
+      }
+    end
+
+    main_code :register_block, from_template: true
+  end
+end

data/lib/rggen/veryl/register_block/protocol/native.erb

@@ -7,6 +7,7 @@ inst u_adapter: rggen::rggen_native_adapter #(
   PRE_DECODE:           <%= pre_decode %>,
   BASE_ADDRESS:         <%= base_address %>,
   BYTE_SIZE:            <%= byte_size %>,
+  USE_READ_STROBE:      <%= use_read_strobe %>,
   ERROR_STATUS:         <%= error_status %>,
   DEFAULT_READ_DATA:    <%= default_read_data %>,
   INSERT_SLICER:        <%= insert_slicer %>

data/lib/rggen/veryl/register_block/protocol/native.rb

@@ -6,6 +6,9 @@ RgGen.define_list_item_feature(:register_block, :protocol, :native) do
       param :strobe_width, {
         name: 'STROBE_WIDTH', type: :u32, default: bus_width / 8
       }
+      param :use_read_strobe, {
+        name: 'USE_READ_STROBE', type: :bit, default: 0
+      }
       modport :csrbus_if, {
         name: 'csrbus_if',
         interface_type: 'rggen::rggen_bus_if', modport: 'slave'

data/lib/rggen/veryl/version.rb

@@ -2,6 +2,6 @@
 
 module RgGen
   module Veryl
-    VERSION = '0.2.0'
+    VERSION = '0.3.0'
   end
 end

data/lib/rggen/veryl.rb

@@ -28,6 +28,7 @@ RgGen.setup_plugin :'rggen-veryl' do |plugin|
     'veryl/register_block/protocol',
     'veryl/register_block/protocol/apb',
     'veryl/register_block/protocol/axi4lite',
+    'veryl/register_block/protocol/avalon',
     'veryl/register_block/protocol/wishbone',
     'veryl/register_block/protocol/native',
     'veryl/register_file/veryl_top',

metadata

@@ -1,13 +1,13 @@
 --- !ruby/object:Gem::Specification
 name: rggen-veryl
 version: !ruby/object:Gem::Version
-  version: 0.2.0
+  version: 0.3.0
 platform: ruby
 authors:
 - Taichi Ishitani
 bindir: bin
 cert_chain: []
-date: 2025-01-23 00:00:00.000000000 Z
+date: 2025-02-19 00:00:00.000000000 Z
 dependencies:
 - !ruby/object:Gem::Dependency
   name: rggen-systemverilog
@@ -15,14 +15,14 @@ dependencies:
     requirements:
     - - ">="
       - !ruby/object:Gem::Version
-        version: 0.34.0
+        version: 0.35.0
   type: :runtime
   prerelease: false
   version_requirements: !ruby/object:Gem::Requirement
     requirements:
     - - ">="
       - !ruby/object:Gem::Version
-        version: 0.34.0
+        version: 0.35.0
 description: Veryl writer plugin for RgGen
 email:
 - rggen@googlegroups.com
@@ -88,6 +88,8 @@ files:
 - lib/rggen/veryl/register_block/protocol.rb
 - lib/rggen/veryl/register_block/protocol/apb.erb
 - lib/rggen/veryl/register_block/protocol/apb.rb
+- lib/rggen/veryl/register_block/protocol/avalon.erb
+- lib/rggen/veryl/register_block/protocol/avalon.rb
 - lib/rggen/veryl/register_block/protocol/axi4lite.erb
 - lib/rggen/veryl/register_block/protocol/axi4lite.rb
 - lib/rggen/veryl/register_block/protocol/native.erb
@@ -130,5 +132,5 @@ required_rubygems_version: !ruby/object:Gem::Requirement
 requirements: []
 rubygems_version: 3.6.2
 specification_version: 4
-summary: rggen-veryl-0.2.0
+summary: rggen-veryl-0.3.0
 test_files: []