rggen-veryl 0.1.0 → 0.2.0

checksums.yaml

@@ -1,7 +1,7 @@
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data/LICENSE

@@ -1,6 +1,6 @@
 The MIT License (MIT)
 
-Copyright (c) 2024 Taichi Ishitani
+Copyright (c) 2024-2025 Taichi Ishitani
 
 Permission is hereby granted, free of charge, to any person obtaining a copy
 of this software and associated documentation files (the "Software"), to deal

data/README.md

@@ -1,6 +1,6 @@
 [![Gem Version](https://badge.fury.io/rb/rggen-veryl.svg)](https://badge.fury.io/rb/rggen-veryl)
 [![CI](https://github.com/rggen/rggen-veryl/actions/workflows/ci.yml/badge.svg)](https://github.com/rggen/rggen-veryl/actions/workflows/ci.yml)
-[![Maintainability](https://api.codeclimate.com/v1/badges/1babafbe1df4a1d7414f/maintainability)](https://codeclimate.com/github/rggen/rggen-veryl/maintainability)
+[![Maintainability](https://api.codeclimate.com/v1/badges/6f93e66d558f43d0693e/maintainability)](https://codeclimate.com/github/rggen/rggen-veryl/maintainability)
 [![codecov](https://codecov.io/gh/rggen/rggen-veryl/graph/badge.svg?token=iYlaqhSjat)](https://codecov.io/gh/rggen/rggen-veryl)
 [![Gitter](https://badges.gitter.im/rggen/rggen.svg)](https://gitter.im/rggen/rggen?utm_source=badge&utm_medium=badge&utm_campaign=pr-badge)
 
@@ -43,7 +43,7 @@ You need to add this repository to the `[dependencies]` section in your `Veryl.t
 
 ```toml
 [dependencies]
-"https://github.com/rggen/rggen-veryl-rtl" = "0.1.0"
+"https://github.com/rggen/rggen-veryl-rtl" = "0.2.0"
 ```
 
 ## Contact
@@ -58,8 +58,8 @@ Feedbacks, bus reports, questions and etc. are welcome! You can post them by usi
 
 ## Copyright & License
 
-Copyright © 2024 Taichi Ishitani. RgGen::Veryl is licensed under the [MIT License](https://opensource.org/licenses/MIT), see [LICENSE](LICENSE) for futher details.
+Copyright © 2024-2025 Taichi Ishitani. RgGen::Veryl is licensed under the [MIT License](https://opensource.org/licenses/MIT), see [LICENSE](LICENSE) for futher details.
 
 ## Code of Conduct
 
-Everyone interacting in the RgGen::Veryl project's codebases, issue trackers, chat rooms and mailing lists is expected to follow the [code of conduct](https://github.com/[USERNAME]/rggen-veryl/blob/master/CODE_OF_CONDUCT.md).
+Everyone interacting in the RgGen::Veryl project's codebases, issue trackers, chat rooms and mailing lists is expected to follow the [code of conduct](https://github.com/rggen/rggen-veryl/blob/master/CODE_OF_CONDUCT.md).

data/lib/rggen/veryl/bit_field/type/custom.rb

@@ -5,47 +5,39 @@ RgGen.define_list_item_feature(:bit_field, :type, :custom) do
     build do
       if external_read_data?
         input :value_in, {
-          name: "i_#{full_name}",
-          width: width, array_size: array_size
+          name: "i_#{full_name}", width:, array_size:
         }
       else
         output :value_out, {
-          name: "o_#{full_name}",
-          width: width, array_size: array_size
+          name: "o_#{full_name}", width:, array_size:
         }
       end
       if bit_field.hw_write?
         input :hw_write_enable, {
-          name: "i_#{full_name}_hw_write_enable",
-          width: 1, array_size: array_size
+          name: "i_#{full_name}_hw_write_enable", width: 1, array_size:
         }
         input :hw_write_data, {
-          name: "i_#{full_name}_hw_write_data",
-          width: width, array_size: array_size
+          name: "i_#{full_name}_hw_write_data", width:, array_size:
         }
       end
       if bit_field.hw_set?
         input :hw_set, {
-          name: "i_#{full_name}_hw_set",
-          width: width, array_size: array_size
+          name: "i_#{full_name}_hw_set", width:, array_size:
         }
       end
       if bit_field.hw_clear?
         input :hw_clear, {
-          name: "i_#{full_name}_hw_clear",
-          width: width, array_size: array_size
+          name: "i_#{full_name}_hw_clear", width:, array_size:
         }
       end
       if bit_field.write_trigger?
         output :write_trigger, {
-          name: "o_#{full_name}_write_trigger",
-          width: 1, array_size: array_size
+          name: "o_#{full_name}_write_trigger", width: 1, array_size:
         }
       end
       if bit_field.read_trigger?
         output :read_trigger, {
-          name: "o_#{full_name}_read_trigger",
-          width: 1, array_size: array_size
+          name: "o_#{full_name}_read_trigger", width: 1, array_size:
         }
       end
     end

data/lib/rggen/veryl/bit_field/type/rc_w0c_w1c_wc_woc.rb

@@ -4,17 +4,14 @@ RgGen.define_list_item_feature(:bit_field, :type, [:rc, :w0c, :w1c, :wc, :woc])
   veryl do
     build do
       input :set, {
-        name: "i_#{full_name}_set",
-        width: width, array_size: array_size
+        name: "i_#{full_name}_set", width:, array_size:
       }
       output :value_out, {
-        name: "o_#{full_name}",
-        width: width, array_size: array_size
+        name: "o_#{full_name}", width:, array_size:
       }
       if bit_field.reference?
         output :value_unmasked, {
-          name: "o_#{full_name}_unmasked",
-          width: width, array_size: array_size
+          name: "o_#{full_name}_unmasked", width:, array_size:
         }
       end
     end

data/lib/rggen/veryl/bit_field/type/ro_rotrg.rb

@@ -5,14 +5,12 @@ RgGen.define_list_item_feature(:bit_field, :type, [:ro, :rotrg]) do
     build do
       unless bit_field.reference?
         input :value_in, {
-          name: "i_#{full_name}",
-          width: width, array_size: array_size
+          name: "i_#{full_name}", width:, array_size:
         }
       end
       if rotrg?
         output :read_trigger, {
-          name: "o_#{full_name}_read_trigger",
-          width: 1, array_size: array_size
+          name: "o_#{full_name}_read_trigger", width: 1, array_size:
         }
       end
     end

data/lib/rggen/veryl/bit_field/type/rohw.rb

@@ -5,15 +5,14 @@ RgGen.define_list_item_feature(:bit_field, :type, :rohw) do
     build do
       unless bit_field.reference?
         input :valid, {
-          name: "i_#{full_name}_valid",
-          width: 1, array_size: array_size
+          name: "i_#{full_name}_valid", width: 1, array_size:
         }
       end
       input :value_in, {
-        name: "i_#{full_name}", width: width, array_size: array_size
+        name: "i_#{full_name}", width:, array_size:
       }
       output :value_out, {
-        name: "o_#{full_name}", width: width, array_size: array_size
+        name: "o_#{full_name}", width:, array_size:
       }
     end
 

data/lib/rggen/veryl/bit_field/type/row0trg_row1trg.rb

@@ -5,13 +5,11 @@ RgGen.define_list_item_feature(:bit_field, :type, [:row0trg, :row1trg]) do
     build do
       unless bit_field.reference?
         input :value_in, {
-          name: "i_#{full_name}",
-          width: width, array_size: array_size
+          name: "i_#{full_name}", width:, array_size:
         }
       end
       output :trigger, {
-        name: "o_#{full_name}_trigger",
-        width: width, array_size: array_size
+        name: "o_#{full_name}_trigger", width:, array_size:
       }
     end
 

data/lib/rggen/veryl/bit_field/type/rowo_rowotrg.rb

@@ -4,23 +4,19 @@ RgGen.define_list_item_feature(:bit_field, :type, [:rowo, :rowotrg]) do
   veryl do
     build do
       output :value_out, {
-        name: "o_#{full_name}",
-        width: width, array_size: array_size
+        name: "o_#{full_name}", width:, array_size:
       }
       unless bit_field.reference?
         input :value_in, {
-          name: "i_#{full_name}",
-          width: width, array_size: array_size
+          name: "i_#{full_name}", width:, array_size:
         }
       end
       if rowotrg?
         output :write_trigger, {
-          name: "o_#{full_name}_write_trigger",
-          width: 1, array_size: array_size
+          name: "o_#{full_name}_write_trigger", width: 1, array_size:
         }
         output :read_trigger, {
-          name: "o_#{full_name}_read_trigger",
-          width: 1, array_size: array_size
+          name: "o_#{full_name}_read_trigger", width: 1, array_size:
         }
       end
     end

data/lib/rggen/veryl/bit_field/type/rs_w0s_w1s_ws_wos.rb

@@ -4,12 +4,10 @@ RgGen.define_list_item_feature(:bit_field, :type, [:rs, :w0s, :w1s, :ws, :wos])
   veryl do
     build do
       input :clear, {
-        name: "i_#{full_name}_clear",
-        width: width, array_size: array_size
+        name: "i_#{full_name}_clear", width:, array_size:
       }
       output :value_out, {
-        name: "o_#{full_name}",
-        width: width, array_size: array_size
+        name: "o_#{full_name}", width:, array_size:
       }
     end
 

data/lib/rggen/veryl/bit_field/type/rw_rwtrg_w1.rb

@@ -4,17 +4,14 @@ RgGen.define_list_item_feature(:bit_field, :type, [:rw, :rwtrg, :w1]) do
   veryl do
     build do
       output :value_out, {
-        name: "o_#{full_name}",
-        width: width, array_size: array_size
+        name: "o_#{full_name}", width:, array_size:
       }
       if rwtrg?
         output :write_trigger, {
-          name: "o_#{full_name}_write_trigger",
-          width: 1, array_size: array_size
+          name: "o_#{full_name}_write_trigger", width: 1, array_size:
         }
         output :read_trigger, {
-          name: "o_#{full_name}_read_trigger",
-          width: 1, array_size: array_size
+          name: "o_#{full_name}_read_trigger", width: 1, array_size:
         }
       end
     end

data/lib/rggen/veryl/bit_field/type/rwc.rb

@@ -5,13 +5,11 @@ RgGen.define_list_item_feature(:bit_field, :type, :rwc) do
     build do
       unless bit_field.reference?
         input :clear, {
-          name: "i_#{full_name}_clear",
-          width: 1, array_size: array_size
+          name: "i_#{full_name}_clear", width: 1, array_size:
         }
       end
       output :value_out, {
-        name: "o_#{full_name}",
-        width: width, array_size: array_size
+        name: "o_#{full_name}", width:, array_size:
       }
     end
 

data/lib/rggen/veryl/bit_field/type/rwe_rwl.rb

@@ -5,13 +5,11 @@ RgGen.define_list_item_feature(:bit_field, :type, [:rwe, :rwl]) do
     build do
       unless bit_field.reference?
         input :control, {
-          name: "i_#{full_name}_#{enable_or_lock}",
-          width: 1, array_size: array_size
+          name: "i_#{full_name}_#{enable_or_lock}", width: 1, array_size:
         }
       end
       output :value_out, {
-        name: "o_#{full_name}",
-        width: width, array_size: array_size
+        name: "o_#{full_name}", width:, array_size:
       }
     end
 

data/lib/rggen/veryl/bit_field/type/rwhw.rb

@@ -5,17 +5,14 @@ RgGen.define_list_item_feature(:bit_field, :type, :rwhw) do
     build do
       unless bit_field.reference?
         input :valid, {
-          name: "i_#{full_name}_valid",
-          width: 1, array_size: array_size
+          name: "i_#{full_name}_valid", width: 1, array_size:
         }
       end
       input :value_in, {
-        name: "i_#{full_name}",
-        width: width, array_size: array_size
+        name: "i_#{full_name}", width:, array_size:
       }
       output :value_out, {
-        name: "o_#{full_name}",
-        width: width, array_size: array_size
+        name: "o_#{full_name}", width:, array_size:
       }
     end
 

data/lib/rggen/veryl/bit_field/type/rws.rb

@@ -5,13 +5,11 @@ RgGen.define_list_item_feature(:bit_field, :type, :rws) do
     build do
       unless bit_field.reference?
         input :set, {
-          name: "i_#{full_name}_set",
-          width: 1, array_size: array_size
+          name: "i_#{full_name}_set", width: 1, array_size:
         }
       end
       output :value_out, {
-        name: "o_#{full_name}",
-        width: width, array_size: array_size
+        name: "o_#{full_name}", width:, array_size:
       }
     end
 

data/lib/rggen/veryl/bit_field/type/w0crs_w0src_w1crs_w1src_wcrs_wsrc.rb

@@ -6,8 +6,7 @@ RgGen.define_list_item_feature(
   veryl do
     build do
       output :value_out, {
-        name: "o_#{full_name}",
-        width: width, array_size: array_size
+        name: "o_#{full_name}", width:, array_size:
       }
     end
 

data/lib/rggen/veryl/bit_field/type/w0t_w1t.rb

@@ -4,8 +4,7 @@ RgGen.define_list_item_feature(:bit_field, :type, [:w0t, :w1t]) do
   veryl do
     build do
       output :value_out, {
-        name: "o_#{full_name}",
-        width: width, array_size: array_size
+        name: "o_#{full_name}", width:, array_size:
       }
     end
 

data/lib/rggen/veryl/bit_field/type/w0trg_w1trg.rb

@@ -4,8 +4,7 @@ RgGen.define_list_item_feature(:bit_field, :type, [:w0trg, :w1trg]) do
   veryl do
     build do
       output :trigger, {
-        name: "o_#{full_name}_trigger",
-        width: width, array_size: array_size
+        name: "o_#{full_name}_trigger", width:, array_size:
       }
     end
 

data/lib/rggen/veryl/bit_field/type/wo_wo1_wotrg.rb

@@ -4,13 +4,11 @@ RgGen.define_list_item_feature(:bit_field, :type, [:wo, :wo1, :wotrg]) do
   veryl do
     build do
       output :value_out, {
-        name: "o_#{full_name}",
-        width: width, array_size: array_size
+        name: "o_#{full_name}", width:, array_size:
       }
       if wotrg?
         output :write_trigger, {
-          name: "o_#{full_name}_write_trigger",
-          width: 1, array_size: array_size
+          name: "o_#{full_name}_write_trigger", width: 1, array_size:
         }
       end
     end

data/lib/rggen/veryl/bit_field/type/wrc_wrs.rb

@@ -4,8 +4,7 @@ RgGen.define_list_item_feature(:bit_field, :type, [:wrc, :wrs]) do
   veryl do
     build do
       output :value_out, {
-        name: "o_#{full_name}",
-        width: width, array_size: array_size
+        name: "o_#{full_name}", width:, array_size:
       }
     end
 

data/lib/rggen/veryl/feature.rb

@@ -7,31 +7,31 @@ module RgGen
 
       private
 
-      def create_if_instance(_, attributes, &block)
-        InterfaceInstance.new(attributes, &block)
+      def create_if_instance(_, attributes, &)
+        InterfaceInstance.new(attributes, &)
       end
 
-      def create_port(direction, attributes, &block)
+      def create_port(direction, attributes, &)
         attributes =
-          { direction: direction }
+          { direction: }
             .merge(attributes)
-        DataObject.new(:port, attributes, &block)
+        DataObject.new(:port, attributes, &)
       end
 
-      def create_modport(_, attributes, &block)
-        Modport.new(attributes, &block)
+      def create_modport(_, attributes, &)
+        Modport.new(attributes, &)
       end
 
-      def create_param(_, attributes, &block)
-        DataObject.new(:param, attributes, &block)
+      def create_param(_, attributes, &)
+        DataObject.new(:param, attributes, &)
       end
 
-      def create_const(_, attributes, &block)
-        DataObject.new(:const, attributes, &block)
+      def create_const(_, attributes, &)
+        DataObject.new(:const, attributes, &)
       end
 
-      def create_var(_, attributes, &block)
-        DataObject.new(:var, attributes, &block)
+      def create_var(_, attributes, &)
+        DataObject.new(:var, attributes, &)
       end
 
       define_entity :input, :create_port, :port, -> { register_block }

data/lib/rggen/veryl/register/type/external.rb

@@ -5,7 +5,7 @@ RgGen.define_list_item_feature(:register, :type, :external) do
     build do
       param :strobe_width, {
         name: "#{register.name}_strobe_width".upcase,
-        type: :u32, default: configuration.byte_width
+        type: :u32, default: register_block.byte_width
       }
       modport :bus_if, {
         name: "#{register.name}_bus_if",

data/lib/rggen/veryl/register_block/protocol/native.erb

@@ -0,0 +1,18 @@
+inst u_adapter: rggen::rggen_native_adapter #(
+  ADDRESS_WIDTH:        <%= address_width %>,
+  LOCAL_ADDRESS_WIDTH:  <%= local_address_width %>,
+  BUS_WIDTH:            <%= bus_width %>,
+  STROBE_WIDTH:         <%= strobe_width %>,
+  REGISTERS:            <%= total_registers %>,
+  PRE_DECODE:           <%= pre_decode %>,
+  BASE_ADDRESS:         <%= base_address %>,
+  BYTE_SIZE:            <%= byte_size %>,
+  ERROR_STATUS:         <%= error_status %>,
+  DEFAULT_READ_DATA:    <%= default_read_data %>,
+  INSERT_SLICER:        <%= insert_slicer %>
+)(
+  i_clk:        <%= register_block.clock %>,
+  i_rst:        <%= register_block.reset %>,
+  csrbus_if:    <%= csrbus_if %>,
+  register_if:  <%= register_block.register_if %>
+);

data/lib/rggen/veryl/register_block/protocol/native.rb

@@ -0,0 +1,17 @@
+# frozen_string_literal: true
+
+RgGen.define_list_item_feature(:register_block, :protocol, :native) do
+  veryl do
+    build do
+      param :strobe_width, {
+        name: 'STROBE_WIDTH', type: :u32, default: bus_width / 8
+      }
+      modport :csrbus_if, {
+        name: 'csrbus_if',
+        interface_type: 'rggen::rggen_bus_if', modport: 'slave'
+      }
+    end
+
+    main_code :register_block, from_template: true
+  end
+end

data/lib/rggen/veryl/register_block/protocol.rb

@@ -29,7 +29,7 @@ RgGen.define_list_feature(:register_block, :protocol) do
       private
 
       def bus_width
-        configuration.bus_width
+        register_block.bus_width
       end
 
       def local_address_width
@@ -46,8 +46,8 @@ RgGen.define_list_feature(:register_block, :protocol) do
     end
 
     factory do
-      def target_feature_key(configuration, _register_block)
-        configuration.protocol
+      def target_feature_key(_configuration, register_block)
+        register_block.protocol
       end
     end
   end

data/lib/rggen/veryl/register_block/veryl_top.rb

@@ -8,7 +8,7 @@ RgGen.define_simple_feature(:register_block, :veryl_top) do
 
       interface :register_if, {
         name: 'register_if', interface_type: 'rggen::rggen_register_if',
-        param_values: param_values, array_size: [total_registers], variables: ['value']
+        param_values:, array_size: [total_registers], variables: ['value']
       }
     end
 
@@ -43,7 +43,7 @@ RgGen.define_simple_feature(:register_block, :veryl_top) do
     end
 
     def bus_width
-      configuration.bus_width
+      register_block.bus_width
     end
 
     def packages

data/lib/rggen/veryl/register_map/keyword_checker.rb

@@ -0,0 +1,35 @@
+# frozen_string_literal: true
+
+module RgGen
+  module Veryl
+    module RegisterMap
+      module KeywordChecker
+        VERYL_KEYWORDS = [
+          'always_comb', 'always_ff', 'as', 'assign', 'bit', 'break', 'case', 'clock',
+          'clock_negedge', 'clock_posedge', 'const', 'default', 'else', 'embed', 'enum',
+          'export', 'f32', 'f64', 'final', 'for', 'function', 'i32', 'i64', 'if',
+          'if_reset', 'import', 'in', 'include', 'initial', 'inout', 'input', 'inside',
+          'inst', 'interface', 'let', 'local', 'logic', 'modport', 'module', 'output',
+          'outside', 'package', 'param', 'proto', 'pub', 'ref', 'repeat', 'reset',
+          'reset_async_high', 'reset_async_low', 'reset_sync_high', 'reset_sync_low',
+          'return', 'signed', 'step', 'struct', 'switch', 'tri', 'type', 'u32', 'u64',
+          'unsafe', 'var'
+        ].freeze
+
+        def self.included(klass)
+          klass.class_eval do
+            verify(:feature, prepend: true) do
+              error_condition do
+                @name && VERYL_KEYWORDS.include?(@name)
+              end
+              message do
+                layer_name = component.layer.to_s.sub('_', ' ')
+                "veryl keyword is not allowed for #{layer_name} name: #{@name}"
+              end
+            end
+          end
+        end
+      end
+    end
+  end
+end

data/lib/rggen/veryl/register_map/name.rb

@@ -0,0 +1,10 @@
+# frozen_string_literal: true
+
+[:register_block, :register_file, :register, :bit_field].each do |layer|
+  RgGen.modify_simple_feature(layer, :name) do
+    register_map do
+      include RgGen::SystemVerilog::RegisterMap::KeywordChecker
+      include RgGen::Veryl::RegisterMap::KeywordChecker
+    end
+  end
+end

data/lib/rggen/veryl/utility.rb

@@ -5,15 +5,15 @@ module RgGen
     module Utility
       private
 
-      def local_scope(name, attributes = {}, &block)
+      def local_scope(name, attributes = {}, &)
         LocalScope
-          .new(attributes.merge(name: name), &block)
+          .new(attributes.merge(name:), &)
           .to_code
       end
 
-      def module_definition(name, attributes = {}, &block)
+      def module_definition(name, attributes = {}, &)
         ModuleDefinition
-          .new(attributes.merge(name: name), &block)
+          .new(attributes.merge(name:), &)
           .to_code
       end
 

data/lib/rggen/veryl/version.rb

@@ -2,6 +2,6 @@
 
 module RgGen
   module Veryl
-    VERSION = '0.1.0'
+    VERSION = '0.2.0'
   end
 end

data/lib/rggen/veryl.rb

@@ -1,5 +1,6 @@
 # frozen_string_literal: true
 
+require 'rggen/systemverilog/rtl'
 require_relative 'veryl/version'
 require_relative 'veryl/utility/data_object'
 require_relative 'veryl/utility/modport'
@@ -10,6 +11,7 @@ require_relative 'veryl/utility'
 require_relative 'veryl/component'
 require_relative 'veryl/feature'
 require_relative 'veryl/factories'
+require_relative 'veryl/register_map/keyword_checker'
 
 RgGen.setup_plugin :'rggen-veryl' do |plugin|
   plugin.version RgGen::Veryl::VERSION
@@ -27,6 +29,7 @@ RgGen.setup_plugin :'rggen-veryl' do |plugin|
     'veryl/register_block/protocol/apb',
     'veryl/register_block/protocol/axi4lite',
     'veryl/register_block/protocol/wishbone',
+    'veryl/register_block/protocol/native',
     'veryl/register_file/veryl_top',
     'veryl/register/veryl_top',
     'veryl/register/type',
@@ -54,4 +57,8 @@ RgGen.setup_plugin :'rggen-veryl' do |plugin|
     'veryl/bit_field/type/wo_wo1_wotrg',
     'veryl/bit_field/type/wrc_wrs'
   ]
+
+  plugin.files [
+    'veryl/register_map/name'
+  ]
 end

metadata

@@ -1,14 +1,13 @@
 --- !ruby/object:Gem::Specification
 name: rggen-veryl
 version: !ruby/object:Gem::Version
-  version: 0.1.0
+  version: 0.2.0
 platform: ruby
 authors:
 - Taichi Ishitani
-autorequire: 
 bindir: bin
 cert_chain: []
-date: 2024-11-28 00:00:00.000000000 Z
+date: 2025-01-23 00:00:00.000000000 Z
 dependencies:
 - !ruby/object:Gem::Dependency
   name: rggen-systemverilog
@@ -16,14 +15,14 @@ dependencies:
     requirements:
     - - ">="
       - !ruby/object:Gem::Version
-        version: 0.33.1
+        version: 0.34.0
   type: :runtime
   prerelease: false
   version_requirements: !ruby/object:Gem::Requirement
     requirements:
     - - ">="
       - !ruby/object:Gem::Version
-        version: 0.33.1
+        version: 0.34.0
 description: Veryl writer plugin for RgGen
 email:
 - rggen@googlegroups.com
@@ -91,10 +90,14 @@ files:
 - lib/rggen/veryl/register_block/protocol/apb.rb
 - lib/rggen/veryl/register_block/protocol/axi4lite.erb
 - lib/rggen/veryl/register_block/protocol/axi4lite.rb
+- lib/rggen/veryl/register_block/protocol/native.erb
+- lib/rggen/veryl/register_block/protocol/native.rb
 - lib/rggen/veryl/register_block/protocol/wishbone.erb
 - lib/rggen/veryl/register_block/protocol/wishbone.rb
 - lib/rggen/veryl/register_block/veryl_top.rb
 - lib/rggen/veryl/register_file/veryl_top.rb
+- lib/rggen/veryl/register_map/keyword_checker.rb
+- lib/rggen/veryl/register_map/name.rb
 - lib/rggen/veryl/utility.rb
 - lib/rggen/veryl/utility/data_object.rb
 - lib/rggen/veryl/utility/interface_instance.rb
@@ -109,9 +112,8 @@ metadata:
   bug_tracker_uri: https://github.com/rggen/rggen/issues
   mailing_list_uri: https://groups.google.com/d/forum/rggen
   rubygems_mfa_required: 'true'
-  source_code_uri: https://github.com/rggen/rggen-vhdl
+  source_code_uri: https://github.com/rggen/rggen-veryl
   wiki_uri: https://github.com/rggen/rggen/wiki
-post_install_message: 
 rdoc_options: []
 require_paths:
 - lib
@@ -119,15 +121,14 @@ required_ruby_version: !ruby/object:Gem::Requirement
   requirements:
   - - ">="
     - !ruby/object:Gem::Version
-      version: 3.0.0
+      version: '3.1'
 required_rubygems_version: !ruby/object:Gem::Requirement
   requirements:
   - - ">="
     - !ruby/object:Gem::Version
       version: '0'
 requirements: []
-rubygems_version: 3.5.16
-signing_key: 
+rubygems_version: 3.6.2
 specification_version: 4
-summary: rggen-veryl-0.1.0
+summary: rggen-veryl-0.2.0
 test_files: []