rggen-verilog 0.3.1 → 0.3.2

This diff represents the content of publicly available package versions that have been released to one of the supported registries. The information contained in this diff is provided for informational purposes only and reflects changes between package versions as they appear in their respective public registries.
checksums.yaml CHANGED
@@ -1,7 +1,7 @@
1
1
  ---
2
2
  SHA256:
3
- metadata.gz: 7071aa165eea26e8fc35de9ce6fd6a026aa5def4b29075d709f2d3db6ad74f89
4
- data.tar.gz: e805e0399138162446f3e5d3ea5b49a95b15167792acf650f142a14d9f3f53a3
3
+ metadata.gz: '06670669d48946bead954241343d1a066259235a35831b208d7f83b2609dbb23'
4
+ data.tar.gz: ccd8a5b93bcbf91d46f2c37187e4c85969f2985c4ab86d7b95b9c471c452f377
5
5
  SHA512:
6
- metadata.gz: fc56d7ab4db650083dd5f7269e29c0341095a37bf1230b3f0d469ae78eaee6f8422fe868240017fa327502d1f6e497da4aec643c5e10a9d1dceaa37e0f5dbf53
7
- data.tar.gz: e285f84c954580f58eabed0e40a709d9bf1f76e3b2f96cafc8588f0807aecd379d983e621eb9e21c80a8b8eaaf60eaaa79998aa7d3cf2b783ba8c2c28981c84f
6
+ metadata.gz: 72671fa06f46bebf4ec983f872c713a48b0b49b56582bab0a8a3779208f321cfcd2a1c9262a0600276e67f40d5946825805ca617c7f8b8810e7ed8f7a4faaf22
7
+ data.tar.gz: e61413d89d74a72316ecbb66597cab18ded435dc4819d68fcbd5a2b9f9b11caa978a85c8112ef66a5b338c26874a7aec1452413523013b5f4d323ceb1f5eecaf
@@ -60,7 +60,7 @@ RgGen.define_simple_feature(:bit_field, :verilog_top) do
60
60
  if !bit_field.initial_value_array?
61
61
  sized_initial_value
62
62
  elsif bit_field.fixed_initial_value?
63
- concat(sized_initial_values)
63
+ merged_initial_values
64
64
  else
65
65
  repeat(bit_field.sequence_size, sized_initial_value)
66
66
  end
@@ -70,11 +70,13 @@ RgGen.define_simple_feature(:bit_field, :verilog_top) do
70
70
  hex(bit_field.register_map.initial_value, bit_field.width)
71
71
  end
72
72
 
73
- def sized_initial_values
74
- bit_field
75
- .initial_values
76
- .reverse
77
- .map { |v| hex(v, bit_field.width) }
73
+ def merged_initial_values
74
+ value =
75
+ bit_field
76
+ .initial_values
77
+ .map.with_index { |v, i| v << (i * bit_field.width) }
78
+ .inject(:|)
79
+ hex(value, bit_field.width * bit_field.sequence_size)
78
80
  end
79
81
 
80
82
  def loop_size
@@ -2,6 +2,6 @@
2
2
 
3
3
  module RgGen
4
4
  module Verilog
5
- VERSION = '0.3.1'
5
+ VERSION = '0.3.2'
6
6
  end
7
7
  end
metadata CHANGED
@@ -1,14 +1,14 @@
1
1
  --- !ruby/object:Gem::Specification
2
2
  name: rggen-verilog
3
3
  version: !ruby/object:Gem::Version
4
- version: 0.3.1
4
+ version: 0.3.2
5
5
  platform: ruby
6
6
  authors:
7
7
  - Taichi Ishitani
8
8
  autorequire:
9
9
  bindir: bin
10
10
  cert_chain: []
11
- date: 2021-05-16 00:00:00.000000000 Z
11
+ date: 2021-05-21 00:00:00.000000000 Z
12
12
  dependencies:
13
13
  - !ruby/object:Gem::Dependency
14
14
  name: rggen-systemverilog
@@ -123,5 +123,5 @@ requirements: []
123
123
  rubygems_version: 3.2.3
124
124
  signing_key:
125
125
  specification_version: 4
126
- summary: rggen-verilog-0.3.1
126
+ summary: rggen-verilog-0.3.2
127
127
  test_files: []