rggen-verilog 0.3.1 → 0.3.2

checksums.yaml

@@ -1,7 +1,7 @@
 ---
 SHA256:
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-  data.tar.gz: e805e0399138162446f3e5d3ea5b49a95b15167792acf650f142a14d9f3f53a3
+  metadata.gz: '06670669d48946bead954241343d1a066259235a35831b208d7f83b2609dbb23'
+  data.tar.gz: ccd8a5b93bcbf91d46f2c37187e4c85969f2985c4ab86d7b95b9c471c452f377
 SHA512:
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+  data.tar.gz: e61413d89d74a72316ecbb66597cab18ded435dc4819d68fcbd5a2b9f9b11caa978a85c8112ef66a5b338c26874a7aec1452413523013b5f4d323ceb1f5eecaf

data/lib/rggen/verilog/bit_field/verilog_top.rb

@@ -60,7 +60,7 @@ RgGen.define_simple_feature(:bit_field, :verilog_top) do
       if !bit_field.initial_value_array?
         sized_initial_value
       elsif bit_field.fixed_initial_value?
-        concat(sized_initial_values)
+        merged_initial_values
       else
         repeat(bit_field.sequence_size, sized_initial_value)
       end
@@ -70,11 +70,13 @@ RgGen.define_simple_feature(:bit_field, :verilog_top) do
       hex(bit_field.register_map.initial_value, bit_field.width)
     end
 
-    def sized_initial_values
-      bit_field
-        .initial_values
-        .reverse
-        .map { |v| hex(v, bit_field.width) }
+    def merged_initial_values
+      value =
+        bit_field
+          .initial_values
+          .map.with_index { |v, i| v << (i * bit_field.width) }
+          .inject(:|)
+      hex(value, bit_field.width * bit_field.sequence_size)
     end
 
     def loop_size

data/lib/rggen/verilog/version.rb

@@ -2,6 +2,6 @@
 
 module RgGen
   module Verilog
-    VERSION = '0.3.1'
+    VERSION = '0.3.2'
   end
 end

metadata

@@ -1,14 +1,14 @@
 --- !ruby/object:Gem::Specification
 name: rggen-verilog
 version: !ruby/object:Gem::Version
-  version: 0.3.1
+  version: 0.3.2
 platform: ruby
 authors:
 - Taichi Ishitani
 autorequire: 
 bindir: bin
 cert_chain: []
-date: 2021-05-16 00:00:00.000000000 Z
+date: 2021-05-21 00:00:00.000000000 Z
 dependencies:
 - !ruby/object:Gem::Dependency
   name: rggen-systemverilog
@@ -123,5 +123,5 @@ requirements: []
 rubygems_version: 3.2.3
 signing_key: 
 specification_version: 4
-summary: rggen-verilog-0.3.1
+summary: rggen-verilog-0.3.2
 test_files: []