rggen-verilog 0.8.1 → 0.10.0
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- checksums.yaml +4 -4
- data/lib/rggen/verilog/rtl/register/type/external.erb +1 -0
- data/lib/rggen/verilog/rtl/register/type/external.rb +5 -1
- data/lib/rggen/verilog/rtl/register/type/rw.erb +27 -0
- data/lib/rggen/verilog/rtl/register/type/rw.rb +7 -0
- data/lib/rggen/verilog/rtl/register_block/verilog_top.rb +1 -1
- data/lib/rggen/verilog/version.rb +1 -1
- data/lib/rggen/verilog.rb +1 -0
- metadata +9 -21
checksums.yaml
CHANGED
@@ -1,7 +1,7 @@
|
|
1
1
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---
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2
2
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SHA256:
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3
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-
metadata.gz:
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4
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-
data.tar.gz:
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3
|
+
metadata.gz: ae3ef0f79a6f941f4efa341eca05fb18fea782cfdab3992e4456c764aa3ba138
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4
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+
data.tar.gz: ac2651f017ab663d7f6dd1cc652f9be843096eca7ce88641fbcef47f8fcab3d6
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5
5
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SHA512:
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6
|
-
metadata.gz:
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7
|
-
data.tar.gz:
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6
|
+
metadata.gz: d3181cf232bb8370a0be9a634d59e3f6770f4e8529b39f6b50f83cca267b7baaad5d194586deaf92b97a47a388a50d0545ef0aca81eba948be9f10008067796d
|
7
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+
data.tar.gz: 1ca0607fb3c090e49ef057e2de426ec9c4ddc91080e3f39a5b21bc27480f828be89bb1f263e8314dbe26e2e3671f5c4db2ede7deadfc2a1b12f134f75abcbe09
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@@ -3,6 +3,10 @@
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3
3
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RgGen.define_list_item_feature(:register, :type, :external) do
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4
4
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verilog_rtl do
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5
5
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build do
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6
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+
parameter :strobe_width, {
|
7
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+
name: "#{register.name}_strobe_width".upcase,
|
8
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+
default: configuration.bus_width / 8
|
9
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+
}
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6
10
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output :external_valid, {
|
7
11
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name: "o_#{register.name}_valid", width: 1
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8
12
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}
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@@ -16,7 +20,7 @@ RgGen.define_list_item_feature(:register, :type, :external) do
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|
16
20
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name: "o_#{register.name}_data", width: bus_width
|
17
21
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}
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18
22
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output :external_strobe, {
|
19
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-
name: "o_#{register.name}_strobe", width:
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23
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+
name: "o_#{register.name}_strobe", width: strobe_width
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20
24
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}
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21
25
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input :external_ready, {
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22
26
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name: "i_#{register.name}_ready", width: 1
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@@ -0,0 +1,27 @@
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1
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+
rggen_default_register #(
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2
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+
.READABLE (1),
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3
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+
.WRITABLE (1),
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4
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+
.ADDRESS_WIDTH (<%= address_width %>),
|
5
|
+
.OFFSET_ADDRESS (<%= offset_address %>),
|
6
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+
.BUS_WIDTH (<%= bus_width %>),
|
7
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+
.DATA_WIDTH (<%= width %>)
|
8
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+
) u_register (
|
9
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+
.i_clk (<%= clock %>),
|
10
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+
.i_rst_n (<%= reset %>),
|
11
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+
.i_register_valid (<%= register_valid %>),
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12
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+
.i_register_access (<%= register_access %>),
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13
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+
.i_register_address (<%= register_address %>),
|
14
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+
.i_register_write_data (<%= register_write_data %>),
|
15
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+
.i_register_strobe (<%= register_strobe %>),
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16
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+
.o_register_active (<%= register_active %>),
|
17
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+
.o_register_ready (<%= register_ready %>),
|
18
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+
.o_register_status (<%= register_status %>),
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19
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+
.o_register_read_data (<%= register_read_data %>),
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20
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+
.o_register_value (<%= register_value %>),
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21
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+
.o_bit_field_valid (<%= bit_field_valid %>),
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22
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+
.o_bit_field_read_mask (<%= bit_field_read_mask %>),
|
23
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+
.o_bit_field_write_mask (<%= bit_field_write_mask %>),
|
24
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+
.o_bit_field_write_data (<%= bit_field_write_data %>),
|
25
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+
.i_bit_field_read_data (<%= bit_field_read_data %>),
|
26
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+
.i_bit_field_value (<%= bit_field_value %>)
|
27
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+
);
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@@ -23,7 +23,7 @@ RgGen.define_simple_feature(:register_block, :verilog_top) do
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|
23
23
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name: 'w_register_write_data', width: bus_width
|
24
24
|
}
|
25
25
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wire :register_strobe, {
|
26
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-
name: 'w_register_strobe', width: bus_width
|
26
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+
name: 'w_register_strobe', width: bus_width
|
27
27
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}
|
28
28
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wire :register_active, {
|
29
29
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name: 'w_register_active', width: 1, array_size: [total_registers]
|
data/lib/rggen/verilog.rb
CHANGED
@@ -31,6 +31,7 @@ RgGen.setup_plugin :'rggen-verilog' do |plugin|
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|
31
31
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'verilog/rtl/register/type',
|
32
32
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'verilog/rtl/register/type/external',
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33
33
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'verilog/rtl/register/type/indirect',
|
34
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+
'verilog/rtl/register/type/rw',
|
34
35
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'verilog/rtl/bit_field/verilog_top',
|
35
36
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'verilog/rtl/bit_field/type',
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36
37
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'verilog/rtl/bit_field/type/custom',
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metadata
CHANGED
@@ -1,14 +1,14 @@
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1
1
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--- !ruby/object:Gem::Specification
|
2
2
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name: rggen-verilog
|
3
3
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version: !ruby/object:Gem::Version
|
4
|
-
version: 0.
|
4
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+
version: 0.10.0
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5
5
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platform: ruby
|
6
6
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authors:
|
7
7
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- Taichi Ishitani
|
8
8
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autorequire:
|
9
9
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bindir: bin
|
10
10
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cert_chain: []
|
11
|
-
date: 2023-
|
11
|
+
date: 2023-12-28 00:00:00.000000000 Z
|
12
12
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dependencies:
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13
13
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- !ruby/object:Gem::Dependency
|
14
14
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name: rggen-systemverilog
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@@ -16,28 +16,14 @@ dependencies:
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16
16
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requirements:
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17
17
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- - ">="
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18
18
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- !ruby/object:Gem::Version
|
19
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-
version: 0.
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19
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+
version: 0.32.0
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20
20
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type: :runtime
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21
21
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prerelease: false
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22
22
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version_requirements: !ruby/object:Gem::Requirement
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23
23
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requirements:
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24
24
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- - ">="
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25
25
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- !ruby/object:Gem::Version
|
26
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-
version: 0.
|
27
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-
- !ruby/object:Gem::Dependency
|
28
|
-
name: bundler
|
29
|
-
requirement: !ruby/object:Gem::Requirement
|
30
|
-
requirements:
|
31
|
-
- - ">="
|
32
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-
- !ruby/object:Gem::Version
|
33
|
-
version: '0'
|
34
|
-
type: :development
|
35
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-
prerelease: false
|
36
|
-
version_requirements: !ruby/object:Gem::Requirement
|
37
|
-
requirements:
|
38
|
-
- - ">="
|
39
|
-
- !ruby/object:Gem::Version
|
40
|
-
version: '0'
|
26
|
+
version: 0.32.0
|
41
27
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description: Verilog write plugin for RgGen
|
42
28
|
email:
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43
29
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- rggen@googlegroups.com
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@@ -94,6 +80,8 @@ files:
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|
94
80
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- lib/rggen/verilog/rtl/register/type/external.rb
|
95
81
|
- lib/rggen/verilog/rtl/register/type/indirect.erb
|
96
82
|
- lib/rggen/verilog/rtl/register/type/indirect.rb
|
83
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+
- lib/rggen/verilog/rtl/register/type/rw.erb
|
84
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+
- lib/rggen/verilog/rtl/register/type/rw.rb
|
97
85
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- lib/rggen/verilog/rtl/register/verilog_top.rb
|
98
86
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- lib/rggen/verilog/rtl/register_block/protocol.rb
|
99
87
|
- lib/rggen/verilog/rtl/register_block/protocol/apb.erb
|
@@ -130,15 +118,15 @@ required_ruby_version: !ruby/object:Gem::Requirement
|
|
130
118
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requirements:
|
131
119
|
- - ">="
|
132
120
|
- !ruby/object:Gem::Version
|
133
|
-
version: '
|
121
|
+
version: '3.0'
|
134
122
|
required_rubygems_version: !ruby/object:Gem::Requirement
|
135
123
|
requirements:
|
136
124
|
- - ">="
|
137
125
|
- !ruby/object:Gem::Version
|
138
126
|
version: '0'
|
139
127
|
requirements: []
|
140
|
-
rubygems_version: 3.
|
128
|
+
rubygems_version: 3.5.3
|
141
129
|
signing_key:
|
142
130
|
specification_version: 4
|
143
|
-
summary: rggen-verilog-0.
|
131
|
+
summary: rggen-verilog-0.10.0
|
144
132
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test_files: []
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