rggen-verilog 0.8.0 → 0.9.0

checksums.yaml

@@ -1,7 +1,7 @@
 ---
 SHA256:
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-  data.tar.gz: 4b245b8815da6fca8ea8bc4abf4c67c83f56c1534693c24851a767e22175e471
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+  data.tar.gz: fa8243ba5f46b51121594dbd982971b3bc253832de69a00229260d23df5dc446
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data/lib/rggen/verilog/rtl/bit_field/type.rb

@@ -22,8 +22,17 @@ RgGen.define_list_feature(:bit_field, :type) do
       end
 
       def initial_value
-        index = bit_field.initial_value_array? && bit_field.local_index || 0
-        macro_call('rggen_slice', [bit_field.initial_value, width, index])
+        if multiple_initial_values?
+          index = bit_field.local_index
+          total_bits = width * bit_field.sequence_size
+          macro_call('rggen_slice', [bit_field.initial_value, total_bits, width, index])
+        else
+          bit_field.initial_value
+        end
+      end
+
+      def multiple_initial_values?
+        bit_field.initial_value_array? && bit_field.sequence_size > 1
       end
 
       def clock

data/lib/rggen/verilog/rtl/register/type/external.erb

@@ -1,8 +1,9 @@
 rggen_external_register #(
   .ADDRESS_WIDTH  (<%= address_width %>),
   .BUS_WIDTH      (<%= bus_width %>),
+  .STROBE_WIDTH   (<%= strobe_width %>),
   .START_ADDRESS  (<%= start_address %>),
-  .END_ADDRESS    (<%= end_address %>)
+  .BYTE_SIZE      (<%= byte_size %>)
 ) u_register (
   .i_clk                  (<%= clock %>),
   .i_rst_n                (<%= reset %>),

data/lib/rggen/verilog/rtl/register/type/external.rb

@@ -3,6 +3,10 @@
 RgGen.define_list_item_feature(:register, :type, :external) do
   verilog_rtl do
     build do
+      parameter :strobe_width, {
+        name: "#{register.name}_strobe_width".upcase,
+        default: configuration.bus_width / 8
+      }
       output :external_valid, {
         name: "o_#{register.name}_valid", width: 1
       }
@@ -16,7 +20,7 @@ RgGen.define_list_item_feature(:register, :type, :external) do
         name: "o_#{register.name}_data", width: bus_width
       }
       output :external_strobe, {
-        name: "o_#{register.name}_strobe", width: bus_width / 8
+        name: "o_#{register.name}_strobe", width: strobe_width
       }
       input :external_ready, {
         name: "i_#{register.name}_ready", width: 1
@@ -37,8 +41,8 @@ RgGen.define_list_item_feature(:register, :type, :external) do
       hex(register.address_range.begin, address_width)
     end
 
-    def end_address
-      hex(register.address_range.last, address_width)
+    def byte_size
+      register.total_byte_size
     end
   end
 end

data/lib/rggen/verilog/rtl/register/type/rw.erb

@@ -0,0 +1,27 @@
+rggen_default_register #(
+  .READABLE       (1),
+  .WRITABLE       (1),
+  .ADDRESS_WIDTH  (<%= address_width %>),
+  .OFFSET_ADDRESS (<%= offset_address %>),
+  .BUS_WIDTH      (<%= bus_width %>),
+  .DATA_WIDTH     (<%= width %>)
+) u_register (
+  .i_clk                  (<%= clock %>),
+  .i_rst_n                (<%= reset %>),
+  .i_register_valid       (<%= register_valid %>),
+  .i_register_access      (<%= register_access %>),
+  .i_register_address     (<%= register_address %>),
+  .i_register_write_data  (<%= register_write_data %>),
+  .i_register_strobe      (<%= register_strobe %>),
+  .o_register_active      (<%= register_active %>),
+  .o_register_ready       (<%= register_ready %>),
+  .o_register_status      (<%= register_status %>),
+  .o_register_read_data   (<%= register_read_data %>),
+  .o_register_value       (<%= register_value %>),
+  .o_bit_field_valid      (<%= bit_field_valid %>),
+  .o_bit_field_read_mask  (<%= bit_field_read_mask %>),
+  .o_bit_field_write_mask (<%= bit_field_write_mask %>),
+  .o_bit_field_write_data (<%= bit_field_write_data %>),
+  .i_bit_field_read_data  (<%= bit_field_read_data %>),
+  .i_bit_field_value      (<%= bit_field_value %>)
+);

data/lib/rggen/verilog/rtl/register/type/rw.rb

@@ -0,0 +1,7 @@
+# frozen_string_literal: true
+
+RgGen.define_list_item_feature(:register, :type, :rw) do
+  verilog_rtl do
+    main_code :register, from_template: true
+  end
+end

data/lib/rggen/verilog/rtl/register_block/verilog_top.rb

@@ -23,7 +23,7 @@ RgGen.define_simple_feature(:register_block, :verilog_top) do
         name: 'w_register_write_data', width: bus_width
       }
       wire :register_strobe, {
-        name: 'w_register_strobe', width: bus_width / 8
+        name: 'w_register_strobe', width: bus_width
       }
       wire :register_active, {
         name: 'w_register_active', width: 1, array_size: [total_registers]

data/lib/rggen/verilog/utility.rb

@@ -16,6 +16,10 @@ module RgGen
       def fill_1(width)
         "{#{width}{1'b1}}"
       end
+
+      def width_cast(expression, _width)
+        expression
+      end
     end
   end
 end

data/lib/rggen/verilog/version.rb

@@ -2,6 +2,6 @@
 
 module RgGen
   module Verilog
-    VERSION = '0.8.0'
+    VERSION = '0.9.0'
   end
 end

data/lib/rggen/verilog.rb

@@ -31,6 +31,7 @@ RgGen.setup_plugin :'rggen-verilog' do |plugin|
     'verilog/rtl/register/type',
     'verilog/rtl/register/type/external',
     'verilog/rtl/register/type/indirect',
+    'verilog/rtl/register/type/rw',
     'verilog/rtl/bit_field/verilog_top',
     'verilog/rtl/bit_field/type',
     'verilog/rtl/bit_field/type/custom',

metadata

@@ -1,14 +1,14 @@
 --- !ruby/object:Gem::Specification
 name: rggen-verilog
 version: !ruby/object:Gem::Version
-  version: 0.8.0
+  version: 0.9.0
 platform: ruby
 authors:
 - Taichi Ishitani
 autorequire: 
 bindir: bin
 cert_chain: []
-date: 2023-04-28 00:00:00.000000000 Z
+date: 2023-09-12 00:00:00.000000000 Z
 dependencies:
 - !ruby/object:Gem::Dependency
   name: rggen-systemverilog
@@ -16,14 +16,14 @@ dependencies:
     requirements:
     - - ">="
       - !ruby/object:Gem::Version
-        version: 0.30.0
+        version: 0.31.0
   type: :runtime
   prerelease: false
   version_requirements: !ruby/object:Gem::Requirement
     requirements:
     - - ">="
       - !ruby/object:Gem::Version
-        version: 0.30.0
+        version: 0.31.0
 - !ruby/object:Gem::Dependency
   name: bundler
   requirement: !ruby/object:Gem::Requirement
@@ -94,6 +94,8 @@ files:
 - lib/rggen/verilog/rtl/register/type/external.rb
 - lib/rggen/verilog/rtl/register/type/indirect.erb
 - lib/rggen/verilog/rtl/register/type/indirect.rb
+- lib/rggen/verilog/rtl/register/type/rw.erb
+- lib/rggen/verilog/rtl/register/type/rw.rb
 - lib/rggen/verilog/rtl/register/verilog_top.rb
 - lib/rggen/verilog/rtl/register_block/protocol.rb
 - lib/rggen/verilog/rtl/register_block/protocol/apb.erb
@@ -137,8 +139,8 @@ required_rubygems_version: !ruby/object:Gem::Requirement
     - !ruby/object:Gem::Version
       version: '0'
 requirements: []
-rubygems_version: 3.4.10
+rubygems_version: 3.4.17
 signing_key: 
 specification_version: 4
-summary: rggen-verilog-0.8.0
+summary: rggen-verilog-0.9.0
 test_files: []