rggen-verilog 0.7.0 → 0.8.1

checksums.yaml

@@ -1,7 +1,7 @@
 ---
 SHA256:
-  metadata.gz: e74fcb34c71a5d9cdfa75d2ce6ee033ef65550e5cf3a225c2357d5e9beb2905f
-  data.tar.gz: 7a109f65cbaddd4abe24ee50e0cefde064e1b4f8036294d66e8ab5d770e5a67a
+  metadata.gz: 501905cb54813b90fc9080c475f4c1b14c341ede3538e10628e9e30d0cb39c24
+  data.tar.gz: bfe15d77b852c68ba19b8a4f17e8f9cf961e218c21c294d752268add08262a95
 SHA512:
-  metadata.gz: 8b55c739e1a881baee014a5bc73521ba6066eb13a2a38e72b016e4debfaab4e4b6417e80ce11643e3350fda393a6f77d469c0d7758c77876bcb12bf4266ed66f
-  data.tar.gz: c507b06be435d72c0c22633b9bbd756427dfa921ed50d78ff6dfe8de64aca7b623be5d114ff1047d4ebb448628ea300bbcaf24319ef0655a5519d6f2bb8a75e4
+  metadata.gz: '024865e81e0e44340b062633e411e4bd1b5db96e67d72e10aeacce980610f0d6a0cdd2db273dcf33e1fd4fca9a96a8a43a23bf7722b4e4b097853a80d403e7c2'
+  data.tar.gz: 2bee917871bf9e33cc311aa84fe7bc39e6a8cfff18ec9ee7e0e970f01a5efbfde923aa2271e257032d5af5a271a9b12507afde8c65ff8cee8a3d39fc917d769f

data/lib/rggen/verilog/rtl/bit_field/type.rb

@@ -22,8 +22,17 @@ RgGen.define_list_feature(:bit_field, :type) do
       end
 
       def initial_value
-        index = bit_field.initial_value_array? && bit_field.local_index || 0
-        macro_call('rggen_slice', [bit_field.initial_value, width, index])
+        if multiple_initial_values?
+          index = bit_field.local_index
+          total_bits = width * bit_field.sequence_size
+          macro_call('rggen_slice', [bit_field.initial_value, total_bits, width, index])
+        else
+          bit_field.initial_value
+        end
+      end
+
+      def multiple_initial_values?
+        bit_field.initial_value_array? && bit_field.sequence_size > 1
       end
 
       def clock

data/lib/rggen/verilog/rtl/register/type/default.erb

@@ -4,8 +4,7 @@ rggen_default_register #(
   .ADDRESS_WIDTH  (<%= address_width %>),
   .OFFSET_ADDRESS (<%= offset_address %>),
   .BUS_WIDTH      (<%= bus_width %>),
-  .DATA_WIDTH     (<%= width %>),
-  .REGISTER_INDEX (<%= register_index %>)
+  .DATA_WIDTH     (<%= width %>)
 ) u_register (
   .i_clk                  (<%= clock %>),
   .i_rst_n                (<%= reset %>),

data/lib/rggen/verilog/rtl/register/type/external.erb

@@ -2,7 +2,7 @@ rggen_external_register #(
   .ADDRESS_WIDTH  (<%= address_width %>),
   .BUS_WIDTH      (<%= bus_width %>),
   .START_ADDRESS  (<%= start_address %>),
-  .END_ADDRESS    (<%= end_address %>)
+  .BYTE_SIZE      (<%= byte_size %>)
 ) u_register (
   .i_clk                  (<%= clock %>),
   .i_rst_n                (<%= reset %>),

data/lib/rggen/verilog/rtl/register/type/external.rb

@@ -34,12 +34,11 @@ RgGen.define_list_item_feature(:register, :type, :external) do
     private
 
     def start_address
-      hex(register.offset_address, address_width)
+      hex(register.address_range.begin, address_width)
     end
 
-    def end_address
-      address = register.offset_address + register.byte_size - 1
-      hex(address, address_width)
+    def byte_size
+      register.total_byte_size
     end
   end
 end

data/lib/rggen/verilog/rtl/register_block/protocol/apb.erb

@@ -7,7 +7,8 @@ rggen_apb_adapter #(
   .BASE_ADDRESS         (<%= base_address %>),
   .BYTE_SIZE            (<%= byte_size %>),
   .ERROR_STATUS         (<%= error_status %>),
-  .DEFAULT_READ_DATA    (<%= default_read_data %>)
+  .DEFAULT_READ_DATA    (<%= default_read_data %>),
+  .INSERT_SLICER        (<%= insert_slicer %>)
 ) u_adapter (
   .i_clk                  (<%= register_block.clock %>),
   .i_rst_n                (<%= register_block.reset %>),

data/lib/rggen/verilog/rtl/register_block/protocol/axi4lite.erb

@@ -9,6 +9,7 @@ rggen_axi4lite_adapter #(
   .BYTE_SIZE            (<%= byte_size %>),
   .ERROR_STATUS         (<%= error_status %>),
   .DEFAULT_READ_DATA    (<%= default_read_data %>),
+  .INSERT_SLICER        (<%= insert_slicer %>),
   .WRITE_FIRST          (<%= write_first %>)
 ) u_adapter (
   .i_clk                  (<%= register_block.clock %>),

data/lib/rggen/verilog/rtl/register_block/protocol/wishbone.erb

@@ -8,6 +8,7 @@ rggen_wishbone_adapter #(
   .BYTE_SIZE            (<%= byte_size %>),
   .ERROR_STATUS         (<%= error_status %>),
   .DEFAULT_READ_DATA    (<%= default_read_data %>),
+  .INSERT_SLICER        (<%= insert_slicer %>),
   .USE_STALL            (<%= use_stall %>)
 ) u_adapter (
   .i_clk                  (<%= register_block.clock %>),

data/lib/rggen/verilog/rtl/register_block/protocol.rb

@@ -21,6 +21,9 @@ RgGen.define_list_feature(:register_block, :protocol) do
         parameter :default_read_data, {
           name: 'DEFAULT_READ_DATA', width: bus_width, default: 0
         }
+        parameter :insert_slicer, {
+          name: 'INSERT_SLICER', default: 0
+        }
       end
 
       private

data/lib/rggen/verilog/rtl_header/bit_field/verilog_rtl_header.rb

@@ -6,6 +6,7 @@ RgGen.define_simple_feature(:bit_field, :verilog_rtl_header) do
       define_macro("#{full_name}_bit_width", width)
       define_macro("#{full_name}_bit_mask", mask)
       define_offset_macro
+      define_label_macros
     end
 
     private
@@ -27,5 +28,13 @@ RgGen.define_simple_feature(:bit_field, :verilog_rtl_header) do
         define_macro("#{full_name}_bit_offset", bit_field.lsb)
       end
     end
+
+    def define_label_macros
+      bit_field.labels.each do |label|
+        name = "#{full_name}_#{label.name}"
+        value = hex(label.value, bit_field.width)
+        define_macro(name, value)
+      end
+    end
   end
 end

data/lib/rggen/verilog/rtl_header/register/verilog_rtl_header.rb

@@ -16,7 +16,7 @@ RgGen.define_simple_feature(:register, :verilog_rtl_header) do
     end
 
     def byte_size
-      register.byte_size(hierarchical: true)
+      register.total_byte_size(hierarchical: true)
     end
 
     def array?

data/lib/rggen/verilog/utility.rb

@@ -16,6 +16,10 @@ module RgGen
       def fill_1(width)
         "{#{width}{1'b1}}"
       end
+
+      def width_cast(expression, _width)
+        expression
+      end
     end
   end
 end

data/lib/rggen/verilog/version.rb

@@ -2,6 +2,6 @@
 
 module RgGen
   module Verilog
-    VERSION = '0.7.0'
+    VERSION = '0.8.1'
   end
 end

metadata

@@ -1,14 +1,14 @@
 --- !ruby/object:Gem::Specification
 name: rggen-verilog
 version: !ruby/object:Gem::Version
-  version: 0.7.0
+  version: 0.8.1
 platform: ruby
 authors:
 - Taichi Ishitani
 autorequire: 
 bindir: bin
 cert_chain: []
-date: 2023-01-02 00:00:00.000000000 Z
+date: 2023-06-09 00:00:00.000000000 Z
 dependencies:
 - !ruby/object:Gem::Dependency
   name: rggen-systemverilog
@@ -16,14 +16,14 @@ dependencies:
     requirements:
     - - ">="
       - !ruby/object:Gem::Version
-        version: 0.29.0
+        version: 0.30.1
   type: :runtime
   prerelease: false
   version_requirements: !ruby/object:Gem::Requirement
     requirements:
     - - ">="
       - !ruby/object:Gem::Version
-        version: 0.29.0
+        version: 0.30.1
 - !ruby/object:Gem::Dependency
   name: bundler
   requirement: !ruby/object:Gem::Requirement
@@ -137,8 +137,8 @@ required_rubygems_version: !ruby/object:Gem::Requirement
     - !ruby/object:Gem::Version
       version: '0'
 requirements: []
-rubygems_version: 3.4.1
+rubygems_version: 3.4.10
 signing_key: 
 specification_version: 4
-summary: rggen-verilog-0.7.0
+summary: rggen-verilog-0.8.1
 test_files: []