rggen-verilog 0.5.0 → 0.7.0

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@@ -1,7 +1,7 @@
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data/LICENSE

@@ -1,6 +1,6 @@
 The MIT License (MIT)
 
-Copyright (c) 2020-2022 Taichi Ishitani
+Copyright (c) 2020-2023 Taichi Ishitani
 
 Permission is hereby granted, free of charge, to any person obtaining a copy
 of this software and associated documentation files (the "Software"), to deal

data/README.md

@@ -68,7 +68,7 @@ Feedbacks, bus reports, questions and etc. are welcome! You can post them bu usi
 
 ## Copyright & License
 
-Copyright © 2020-2022 Taichi Ishitani. RgGen::Verilog is licensed under the [MIT License](https://opensource.org/licenses/MIT), see [LICENSE](LICENSE) for futher details.
+Copyright © 2020-2023 Taichi Ishitani. RgGen::Verilog is licensed under the [MIT License](https://opensource.org/licenses/MIT), see [LICENSE](LICENSE) for futher details.
 
 ## Code of Conduct
 

data/lib/rggen/verilog/rtl/bit_field/type/custom.erb

@@ -0,0 +1,30 @@
+rggen_bit_field #(
+  .WIDTH              (<%= width %>),
+  .INITIAL_VALUE      (<%= initial_value %>),
+  .SW_READ_ACTION     (<%= sw_read_action %>),
+  .SW_WRITE_ACTION    (<%= sw_write_action %>),
+  .SW_WRITE_ONCE      (<%= write_once %>),
+  .STORAGE            (<%= storage %>),
+  .EXTERNAL_READ_DATA (<%= external_read_data %>),
+  .TRIGGER            (<%= trigger %>)
+) u_bit_field (
+  .i_clk              (<%= clock %>),
+  .i_rst_n            (<%= reset %>),
+  .i_sw_valid         (<%= bit_field_valid %>),
+  .i_sw_read_mask     (<%= bit_field_read_mask %>),
+  .i_sw_write_enable  (1'b1),
+  .i_sw_write_mask    (<%= bit_field_write_mask %>),
+  .i_sw_write_data    (<%= bit_field_write_data %>),
+  .o_sw_read_data     (<%= bit_field_read_data %>),
+  .o_sw_value         (<%= bit_field_value %>),
+  .o_write_trigger    (<%= output_port(:write_trigger) %>),
+  .o_read_trigger     (<%= output_port(:read_trigger) %>),
+  .i_hw_write_enable  (<%= input_port(:hw_write_enable, "1'b0") %>),
+  .i_hw_write_data    (<%= input_port(:hw_write_data) %>),
+  .i_hw_set           (<%= input_port(:hw_set) %>),
+  .i_hw_clear         (<%= input_port(:hw_clear) %>),
+  .i_value            (<%= input_port(:value_in) %>),
+  .i_mask             (<%= fill_1(width) %>),
+  .o_value            (<%= output_port(:value_out) %>),
+  .o_value_unmasked   ()
+);

data/lib/rggen/verilog/rtl/bit_field/type/custom.rb

@@ -0,0 +1,113 @@
+# frozen_string_literal: true
+
+RgGen.define_list_item_feature(:bit_field, :type, :custom) do
+  verilog_rtl do
+    build do
+      if external_read_data?
+        input :value_in, {
+          name: "i_#{full_name}", width: width, array_size: array_size
+        }
+      else
+        output :value_out, {
+          name: "o_#{full_name}", width: width, array_size: array_size
+        }
+      end
+      if bit_field.hw_write?
+        input :hw_write_enable, {
+          name: "i_#{full_name}_hw_write_enable", width: 1, array_size: array_size
+        }
+        input :hw_write_data, {
+          name: "i_#{full_name}_hw_write_data", width: width, array_size: array_size
+        }
+      end
+      if bit_field.hw_set?
+        input :hw_set, {
+          name: "i_#{full_name}_hw_set", width: width, array_size: array_size
+        }
+      end
+      if bit_field.hw_clear?
+        input :hw_clear, {
+          name: "i_#{full_name}_hw_clear", width: width, array_size: array_size
+        }
+      end
+      if bit_field.write_trigger?
+        output :write_trigger, {
+          name: "o_#{full_name}_write_trigger", width: 1, array_size: array_size
+        }
+      end
+      if bit_field.read_trigger?
+        output :read_trigger, {
+          name: "o_#{full_name}_read_trigger", width: 1, array_size: array_size
+        }
+      end
+    end
+
+    main_code :bit_field, from_template: true
+
+    private
+
+    def external_read_data?
+      !bit_field.sw_update? && !bit_field.hw_update?
+    end
+
+    def initial_value
+      external_read_data? && fill_0(width) || super
+    end
+
+    def sw_read_action
+      {
+        none: '`RGGEN_READ_NONE',
+        default: '`RGGEN_READ_DEFAULT',
+        set: '`RGGEN_READ_SET',
+        clear: '`RGGEN_READ_CLEAR'
+      }[bit_field.sw_read]
+    end
+
+    def sw_write_action
+      {
+        none: '`RGGEN_WRITE_NONE',
+        default: '`RGGEN_WRITE_DEFAULT',
+        clear_0: '`RGGEN_WRITE_0_CLEAR',
+        clear_1: '`RGGEN_WRITE_1_CLEAR',
+        clear: '`RGGEN_WRITE_CLEAR',
+        set_0: '`RGGEN_WRITE_0_SET',
+        set_1: '`RGGEN_WRITE_1_SET',
+        set: '`RGGEN_WRITE_SET',
+        toggle_0: '`RGGEN_WRITE_0_TOGGLE',
+        toggle_1: '`RGGEN_WRITE_1_TOGGLE'
+      }[bit_field.sw_write]
+    end
+
+    def write_once
+      bit_field.sw_write_once? && 1 || 0
+    end
+
+    def storage
+      external_read_data? && 0 || 1
+    end
+
+    def external_read_data
+      external_read_data? && 1 || 0
+    end
+
+    def trigger?
+      bit_field.write_trigger? || bit_field.read_trigger?
+    end
+
+    def trigger
+      trigger? && 1 || 0
+    end
+
+    def input_port(name, default = nil)
+      find_port(name, default || fill_0(width))
+    end
+
+    def output_port(name)
+      find_port(name, '')
+    end
+
+    def find_port(name, default_value)
+      respond_to?(name) && __send__(name)[loop_variables] || default_value
+    end
+  end
+end

data/lib/rggen/verilog/{bit_field → rtl/bit_field}/type/rc_w0c_w1c_wc_woc.rb

@@ -1,7 +1,7 @@
 # frozen_string_literal: true
 
 RgGen.define_list_item_feature(:bit_field, :type, [:rc, :w0c, :w1c, :wc, :woc]) do
-  verilog do
+  verilog_rtl do
     build do
       input :set, {
         name: "i_#{full_name}_set", width: width, array_size: array_size

data/lib/rggen/verilog/{bit_field → rtl/bit_field}/type/ro_rotrg.rb

@@ -1,7 +1,7 @@
 # frozen_string_literal: true
 
 RgGen.define_list_item_feature(:bit_field, :type, [:ro, :rotrg]) do
-  verilog do
+  verilog_rtl do
     build do
       unless bit_field.reference?
         input :value_in, {

data/lib/rggen/verilog/{bit_field → rtl/bit_field}/type/rof.rb

@@ -1,7 +1,7 @@
 # frozen_string_literal: true
 
 RgGen.define_list_item_feature(:bit_field, :type, :rof) do
-  verilog do
+  verilog_rtl do
     main_code :bit_field, from_template: true
   end
 end

data/lib/rggen/verilog/rtl/bit_field/type/rol.erb

@@ -0,0 +1,25 @@
+rggen_bit_field #(
+  .WIDTH            (<%= width %>),
+  .INITIAL_VALUE    (<%= initial_value %>),
+  .SW_WRITE_ACTION  (`RGGEN_WRITE_NONE)
+) u_bit_field (
+  .i_clk              (<%= clock %>),
+  .i_rst_n            (<%= reset %>),
+  .i_sw_valid         (<%= bit_field_valid %>),
+  .i_sw_read_mask     (<%= bit_field_read_mask %>),
+  .i_sw_write_enable  (1'b1),
+  .i_sw_write_mask    (<%= bit_field_write_mask %>),
+  .i_sw_write_data    (<%= bit_field_write_data %>),
+  .o_sw_read_data     (<%= bit_field_read_data %>),
+  .o_sw_value         (<%= bit_field_value %>),
+  .o_write_trigger    (),
+  .o_read_trigger     (),
+  .i_hw_write_enable  (<%= latch_signal %>),
+  .i_hw_write_data    (<%= value_in[loop_variables] %>),
+  .i_hw_set           (<%= fill_0(width) %>),
+  .i_hw_clear         (<%= fill_0(width) %>),
+  .i_value            (<%= fill_0(width) %>),
+  .i_mask             (<%= fill_1(width) %>),
+  .o_value            (<%= value_out[loop_variables] %>),
+  .o_value_unmasked   ()
+);

data/lib/rggen/verilog/rtl/bit_field/type/rol.rb

@@ -0,0 +1,25 @@
+# frozen_string_literal: true
+
+RgGen.define_list_item_feature(:bit_field, :type, :rol) do
+  verilog_rtl do
+    build do
+      unless bit_field.reference?
+        input :latch, {
+          name: "i_#{full_name}_latch", width: 1, array_size: array_size
+        }
+      end
+      input :value_in, {
+        name: "i_#{full_name}", width: width, array_size: array_size
+      }
+      output :value_out, {
+        name: "o_#{full_name}", width: width, array_size: array_size
+      }
+    end
+
+    main_code :bit_field, from_template: true
+
+    def latch_signal
+      reference_bit_field || latch[loop_variables]
+    end
+  end
+end

data/lib/rggen/verilog/{bit_field → rtl/bit_field}/type/row0trg_row1trg.rb

@@ -1,7 +1,7 @@
 # frozen_string_literal: true
 
 RgGen.define_list_item_feature(:bit_field, :type, [:row0trg, :row1trg]) do
-  verilog do
+  verilog_rtl do
     build do
       unless bit_field.reference?
         input :value_in, {

data/lib/rggen/verilog/{bit_field → rtl/bit_field}/type/rowo_rowotrg.rb

@@ -1,7 +1,7 @@
 # frozen_string_literal: true
 
 RgGen.define_list_item_feature(:bit_field, :type, [:rowo, :rowotrg]) do
-  verilog do
+  verilog_rtl do
     build do
       output :value_out, {
         name: "o_#{full_name}", width: width, array_size: array_size

data/lib/rggen/verilog/{bit_field → rtl/bit_field}/type/rs_w0s_w1s_ws_wos.rb

@@ -1,7 +1,7 @@
 # frozen_string_literal: true
 
 RgGen.define_list_item_feature(:bit_field, :type, [:rs, :w0s, :w1s, :ws, :wos]) do
-  verilog do
+  verilog_rtl do
     build do
       input :clear, {
         name: "i_#{full_name}_clear", width: width, array_size: array_size

data/lib/rggen/verilog/{bit_field → rtl/bit_field}/type/rw_rwtrg_w1.rb

@@ -1,7 +1,7 @@
 # frozen_string_literal: true
 
 RgGen.define_list_item_feature(:bit_field, :type, [:rw, :rwtrg, :w1]) do
-  verilog do
+  verilog_rtl do
     build do
       output :value_out, {
         name: "o_#{full_name}", width: width, array_size: array_size

data/lib/rggen/verilog/{bit_field → rtl/bit_field}/type/rwc.rb

@@ -1,7 +1,7 @@
 # frozen_string_literal: true
 
 RgGen.define_list_item_feature(:bit_field, :type, :rwc) do
-  verilog do
+  verilog_rtl do
     build do
       unless bit_field.reference?
         input :clear, {

data/lib/rggen/verilog/{bit_field → rtl/bit_field}/type/rwe_rwl.rb

@@ -1,7 +1,7 @@
 # frozen_string_literal: true
 
 RgGen.define_list_item_feature(:bit_field, :type, [:rwe, :rwl]) do
-  verilog do
+  verilog_rtl do
     build do
       unless bit_field.reference?
         input :control, {

data/lib/rggen/verilog/{bit_field → rtl/bit_field}/type/rws.rb

@@ -1,7 +1,7 @@
 # frozen_string_literal: true
 
 RgGen.define_list_item_feature(:bit_field, :type, :rws) do
-  verilog do
+  verilog_rtl do
     build do
       unless bit_field.reference?
         input :set, {

data/lib/rggen/verilog/{bit_field → rtl/bit_field}/type/w0crs_w0src_w1crs_w1src_wcrs_wsrc.rb

@@ -3,7 +3,7 @@
 RgGen.define_list_item_feature(
   :bit_field, :type, [:w0crs, :w0src, :w1crs, :w1src, :wcrs, :wsrc]
 ) do
-  verilog do
+  verilog_rtl do
     build do
       output :value_out, {
         name: "o_#{full_name}", width: width, array_size: array_size
@@ -19,7 +19,7 @@ RgGen.define_list_item_feature(
     end
 
     def read_set?
-      [:w0crs, :w1crs, :wcrs].include?(bit_field.type)
+      [:w0crs, :w1crs, :wcrs].any? { |type| bit_field.type == type }
     end
 
     def write_action

data/lib/rggen/verilog/{bit_field → rtl/bit_field}/type/w0t_w1t.rb

@@ -1,7 +1,7 @@
 # frozen_string_literal: true
 
 RgGen.define_list_item_feature(:bit_field, :type, [:w0t, :w1t]) do
-  verilog do
+  verilog_rtl do
     build do
       output :value_out, {
         name: "o_#{full_name}", width: width, array_size: array_size

data/lib/rggen/verilog/{bit_field → rtl/bit_field}/type/w0trg_w1trg.rb

@@ -1,7 +1,7 @@
 # frozen_string_literal: true
 
 RgGen.define_list_item_feature(:bit_field, :type, [:w0trg, :w1trg]) do
-  verilog do
+  verilog_rtl do
     build do
       output :trigger, {
         name: "o_#{full_name}_trigger", width: width, array_size: array_size

data/lib/rggen/verilog/{bit_field → rtl/bit_field}/type/wo_wo1_wotrg.rb

@@ -1,7 +1,7 @@
 # frozen_string_literal: true
 
 RgGen.define_list_item_feature(:bit_field, :type, [:wo, :wo1, :wotrg]) do
-  verilog do
+  verilog_rtl do
     build do
       output :value_out, {
         name: "o_#{full_name}", width: width, array_size: array_size

data/lib/rggen/verilog/{bit_field → rtl/bit_field}/type/wrc_wrs.rb

@@ -1,7 +1,7 @@
 # frozen_string_literal: true
 
 RgGen.define_list_item_feature(:bit_field, :type, [:wrc, :wrs]) do
-  verilog do
+  verilog_rtl do
     build do
       output :value_out, {
         name: "o_#{full_name}", width: width, array_size: array_size

data/lib/rggen/verilog/{bit_field → rtl/bit_field}/type.rb

@@ -1,7 +1,7 @@
 # frozen_string_literal: true
 
 RgGen.define_list_feature(:bit_field, :type) do
-  verilog do
+  verilog_rtl do
     base_feature do
       private
 

data/lib/rggen/verilog/{bit_field → rtl/bit_field}/verilog_top.rb

@@ -1,7 +1,7 @@
 # frozen_string_literal: true
 
 RgGen.define_simple_feature(:bit_field, :verilog_top) do
-  verilog do
+  verilog_rtl do
     include RgGen::SystemVerilog::RTL::BitFieldIndex
 
     export :initial_value

data/lib/rggen/verilog/rtl/component.rb

@@ -0,0 +1,9 @@
+# frozen_string_literal: true
+
+module RgGen
+  module Verilog
+    module RTL
+      Component = SystemVerilog::Common::Component
+    end
+  end
+end

data/lib/rggen/verilog/rtl/feature.rb

@@ -0,0 +1,37 @@
+# frozen_string_literal: true
+
+module RgGen
+  module Verilog
+    module RTL
+      class Feature < SystemVerilog::RTL::Feature
+        include Utility
+
+        private
+
+        def create_variable(data_type, attributes, &block)
+          attributes = attributes.merge(array_format: :serialized)
+          super
+        end
+
+        def create_port(direction, attributes, &block)
+          attributes =
+            attributes
+              .except(:data_type)
+              .merge(direction: direction, array_format: :serialized)
+          DataObject.new(:argument, attributes, &block)
+        end
+
+        def create_parameter(parameter_type, attributes, &block)
+          attributes = attributes.merge(array_format: :serialized)
+          super
+        end
+
+        define_entity :wire, :create_variable, :variable, -> { component }
+
+        undef_method :interface
+        undef_method :interface_port
+        undef_method :localparam
+      end
+    end
+  end
+end

data/lib/rggen/verilog/{register → rtl/register}/type/external.rb

@@ -1,7 +1,7 @@
 # frozen_string_literal: true
 
 RgGen.define_list_item_feature(:register, :type, :external) do
-  verilog do
+  verilog_rtl do
     build do
       output :external_valid, {
         name: "o_#{register.name}_valid", width: 1

data/lib/rggen/verilog/{register → rtl/register}/type/indirect.rb

@@ -1,7 +1,7 @@
 # frozen_string_literal: true
 
 RgGen.define_list_item_feature(:register, :type, :indirect) do
-  verilog do
+  verilog_rtl do
     include RgGen::SystemVerilog::RTL::IndirectIndex
 
     build do

data/lib/rggen/verilog/{register → rtl/register}/type.rb

@@ -1,7 +1,7 @@
 # frozen_string_literal: true
 
 RgGen.define_list_feature(:register, :type) do
-  verilog do
+  verilog_rtl do
     base_feature do
       include RgGen::SystemVerilog::RTL::RegisterType
 

data/lib/rggen/verilog/{register → rtl/register}/verilog_top.rb

@@ -1,7 +1,7 @@
 # frozen_string_literal: true
 
 RgGen.define_simple_feature(:register, :verilog_top) do
-  verilog do
+  verilog_rtl do
     include RgGen::SystemVerilog::RTL::RegisterIndex
 
     build do

data/lib/rggen/verilog/{register_block → rtl/register_block}/protocol/apb.rb

@@ -1,7 +1,7 @@
 # frozen_string_literal: true
 
 RgGen.define_list_item_feature(:register_block, :protocol, :apb) do
-  verilog do
+  verilog_rtl do
     build do
       input :psel, {
         name: 'i_psel', width: 1

data/lib/rggen/verilog/{register_block → rtl/register_block}/protocol/axi4lite.rb

@@ -1,7 +1,7 @@
 # frozen_string_literal: true
 
 RgGen.define_list_item_feature(:register_block, :protocol, :axi4lite) do
-  verilog do
+  verilog_rtl do
     build do
       parameter :id_width, {
         name: 'ID_WIDTH', default: 0

data/lib/rggen/verilog/{register_block → rtl/register_block}/protocol/wishbone.rb

@@ -1,7 +1,7 @@
 # frozen_string_literal: true
 
 RgGen.define_list_item_feature(:register_block, :protocol, :wishbone) do
-  verilog do
+  verilog_rtl do
     build do
       parameter :use_stall, {
         name: 'USE_STALL', default: 1

data/lib/rggen/verilog/{register_block → rtl/register_block}/protocol.rb

@@ -1,7 +1,7 @@
 # frozen_string_literal: true
 
 RgGen.define_list_feature(:register_block, :protocol) do
-  verilog do
+  verilog_rtl do
     shared_context.feature_registry(registry)
 
     base_feature do

data/lib/rggen/verilog/{register_block → rtl/register_block}/verilog_top.rb

@@ -1,7 +1,7 @@
 # frozen_string_literal: true
 
 RgGen.define_simple_feature(:register_block, :verilog_top) do
-  verilog do
+  verilog_rtl do
     build do
       input :clock, {
         name: 'i_clk', width: 1
@@ -90,7 +90,7 @@ RgGen.define_simple_feature(:register_block, :verilog_top) do
     def ports
       register_block
         .declarations[:port]
-        .yield_self(&method(:sort_port_declarations))
+        .then(&method(:sort_port_declarations))
     end
 
     def sort_port_declarations(declarations)

data/lib/rggen/verilog/{register_file → rtl/register_file}/verilog_top.rb

@@ -1,7 +1,7 @@
 # frozen_string_literal: true
 
 RgGen.define_simple_feature(:register_file, :verilog_top) do
-  verilog do
+  verilog_rtl do
     include RgGen::SystemVerilog::RTL::RegisterIndex
 
     main_code :register_file do

data/lib/rggen/verilog/rtl_header/bit_field/verilog_rtl_header.rb

@@ -0,0 +1,31 @@
+# frozen_string_literal: true
+
+RgGen.define_simple_feature(:bit_field, :verilog_rtl_header) do
+  verilog_rtl_header do
+    build do
+      define_macro("#{full_name}_bit_width", width)
+      define_macro("#{full_name}_bit_mask", mask)
+      define_offset_macro
+    end
+
+    private
+
+    def width
+      bit_field.width
+    end
+
+    def mask
+      hex((1 << width) - 1, width)
+    end
+
+    def define_offset_macro
+      if bit_field.sequential?
+        bit_field.sequence_size.times do |i|
+          define_macro("#{full_name}_bit_offset_#{i}", bit_field.lsb(i))
+        end
+      else
+        define_macro("#{full_name}_bit_offset", bit_field.lsb)
+      end
+    end
+  end
+end

data/lib/rggen/verilog/rtl_header/component.rb

@@ -0,0 +1,13 @@
+# frozen_string_literal: true
+
+module RgGen
+  module Verilog
+    module RTLHeader
+      class Component < SystemVerilog::Common::Component
+        def macro_definitions
+          [*@children, *@features.values].flat_map(&:macro_definitions)
+        end
+      end
+    end
+  end
+end

data/lib/rggen/verilog/rtl_header/feature.rb

@@ -0,0 +1,26 @@
+# frozen_string_literal: true
+
+module RgGen
+  module Verilog
+    module RTLHeader
+      class Feature < SystemVerilog::RTL::Feature
+        include Utility
+
+        def macro_definitions
+          @macro_definitions ||= []
+        end
+
+        private
+
+        def define_macro(name, value)
+          macro_definitions <<
+            Core::Utility::CodeUtility::MacroDefinition.new(name.upcase, value)
+        end
+
+        def full_name(separator = '_')
+          [register_block.name, component.full_name(separator)].join(separator)
+        end
+      end
+    end
+  end
+end

data/lib/rggen/verilog/rtl_header/register/verilog_rtl_header.rb

@@ -0,0 +1,62 @@
+# frozen_string_literal: true
+
+RgGen.define_simple_feature(:register, :verilog_rtl_header) do
+  verilog_rtl_header do
+    build do
+      define_macro("#{full_name}_byte_width", byte_width)
+      define_macro("#{full_name}_byte_size", byte_size)
+      define_array_macros if array?
+      define_offset_address_macros
+    end
+
+    private
+
+    def byte_width
+      register.byte_width
+    end
+
+    def byte_size
+      register.byte_size(hierarchical: true)
+    end
+
+    def array?
+      register.array?(hierarchical: true)
+    end
+
+    def array_size
+      register.array_size(hierarchical: true)
+    end
+
+    def define_array_macros
+      size_list = array_size
+      define_macro("#{full_name}_array_dimension", size_list.size)
+      size_list.each_with_index do |size, i|
+        define_macro("#{full_name}_array_size_#{i}", size)
+      end
+    end
+
+    def define_offset_address_macros
+      if array?
+        address_list.zip(array_suffix) do |address, suffix|
+          define_macro("#{full_name}_byte_offset_#{suffix}", address)
+        end
+      else
+        define_macro("#{full_name}_byte_offset", address_list.first)
+      end
+    end
+
+    def address_list
+      width = register_block.local_address_width
+      register
+        .expanded_offset_addresses
+        .map { |address| hex(address, width) }
+    end
+
+    def array_suffix
+      array_size
+        .map { |size| (0...size).to_a }
+        .then { |list| list.first.product(*list[1..]) }
+        .map { |list| list.join('_') }
+    end
+  end
+end

data/lib/rggen/verilog/rtl_header/register_block/verilog_rtl_header.rb

@@ -0,0 +1,10 @@
+# frozen_string_literal: true
+
+RgGen.define_simple_feature(:register_block, :verilog_rtl_header) do
+  verilog_rtl_header do
+    write_file '<%= register_block.name %>.vh' do |f|
+      f.include_guard
+      f.macro_definitions register_block.macro_definitions
+    end
+  end
+end

data/lib/rggen/verilog/version.rb

@@ -2,6 +2,6 @@
 
 module RgGen
   module Verilog
-    VERSION = '0.5.0'
+    VERSION = '0.7.0'
   end
 end

data/lib/rggen/verilog.rb

@@ -4,47 +4,64 @@ require 'rggen/systemverilog/rtl'
 require_relative 'verilog/version'
 require_relative 'verilog/utility/local_scope'
 require_relative 'verilog/utility'
-require_relative 'verilog/component'
-require_relative 'verilog/feature'
+require_relative 'verilog/rtl/component'
+require_relative 'verilog/rtl/feature'
+require_relative 'verilog/rtl_header/component'
+require_relative 'verilog/rtl_header/feature'
 require_relative 'verilog/factories'
 
 RgGen.setup_plugin :'rggen-verilog' do |plugin|
   plugin.version RgGen::Verilog::VERSION
 
-  plugin.register_component :verilog do
-    component RgGen::Verilog::Component,
+  plugin.register_component :verilog_rtl do
+    component RgGen::Verilog::RTL::Component,
               RgGen::Verilog::ComponentFactory
-    feature RgGen::Verilog::Feature,
+    feature RgGen::Verilog::RTL::Feature,
             RgGen::Verilog::FeatureFactory
   end
 
   plugin.files [
-    'verilog/register_block/verilog_top',
-    'verilog/register_block/protocol',
-    'verilog/register_block/protocol/apb',
-    'verilog/register_block/protocol/axi4lite',
-    'verilog/register_block/protocol/wishbone',
-    'verilog/register_file/verilog_top',
-    'verilog/register/verilog_top',
-    'verilog/register/type',
-    'verilog/register/type/external',
-    'verilog/register/type/indirect',
-    'verilog/bit_field/verilog_top',
-    'verilog/bit_field/type',
-    'verilog/bit_field/type/rc_w0c_w1c_wc_woc',
-    'verilog/bit_field/type/ro_rotrg',
-    'verilog/bit_field/type/rof',
-    'verilog/bit_field/type/row0trg_row1trg',
-    'verilog/bit_field/type/rowo_rowotrg',
-    'verilog/bit_field/type/rs_w0s_w1s_ws_wos',
-    'verilog/bit_field/type/rw_rwtrg_w1',
-    'verilog/bit_field/type/rwc',
-    'verilog/bit_field/type/rwe_rwl',
-    'verilog/bit_field/type/rws',
-    'verilog/bit_field/type/w0crs_w0src_w1crs_w1src_wcrs_wsrc',
-    'verilog/bit_field/type/w0t_w1t',
-    'verilog/bit_field/type/w0trg_w1trg',
-    'verilog/bit_field/type/wo_wo1_wotrg',
-    'verilog/bit_field/type/wrc_wrs'
+    'verilog/rtl/register_block/verilog_top',
+    'verilog/rtl/register_block/protocol',
+    'verilog/rtl/register_block/protocol/apb',
+    'verilog/rtl/register_block/protocol/axi4lite',
+    'verilog/rtl/register_block/protocol/wishbone',
+    'verilog/rtl/register_file/verilog_top',
+    'verilog/rtl/register/verilog_top',
+    'verilog/rtl/register/type',
+    'verilog/rtl/register/type/external',
+    'verilog/rtl/register/type/indirect',
+    'verilog/rtl/bit_field/verilog_top',
+    'verilog/rtl/bit_field/type',
+    'verilog/rtl/bit_field/type/custom',
+    'verilog/rtl/bit_field/type/rc_w0c_w1c_wc_woc',
+    'verilog/rtl/bit_field/type/ro_rotrg',
+    'verilog/rtl/bit_field/type/rof',
+    'verilog/rtl/bit_field/type/rol',
+    'verilog/rtl/bit_field/type/row0trg_row1trg',
+    'verilog/rtl/bit_field/type/rowo_rowotrg',
+    'verilog/rtl/bit_field/type/rs_w0s_w1s_ws_wos',
+    'verilog/rtl/bit_field/type/rw_rwtrg_w1',
+    'verilog/rtl/bit_field/type/rwc',
+    'verilog/rtl/bit_field/type/rwe_rwl',
+    'verilog/rtl/bit_field/type/rws',
+    'verilog/rtl/bit_field/type/w0crs_w0src_w1crs_w1src_wcrs_wsrc',
+    'verilog/rtl/bit_field/type/w0t_w1t',
+    'verilog/rtl/bit_field/type/w0trg_w1trg',
+    'verilog/rtl/bit_field/type/wo_wo1_wotrg',
+    'verilog/rtl/bit_field/type/wrc_wrs'
+  ]
+
+  plugin.register_component :verilog_rtl_header do
+    component RgGen::Verilog::RTLHeader::Component,
+              RgGen::Verilog::ComponentFactory
+    feature RgGen::Verilog::RTLHeader::Feature,
+            RgGen::Verilog::FeatureFactory
+  end
+
+  plugin.files [
+    'verilog/rtl_header/bit_field/verilog_rtl_header',
+    'verilog/rtl_header/register/verilog_rtl_header',
+    'verilog/rtl_header/register_block/verilog_rtl_header'
   ]
 end

metadata

@@ -1,14 +1,14 @@
 --- !ruby/object:Gem::Specification
 name: rggen-verilog
 version: !ruby/object:Gem::Version
-  version: 0.5.0
+  version: 0.7.0
 platform: ruby
 authors:
 - Taichi Ishitani
 autorequire: 
 bindir: bin
 cert_chain: []
-date: 2022-07-05 00:00:00.000000000 Z
+date: 2023-01-02 00:00:00.000000000 Z
 dependencies:
 - !ruby/object:Gem::Dependency
   name: rggen-systemverilog
@@ -16,14 +16,14 @@ dependencies:
     requirements:
     - - ">="
       - !ruby/object:Gem::Version
-        version: 0.27.0
+        version: 0.29.0
   type: :runtime
   prerelease: false
   version_requirements: !ruby/object:Gem::Requirement
     requirements:
     - - ">="
       - !ruby/object:Gem::Version
-        version: 0.27.0
+        version: 0.29.0
 - !ruby/object:Gem::Dependency
   name: bundler
   requirement: !ruby/object:Gem::Requirement
@@ -49,58 +49,67 @@ files:
 - LICENSE
 - README.md
 - lib/rggen/verilog.rb
-- lib/rggen/verilog/bit_field/type.rb
-- lib/rggen/verilog/bit_field/type/rc_w0c_w1c_wc_woc.erb
-- lib/rggen/verilog/bit_field/type/rc_w0c_w1c_wc_woc.rb
-- lib/rggen/verilog/bit_field/type/ro_rotrg.erb
-- lib/rggen/verilog/bit_field/type/ro_rotrg.rb
-- lib/rggen/verilog/bit_field/type/rof.erb
-- lib/rggen/verilog/bit_field/type/rof.rb
-- lib/rggen/verilog/bit_field/type/row0trg_row1trg.erb
-- lib/rggen/verilog/bit_field/type/row0trg_row1trg.rb
-- lib/rggen/verilog/bit_field/type/rowo_rowotrg.erb
-- lib/rggen/verilog/bit_field/type/rowo_rowotrg.rb
-- lib/rggen/verilog/bit_field/type/rs_w0s_w1s_ws_wos.erb
-- lib/rggen/verilog/bit_field/type/rs_w0s_w1s_ws_wos.rb
-- lib/rggen/verilog/bit_field/type/rw_rwtrg_w1.erb
-- lib/rggen/verilog/bit_field/type/rw_rwtrg_w1.rb
-- lib/rggen/verilog/bit_field/type/rwc.erb
-- lib/rggen/verilog/bit_field/type/rwc.rb
-- lib/rggen/verilog/bit_field/type/rwe_rwl.erb
-- lib/rggen/verilog/bit_field/type/rwe_rwl.rb
-- lib/rggen/verilog/bit_field/type/rws.erb
-- lib/rggen/verilog/bit_field/type/rws.rb
-- lib/rggen/verilog/bit_field/type/w0crs_w0src_w1crs_w1src_wcrs_wsrc.erb
-- lib/rggen/verilog/bit_field/type/w0crs_w0src_w1crs_w1src_wcrs_wsrc.rb
-- lib/rggen/verilog/bit_field/type/w0t_w1t.erb
-- lib/rggen/verilog/bit_field/type/w0t_w1t.rb
-- lib/rggen/verilog/bit_field/type/w0trg_w1trg.erb
-- lib/rggen/verilog/bit_field/type/w0trg_w1trg.rb
-- lib/rggen/verilog/bit_field/type/wo_wo1_wotrg.erb
-- lib/rggen/verilog/bit_field/type/wo_wo1_wotrg.rb
-- lib/rggen/verilog/bit_field/type/wrc_wrs.erb
-- lib/rggen/verilog/bit_field/type/wrc_wrs.rb
-- lib/rggen/verilog/bit_field/verilog_top.rb
-- lib/rggen/verilog/component.rb
 - lib/rggen/verilog/factories.rb
-- lib/rggen/verilog/feature.rb
-- lib/rggen/verilog/register/type.rb
-- lib/rggen/verilog/register/type/default.erb
-- lib/rggen/verilog/register/type/external.erb
-- lib/rggen/verilog/register/type/external.rb
-- lib/rggen/verilog/register/type/indirect.erb
-- lib/rggen/verilog/register/type/indirect.rb
-- lib/rggen/verilog/register/verilog_top.rb
-- lib/rggen/verilog/register_block/protocol.rb
-- lib/rggen/verilog/register_block/protocol/apb.erb
-- lib/rggen/verilog/register_block/protocol/apb.rb
-- lib/rggen/verilog/register_block/protocol/axi4lite.erb
-- lib/rggen/verilog/register_block/protocol/axi4lite.rb
-- lib/rggen/verilog/register_block/protocol/wishbone.erb
-- lib/rggen/verilog/register_block/protocol/wishbone.rb
-- lib/rggen/verilog/register_block/verilog_macros.erb
-- lib/rggen/verilog/register_block/verilog_top.rb
-- lib/rggen/verilog/register_file/verilog_top.rb
+- lib/rggen/verilog/rtl/bit_field/type.rb
+- lib/rggen/verilog/rtl/bit_field/type/custom.erb
+- lib/rggen/verilog/rtl/bit_field/type/custom.rb
+- lib/rggen/verilog/rtl/bit_field/type/rc_w0c_w1c_wc_woc.erb
+- lib/rggen/verilog/rtl/bit_field/type/rc_w0c_w1c_wc_woc.rb
+- lib/rggen/verilog/rtl/bit_field/type/ro_rotrg.erb
+- lib/rggen/verilog/rtl/bit_field/type/ro_rotrg.rb
+- lib/rggen/verilog/rtl/bit_field/type/rof.erb
+- lib/rggen/verilog/rtl/bit_field/type/rof.rb
+- lib/rggen/verilog/rtl/bit_field/type/rol.erb
+- lib/rggen/verilog/rtl/bit_field/type/rol.rb
+- lib/rggen/verilog/rtl/bit_field/type/row0trg_row1trg.erb
+- lib/rggen/verilog/rtl/bit_field/type/row0trg_row1trg.rb
+- lib/rggen/verilog/rtl/bit_field/type/rowo_rowotrg.erb
+- lib/rggen/verilog/rtl/bit_field/type/rowo_rowotrg.rb
+- lib/rggen/verilog/rtl/bit_field/type/rs_w0s_w1s_ws_wos.erb
+- lib/rggen/verilog/rtl/bit_field/type/rs_w0s_w1s_ws_wos.rb
+- lib/rggen/verilog/rtl/bit_field/type/rw_rwtrg_w1.erb
+- lib/rggen/verilog/rtl/bit_field/type/rw_rwtrg_w1.rb
+- lib/rggen/verilog/rtl/bit_field/type/rwc.erb
+- lib/rggen/verilog/rtl/bit_field/type/rwc.rb
+- lib/rggen/verilog/rtl/bit_field/type/rwe_rwl.erb
+- lib/rggen/verilog/rtl/bit_field/type/rwe_rwl.rb
+- lib/rggen/verilog/rtl/bit_field/type/rws.erb
+- lib/rggen/verilog/rtl/bit_field/type/rws.rb
+- lib/rggen/verilog/rtl/bit_field/type/w0crs_w0src_w1crs_w1src_wcrs_wsrc.erb
+- lib/rggen/verilog/rtl/bit_field/type/w0crs_w0src_w1crs_w1src_wcrs_wsrc.rb
+- lib/rggen/verilog/rtl/bit_field/type/w0t_w1t.erb
+- lib/rggen/verilog/rtl/bit_field/type/w0t_w1t.rb
+- lib/rggen/verilog/rtl/bit_field/type/w0trg_w1trg.erb
+- lib/rggen/verilog/rtl/bit_field/type/w0trg_w1trg.rb
+- lib/rggen/verilog/rtl/bit_field/type/wo_wo1_wotrg.erb
+- lib/rggen/verilog/rtl/bit_field/type/wo_wo1_wotrg.rb
+- lib/rggen/verilog/rtl/bit_field/type/wrc_wrs.erb
+- lib/rggen/verilog/rtl/bit_field/type/wrc_wrs.rb
+- lib/rggen/verilog/rtl/bit_field/verilog_top.rb
+- lib/rggen/verilog/rtl/component.rb
+- lib/rggen/verilog/rtl/feature.rb
+- lib/rggen/verilog/rtl/register/type.rb
+- lib/rggen/verilog/rtl/register/type/default.erb
+- lib/rggen/verilog/rtl/register/type/external.erb
+- lib/rggen/verilog/rtl/register/type/external.rb
+- lib/rggen/verilog/rtl/register/type/indirect.erb
+- lib/rggen/verilog/rtl/register/type/indirect.rb
+- lib/rggen/verilog/rtl/register/verilog_top.rb
+- lib/rggen/verilog/rtl/register_block/protocol.rb
+- lib/rggen/verilog/rtl/register_block/protocol/apb.erb
+- lib/rggen/verilog/rtl/register_block/protocol/apb.rb
+- lib/rggen/verilog/rtl/register_block/protocol/axi4lite.erb
+- lib/rggen/verilog/rtl/register_block/protocol/axi4lite.rb
+- lib/rggen/verilog/rtl/register_block/protocol/wishbone.erb
+- lib/rggen/verilog/rtl/register_block/protocol/wishbone.rb
+- lib/rggen/verilog/rtl/register_block/verilog_macros.erb
+- lib/rggen/verilog/rtl/register_block/verilog_top.rb
+- lib/rggen/verilog/rtl/register_file/verilog_top.rb
+- lib/rggen/verilog/rtl_header/bit_field/verilog_rtl_header.rb
+- lib/rggen/verilog/rtl_header/component.rb
+- lib/rggen/verilog/rtl_header/feature.rb
+- lib/rggen/verilog/rtl_header/register/verilog_rtl_header.rb
+- lib/rggen/verilog/rtl_header/register_block/verilog_rtl_header.rb
 - lib/rggen/verilog/utility.rb
 - lib/rggen/verilog/utility/local_scope.rb
 - lib/rggen/verilog/version.rb
@@ -121,15 +130,15 @@ required_ruby_version: !ruby/object:Gem::Requirement
   requirements:
   - - ">="
     - !ruby/object:Gem::Version
-      version: '2.6'
+      version: '2.7'
 required_rubygems_version: !ruby/object:Gem::Requirement
   requirements:
   - - ">="
     - !ruby/object:Gem::Version
       version: '0'
 requirements: []
-rubygems_version: 3.3.3
+rubygems_version: 3.4.1
 signing_key: 
 specification_version: 4
-summary: rggen-verilog-0.5.0
+summary: rggen-verilog-0.7.0
 test_files: []

data/lib/rggen/verilog/component.rb

@@ -1,7 +0,0 @@
-# frozen_string_literal: true
-
-module RgGen
-  module Verilog
-    Component = SystemVerilog::Common::Component
-  end
-end

data/lib/rggen/verilog/feature.rb

@@ -1,35 +0,0 @@
-# frozen_string_literal: true
-
-module RgGen
-  module Verilog
-    class Feature < SystemVerilog::RTL::Feature
-      include Utility
-
-      private
-
-      def create_variable(data_type, attributes, &block)
-        attributes = attributes.merge(array_format: :serialized)
-        super
-      end
-
-      def create_port(direction, attributes, &block)
-        attributes =
-          attributes
-            .except(:data_type)
-            .merge(direction: direction, array_format: :serialized)
-        DataObject.new(:argument, attributes, &block)
-      end
-
-      def create_parameter(parameter_type, attributes, &block)
-        attributes = attributes.merge(array_format: :serialized)
-        super
-      end
-
-      define_entity :wire, :create_variable, :variable, -> { component }
-
-      undef_method :interface
-      undef_method :interface_port
-      undef_method :localparam
-    end
-  end
-end