rggen-verilog 0.5.0 → 0.6.0

checksums.yaml

@@ -1,7 +1,7 @@
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+  data.tar.gz: 5a61bd68a631f85e8aaa9ab666a72ac366c1d979479638cad454a6b28ff5de36892c02f1fb37d902cb6aab9a75f606050538c9a5e1001db53e2179e3f0236fe7

data/lib/rggen/verilog/bit_field/type/custom.erb

@@ -0,0 +1,30 @@
+rggen_bit_field #(
+  .WIDTH              (<%= width %>),
+  .INITIAL_VALUE      (<%= initial_value %>),
+  .SW_READ_ACTION     (<%= sw_read_action %>),
+  .SW_WRITE_ACTION    (<%= sw_write_action %>),
+  .SW_WRITE_ONCE      (<%= write_once %>),
+  .STORAGE            (<%= storage %>),
+  .EXTERNAL_READ_DATA (<%= external_read_data %>),
+  .TRIGGER            (<%= trigger %>)
+) u_bit_field (
+  .i_clk              (<%= clock %>),
+  .i_rst_n            (<%= reset %>),
+  .i_sw_valid         (<%= bit_field_valid %>),
+  .i_sw_read_mask     (<%= bit_field_read_mask %>),
+  .i_sw_write_enable  (1'b1),
+  .i_sw_write_mask    (<%= bit_field_write_mask %>),
+  .i_sw_write_data    (<%= bit_field_write_data %>),
+  .o_sw_read_data     (<%= bit_field_read_data %>),
+  .o_sw_value         (<%= bit_field_value %>),
+  .o_write_trigger    (<%= output_port(:write_trigger) %>),
+  .o_read_trigger     (<%= output_port(:read_trigger) %>),
+  .i_hw_write_enable  (<%= input_port(:hw_write_enable, "1'b0") %>),
+  .i_hw_write_data    (<%= input_port(:hw_write_data) %>),
+  .i_hw_set           (<%= input_port(:hw_set) %>),
+  .i_hw_clear         (<%= input_port(:hw_clear) %>),
+  .i_value            (<%= input_port(:value_in) %>),
+  .i_mask             (<%= fill_1(width) %>),
+  .o_value            (<%= output_port(:value_out) %>),
+  .o_value_unmasked   ()
+);

data/lib/rggen/verilog/bit_field/type/custom.rb

@@ -0,0 +1,113 @@
+# frozen_string_literal: true
+
+RgGen.define_list_item_feature(:bit_field, :type, :custom) do
+  verilog do
+    build do
+      if external_read_data?
+        input :value_in, {
+          name: "i_#{full_name}", width: width, array_size: array_size
+        }
+      else
+        output :value_out, {
+          name: "o_#{full_name}", width: width, array_size: array_size
+        }
+      end
+      if bit_field.hw_write?
+        input :hw_write_enable, {
+          name: "i_#{full_name}_hw_write_enable", width: 1, array_size: array_size
+        }
+        input :hw_write_data, {
+          name: "i_#{full_name}_hw_write_data", width: width, array_size: array_size
+        }
+      end
+      if bit_field.hw_set?
+        input :hw_set, {
+          name: "i_#{full_name}_hw_set", width: width, array_size: array_size
+        }
+      end
+      if bit_field.hw_clear?
+        input :hw_clear, {
+          name: "i_#{full_name}_hw_clear", width: width, array_size: array_size
+        }
+      end
+      if bit_field.write_trigger?
+        output :write_trigger, {
+          name: "o_#{full_name}_write_trigger", width: 1, array_size: array_size
+        }
+      end
+      if bit_field.read_trigger?
+        output :read_trigger, {
+          name: "o_#{full_name}_read_trigger", width: 1, array_size: array_size
+        }
+      end
+    end
+
+    main_code :bit_field, from_template: true
+
+    private
+
+    def external_read_data?
+      !bit_field.sw_update? && !bit_field.hw_update?
+    end
+
+    def initial_value
+      external_read_data? && fill_0(width) || super
+    end
+
+    def sw_read_action
+      {
+        none: '`RGGEN_READ_NONE',
+        default: '`RGGEN_READ_DEFAULT',
+        set: '`RGGEN_READ_SET',
+        clear: '`RGGEN_READ_CLEAR'
+      }[bit_field.sw_read]
+    end
+
+    def sw_write_action
+      {
+        none: '`RGGEN_WRITE_NONE',
+        default: '`RGGEN_WRITE_DEFAULT',
+        clear_0: '`RGGEN_WRITE_0_CLEAR',
+        clear_1: '`RGGEN_WRITE_1_CLEAR',
+        clear: '`RGGEN_WRITE_CLEAR',
+        set_0: '`RGGEN_WRITE_0_SET',
+        set_1: '`RGGEN_WRITE_1_SET',
+        set: '`RGGEN_WRITE_SET',
+        toggle_0: '`RGGEN_WRITE_0_TOGGLE',
+        toggle_1: '`RGGEN_WRITE_1_TOGGLE'
+      }[bit_field.sw_write]
+    end
+
+    def write_once
+      bit_field.sw_write_once? && 1 || 0
+    end
+
+    def storage
+      external_read_data? && 0 || 1
+    end
+
+    def external_read_data
+      external_read_data? && 1 || 0
+    end
+
+    def trigger?
+      bit_field.write_trigger? || bit_field.read_trigger?
+    end
+
+    def trigger
+      trigger? && 1 || 0
+    end
+
+    def input_port(name, default = nil)
+      find_port(name, default || fill_0(width))
+    end
+
+    def output_port(name)
+      find_port(name, '')
+    end
+
+    def find_port(name, default_value)
+      respond_to?(name) && __send__(name)[loop_variables] || default_value
+    end
+  end
+end

data/lib/rggen/verilog/bit_field/type/rol.erb

@@ -0,0 +1,25 @@
+rggen_bit_field #(
+  .WIDTH            (<%= width %>),
+  .INITIAL_VALUE    (<%= initial_value %>),
+  .SW_WRITE_ACTION  (`RGGEN_WRITE_NONE)
+) u_bit_field (
+  .i_clk              (<%= clock %>),
+  .i_rst_n            (<%= reset %>),
+  .i_sw_valid         (<%= bit_field_valid %>),
+  .i_sw_read_mask     (<%= bit_field_read_mask %>),
+  .i_sw_write_enable  (1'b1),
+  .i_sw_write_mask    (<%= bit_field_write_mask %>),
+  .i_sw_write_data    (<%= bit_field_write_data %>),
+  .o_sw_read_data     (<%= bit_field_read_data %>),
+  .o_sw_value         (<%= bit_field_value %>),
+  .o_write_trigger    (),
+  .o_read_trigger     (),
+  .i_hw_write_enable  (<%= latch_signal %>),
+  .i_hw_write_data    (<%= value_in[loop_variables] %>),
+  .i_hw_set           (<%= fill_0(width) %>),
+  .i_hw_clear         (<%= fill_0(width) %>),
+  .i_value            (<%= fill_0(width) %>),
+  .i_mask             (<%= fill_1(width) %>),
+  .o_value            (<%= value_out[loop_variables] %>),
+  .o_value_unmasked   ()
+);

data/lib/rggen/verilog/bit_field/type/rol.rb

@@ -0,0 +1,25 @@
+# frozen_string_literal: true
+
+RgGen.define_list_item_feature(:bit_field, :type, :rol) do
+  verilog do
+    build do
+      unless bit_field.reference?
+        input :latch, {
+          name: "i_#{full_name}_latch", width: 1, array_size: array_size
+        }
+      end
+      input :value_in, {
+        name: "i_#{full_name}", width: width, array_size: array_size
+      }
+      output :value_out, {
+        name: "o_#{full_name}", width: width, array_size: array_size
+      }
+    end
+
+    main_code :bit_field, from_template: true
+
+    def latch_signal
+      reference_bit_field || latch[loop_variables]
+    end
+  end
+end

data/lib/rggen/verilog/bit_field/type/w0crs_w0src_w1crs_w1src_wcrs_wsrc.rb

@@ -19,7 +19,7 @@ RgGen.define_list_item_feature(
     end
 
     def read_set?
-      [:w0crs, :w1crs, :wcrs].include?(bit_field.type)
+      [:w0crs, :w1crs, :wcrs].any? { |type| bit_field.type == type }
     end
 
     def write_action

data/lib/rggen/verilog/register_block/verilog_top.rb

@@ -90,7 +90,7 @@ RgGen.define_simple_feature(:register_block, :verilog_top) do
     def ports
       register_block
         .declarations[:port]
-        .yield_self(&method(:sort_port_declarations))
+        .then(&method(:sort_port_declarations))
     end
 
     def sort_port_declarations(declarations)

data/lib/rggen/verilog/version.rb

@@ -2,6 +2,6 @@
 
 module RgGen
   module Verilog
-    VERSION = '0.5.0'
+    VERSION = '0.6.0'
   end
 end

data/lib/rggen/verilog.rb

@@ -31,9 +31,11 @@ RgGen.setup_plugin :'rggen-verilog' do |plugin|
     'verilog/register/type/indirect',
     'verilog/bit_field/verilog_top',
     'verilog/bit_field/type',
+    'verilog/bit_field/type/custom',
     'verilog/bit_field/type/rc_w0c_w1c_wc_woc',
     'verilog/bit_field/type/ro_rotrg',
     'verilog/bit_field/type/rof',
+    'verilog/bit_field/type/rol',
     'verilog/bit_field/type/row0trg_row1trg',
     'verilog/bit_field/type/rowo_rowotrg',
     'verilog/bit_field/type/rs_w0s_w1s_ws_wos',

metadata

@@ -1,14 +1,14 @@
 --- !ruby/object:Gem::Specification
 name: rggen-verilog
 version: !ruby/object:Gem::Version
-  version: 0.5.0
+  version: 0.6.0
 platform: ruby
 authors:
 - Taichi Ishitani
 autorequire: 
 bindir: bin
 cert_chain: []
-date: 2022-07-05 00:00:00.000000000 Z
+date: 2022-10-10 00:00:00.000000000 Z
 dependencies:
 - !ruby/object:Gem::Dependency
   name: rggen-systemverilog
@@ -16,14 +16,14 @@ dependencies:
     requirements:
     - - ">="
       - !ruby/object:Gem::Version
-        version: 0.27.0
+        version: 0.28.0
   type: :runtime
   prerelease: false
   version_requirements: !ruby/object:Gem::Requirement
     requirements:
     - - ">="
       - !ruby/object:Gem::Version
-        version: 0.27.0
+        version: 0.28.0
 - !ruby/object:Gem::Dependency
   name: bundler
   requirement: !ruby/object:Gem::Requirement
@@ -50,12 +50,16 @@ files:
 - README.md
 - lib/rggen/verilog.rb
 - lib/rggen/verilog/bit_field/type.rb
+- lib/rggen/verilog/bit_field/type/custom.erb
+- lib/rggen/verilog/bit_field/type/custom.rb
 - lib/rggen/verilog/bit_field/type/rc_w0c_w1c_wc_woc.erb
 - lib/rggen/verilog/bit_field/type/rc_w0c_w1c_wc_woc.rb
 - lib/rggen/verilog/bit_field/type/ro_rotrg.erb
 - lib/rggen/verilog/bit_field/type/ro_rotrg.rb
 - lib/rggen/verilog/bit_field/type/rof.erb
 - lib/rggen/verilog/bit_field/type/rof.rb
+- lib/rggen/verilog/bit_field/type/rol.erb
+- lib/rggen/verilog/bit_field/type/rol.rb
 - lib/rggen/verilog/bit_field/type/row0trg_row1trg.erb
 - lib/rggen/verilog/bit_field/type/row0trg_row1trg.rb
 - lib/rggen/verilog/bit_field/type/rowo_rowotrg.erb
@@ -128,8 +132,8 @@ required_rubygems_version: !ruby/object:Gem::Requirement
     - !ruby/object:Gem::Version
       version: '0'
 requirements: []
-rubygems_version: 3.3.3
+rubygems_version: 3.3.7
 signing_key: 
 specification_version: 4
-summary: rggen-verilog-0.5.0
+summary: rggen-verilog-0.6.0
 test_files: []