rggen-verilog 0.4.0 → 0.4.1

This diff represents the content of publicly available package versions that have been released to one of the supported registries. The information contained in this diff is provided for informational purposes only and reflects changes between package versions as they appear in their respective public registries.
Files changed (6) hide show
  1. checksums.yaml +4 -4
  2. data/lib/rggen/verilog/register/type/default.erb +0 -1
  3. data/lib/rggen/verilog/register/type/indirect.erb +0 -1
  4. data/lib/rggen/verilog/register/type.rb +12 -0
  5. data/lib/rggen/verilog/version.rb +1 -1
  6. metadata +3 -3
checksums.yaml CHANGED
@@ -1,7 +1,7 @@
1
1
  ---
2
2
  SHA256:
3
- metadata.gz: 8a67c663d19ff7961ec27d7cd6ab19cedfe3fac30fa63b979ce49619a294f3d5
4
- data.tar.gz: c4bdb45657ce7ab10bb5d5caa414f3e9159be3a0fc0b69f6206d06441d82aee3
3
+ metadata.gz: 69bdb147ee2667a46190e137d12ddb6846ebd91465e7bc6e5cb2b352a6cbbb15
4
+ data.tar.gz: 8e799e3a709c59913b267d05155eb00383c780764ecd6fc57e4a556b274fc752
5
5
  SHA512:
6
- metadata.gz: 475653aadd4aa3f2fd7ba1ee6c0a8ff5630c8c0269b8a8107c765250f3f878af3f8297fbaec8b8ea6cf50803f89a01ccf23db587b78340e83bcf9047f302ccfe
7
- data.tar.gz: 5cbe51368dccafd60e8d2a68c82293a54a83b88ec426966c537348e553d86ea8e4aa6e50ab4dd3ad8bbf1856b339030b0b9ed317f7c1615d3caa7e2a96e2491c
6
+ metadata.gz: bdb1c0c8bb75d07d4437cd206af4287c4cdb7e6651ec0d2e3e5f1a33a3a2b433ec3dad571a4788d3c4d3284b2d9f5901fe8759e1ae5f0ce912312c0f3ab2a4ae
7
+ data.tar.gz: e0020b2c399628bbf6263f2f3f2051204d9e72546fe35fd3df8b3f7947e445e0513fa09c4aaaa5686935b06b287545378a05e506310c4c240cee355a91cfdcd5
data/lib/rggen/verilog/register/type/default.erb CHANGED
@@ -5,7 +5,6 @@ rggen_default_register #(
5
5
  .OFFSET_ADDRESS (<%= offset_address %>),
6
6
  .BUS_WIDTH (<%= bus_width %>),
7
7
  .DATA_WIDTH (<%= width %>),
8
- .VALID_BITS (<%= valid_bits %>),
9
8
  .REGISTER_INDEX (<%= register_index %>)
10
9
  ) u_register (
11
10
  .i_clk (<%= clock %>),
data/lib/rggen/verilog/register/type/indirect.erb CHANGED
@@ -5,7 +5,6 @@ rggen_indirect_register #(
5
5
  .OFFSET_ADDRESS (<%= offset_address %>),
6
6
  .BUS_WIDTH (<%= bus_width %>),
7
7
  .DATA_WIDTH (<%= width %>),
8
- .VALID_BITS (<%= valid_bits %>),
9
8
  .INDIRECT_INDEX_WIDTH (<%= index_width %>),
10
9
  .INDIRECT_INDEX_VALUE (<%= concat(index_values) %>)
11
10
  ) u_register (
data/lib/rggen/verilog/register/type.rb CHANGED
@@ -5,6 +5,11 @@ RgGen.define_list_feature(:register, :type) do
5
5
  base_feature do
6
6
  include RgGen::SystemVerilog::RTL::RegisterType
7
7
 
8
+ pre_code :register do |code|
9
+ register.bit_fields.empty? ||
10
+ (code << tie_off_unused_signals << nl)
11
+ end
12
+
8
13
  private
9
14
 
10
15
  def clock
@@ -78,6 +83,13 @@ RgGen.define_list_feature(:register, :type) do
78
83
  def bit_field_value
79
84
  register.bit_field_value
80
85
  end
86
+
87
+ def tie_off_unused_signals
88
+ macro_call(
89
+ 'rggen_tie_off_unused_signals',
90
+ [width, valid_bits, bit_field_read_data, bit_field_value]
91
+ )
92
+ end
81
93
  end
82
94
 
83
95
  default_feature do
data/lib/rggen/verilog/version.rb CHANGED
@@ -2,6 +2,6 @@
2
2
 
3
3
  module RgGen
4
4
  module Verilog
5
- VERSION = '0.4.0'
5
+ VERSION = '0.4.1'
6
6
  end
7
7
  end
metadata CHANGED
@@ -1,14 +1,14 @@
1
1
  --- !ruby/object:Gem::Specification
2
2
  name: rggen-verilog
3
3
  version: !ruby/object:Gem::Version
4
- version: 0.4.0
4
+ version: 0.4.1
5
5
  platform: ruby
6
6
  authors:
7
7
  - Taichi Ishitani
8
8
  autorequire:
9
9
  bindir: bin
10
10
  cert_chain: []
11
- date: 2022-03-25 00:00:00.000000000 Z
11
+ date: 2022-06-07 00:00:00.000000000 Z
12
12
  dependencies:
13
13
  - !ruby/object:Gem::Dependency
14
14
  name: rggen-systemverilog
@@ -130,5 +130,5 @@ requirements: []
130
130
  rubygems_version: 3.3.3
131
131
  signing_key:
132
132
  specification_version: 4
133
- summary: rggen-verilog-0.4.0
133
+ summary: rggen-verilog-0.4.1
134
134
  test_files: []