rggen-verilog 0.4.0 → 0.4.1

checksums.yaml

@@ -1,7 +1,7 @@
 ---
 SHA256:
-  metadata.gz: 8a67c663d19ff7961ec27d7cd6ab19cedfe3fac30fa63b979ce49619a294f3d5
-  data.tar.gz: c4bdb45657ce7ab10bb5d5caa414f3e9159be3a0fc0b69f6206d06441d82aee3
+  metadata.gz: 69bdb147ee2667a46190e137d12ddb6846ebd91465e7bc6e5cb2b352a6cbbb15
+  data.tar.gz: 8e799e3a709c59913b267d05155eb00383c780764ecd6fc57e4a556b274fc752
 SHA512:
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-  data.tar.gz: 5cbe51368dccafd60e8d2a68c82293a54a83b88ec426966c537348e553d86ea8e4aa6e50ab4dd3ad8bbf1856b339030b0b9ed317f7c1615d3caa7e2a96e2491c
+  metadata.gz: bdb1c0c8bb75d07d4437cd206af4287c4cdb7e6651ec0d2e3e5f1a33a3a2b433ec3dad571a4788d3c4d3284b2d9f5901fe8759e1ae5f0ce912312c0f3ab2a4ae
+  data.tar.gz: e0020b2c399628bbf6263f2f3f2051204d9e72546fe35fd3df8b3f7947e445e0513fa09c4aaaa5686935b06b287545378a05e506310c4c240cee355a91cfdcd5

data/lib/rggen/verilog/register/type/default.erb

@@ -5,7 +5,6 @@ rggen_default_register #(
   .OFFSET_ADDRESS (<%= offset_address %>),
   .BUS_WIDTH      (<%= bus_width %>),
   .DATA_WIDTH     (<%= width %>),
-  .VALID_BITS     (<%= valid_bits %>),
   .REGISTER_INDEX (<%= register_index %>)
 ) u_register (
   .i_clk                  (<%= clock %>),

data/lib/rggen/verilog/register/type/indirect.erb

@@ -5,7 +5,6 @@ rggen_indirect_register #(
   .OFFSET_ADDRESS       (<%= offset_address %>),
   .BUS_WIDTH            (<%= bus_width %>),
   .DATA_WIDTH           (<%= width %>),
-  .VALID_BITS           (<%= valid_bits %>),
   .INDIRECT_INDEX_WIDTH (<%= index_width %>),
   .INDIRECT_INDEX_VALUE (<%= concat(index_values) %>)
 ) u_register (

data/lib/rggen/verilog/register/type.rb

@@ -5,6 +5,11 @@ RgGen.define_list_feature(:register, :type) do
     base_feature do
       include RgGen::SystemVerilog::RTL::RegisterType
 
+      pre_code :register do |code|
+        register.bit_fields.empty? ||
+          (code << tie_off_unused_signals << nl)
+      end
+
       private
 
       def clock
@@ -78,6 +83,13 @@ RgGen.define_list_feature(:register, :type) do
       def bit_field_value
         register.bit_field_value
       end
+
+      def tie_off_unused_signals
+        macro_call(
+          'rggen_tie_off_unused_signals',
+          [width, valid_bits, bit_field_read_data, bit_field_value]
+        )
+      end
     end
 
     default_feature do

data/lib/rggen/verilog/version.rb

@@ -2,6 +2,6 @@
 
 module RgGen
   module Verilog
-    VERSION = '0.4.0'
+    VERSION = '0.4.1'
   end
 end

metadata

@@ -1,14 +1,14 @@
 --- !ruby/object:Gem::Specification
 name: rggen-verilog
 version: !ruby/object:Gem::Version
-  version: 0.4.0
+  version: 0.4.1
 platform: ruby
 authors:
 - Taichi Ishitani
 autorequire: 
 bindir: bin
 cert_chain: []
-date: 2022-03-25 00:00:00.000000000 Z
+date: 2022-06-07 00:00:00.000000000 Z
 dependencies:
 - !ruby/object:Gem::Dependency
   name: rggen-systemverilog
@@ -130,5 +130,5 @@ requirements: []
 rubygems_version: 3.3.3
 signing_key: 
 specification_version: 4
-summary: rggen-verilog-0.4.0
+summary: rggen-verilog-0.4.1
 test_files: []