rggen-verilog 0.3.2 → 0.5.0
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- checksums.yaml +4 -4
- data/LICENSE +1 -1
- data/README.md +3 -2
- data/lib/rggen/verilog/bit_field/type/rc_w0c_w1c_wc_woc.erb +2 -0
- data/lib/rggen/verilog/bit_field/type/{ro.erb → ro_rotrg.erb} +8 -4
- data/lib/rggen/verilog/bit_field/type/ro_rotrg.rb +38 -0
- data/lib/rggen/verilog/bit_field/type/rof.erb +5 -2
- data/lib/rggen/verilog/bit_field/type/row0trg_row1trg.erb +16 -0
- data/lib/rggen/verilog/bit_field/type/row0trg_row1trg.rb +28 -0
- data/lib/rggen/verilog/bit_field/type/rowo_rowotrg.erb +26 -0
- data/lib/rggen/verilog/bit_field/type/rowo_rowotrg.rb +48 -0
- data/lib/rggen/verilog/bit_field/type/rs_w0s_w1s_ws_wos.erb +2 -0
- data/lib/rggen/verilog/bit_field/type/{rw_w1_wo_wo1.erb → rw_rwtrg_w1.erb} +4 -2
- data/lib/rggen/verilog/bit_field/type/rw_rwtrg_w1.rb +43 -0
- data/lib/rggen/verilog/bit_field/type/rwc.erb +2 -0
- data/lib/rggen/verilog/bit_field/type/rwe_rwl.erb +2 -0
- data/lib/rggen/verilog/bit_field/type/rws.erb +2 -0
- data/lib/rggen/verilog/bit_field/type/w0crs_w0src_w1crs_w1src_wcrs_wsrc.erb +2 -0
- data/lib/rggen/verilog/bit_field/type/w0t_w1t.erb +2 -0
- data/lib/rggen/verilog/bit_field/type/w0trg_w1trg.erb +11 -9
- data/lib/rggen/verilog/bit_field/type/wo_wo1_wotrg.erb +27 -0
- data/lib/rggen/verilog/bit_field/type/wo_wo1_wotrg.rb +36 -0
- data/lib/rggen/verilog/bit_field/type/wrc_wrs.erb +2 -0
- data/lib/rggen/verilog/register/type/default.erb +0 -1
- data/lib/rggen/verilog/register/type/indirect.erb +0 -1
- data/lib/rggen/verilog/register/type.rb +12 -0
- data/lib/rggen/verilog/register_block/protocol/wishbone.erb +35 -0
- data/lib/rggen/verilog/register_block/protocol/wishbone.rb +47 -0
- data/lib/rggen/verilog/version.rb +1 -1
- data/lib/rggen/verilog.rb +37 -35
- metadata +21 -13
- data/lib/rggen/verilog/bit_field/type/ro.rb +0 -21
- data/lib/rggen/verilog/bit_field/type/rw_w1_wo_wo1.rb +0 -23
- data/lib/rggen/verilog/setup.rb +0 -11
checksums.yaml
CHANGED
@@ -1,7 +1,7 @@
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1
1
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---
|
2
2
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SHA256:
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3
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-
metadata.gz:
|
4
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-
data.tar.gz:
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3
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+
metadata.gz: 92ebf6366cd316b67c1baff2f0298b9240a2c570cf1660ec808ed952f763f114
|
4
|
+
data.tar.gz: d3cd1664b3e5441c5b09867236012b917c29a0a9dd306c5e781b5c8a215b4b9e
|
5
5
|
SHA512:
|
6
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-
metadata.gz:
|
7
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-
data.tar.gz:
|
6
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+
metadata.gz: d4cf77051fb8dcf8e5516c030a874d7183cca68d2b7e9ca7fe550100cd23fef13e31fd915836ab8d439fe468efb5ffcb33a350f71eda030a81a37a76346c2345
|
7
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+
data.tar.gz: 1f2e154e8fbe2444127d99d4bcca05c6042058c19ac46b6d2337a3b288ac7a511b3bc77ea88f08cdb5882667e56b74649d5db54f5ba7ea0db6f1fbb7a35f1667
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data/LICENSE
CHANGED
@@ -1,6 +1,6 @@
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1
1
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The MIT License (MIT)
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2
2
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-
Copyright (c) 2020-
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3
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+
Copyright (c) 2020-2022 Taichi Ishitani
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5
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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data/README.md
CHANGED
@@ -60,14 +60,15 @@ $ simulator \
|
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60
60
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61
61
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Feedbacks, bus reports, questions and etc. are welcome! You can post them bu using following ways:
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-
* [GitHub Issue Tracker](https://github.com/rggen/rggen
|
63
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+
* [GitHub Issue Tracker](https://github.com/rggen/rggen/issues)
|
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+
* [GitHub Discussions](https://github.com/rggen/rggen/discussions)
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65
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* [Chat Room](https://gitter.im/rggen/rggen)
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65
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* [Mailing List](https://groups.google.com/d/forum/rggen)
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67
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* [Mail](mailto:rggen@googlegroups.com)
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## Copyright & License
|
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70
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-
Copyright © 2020-
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+
Copyright © 2020-2022 Taichi Ishitani. RgGen::Verilog is licensed under the [MIT License](https://opensource.org/licenses/MIT), see [LICENSE](LICENSE) for futher details.
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## Code of Conduct
|
73
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@@ -13,6 +13,8 @@ rggen_bit_field #(
|
|
13
13
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.i_sw_write_data (<%= bit_field_write_data %>),
|
14
14
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.o_sw_read_data (<%= bit_field_read_data %>),
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15
15
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.o_sw_value (<%= bit_field_value %>),
|
16
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+
.o_write_trigger (),
|
17
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+
.o_read_trigger (),
|
16
18
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.i_hw_write_enable (1'b0),
|
17
19
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.i_hw_write_data (<%= fill_0(width) %>),
|
18
20
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.i_hw_set (<%= set[loop_variables] %>),
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@@ -1,9 +1,11 @@
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1
1
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rggen_bit_field #(
|
2
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-
.WIDTH
|
3
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-
.STORAGE
|
2
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+
.WIDTH (<%= width %>),
|
3
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+
.STORAGE (0),
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4
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+
.EXTERNAL_READ_DATA (1),
|
5
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+
.TRIGGER (<%= trigger %>)
|
4
6
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) u_bit_field (
|
5
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-
.i_clk (
|
6
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-
.i_rst_n (
|
7
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+
.i_clk (<%= clock %>),
|
8
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+
.i_rst_n (<%= reset %>),
|
7
9
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.i_sw_valid (<%= bit_field_valid %>),
|
8
10
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.i_sw_read_mask (<%= bit_field_read_mask %>),
|
9
11
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.i_sw_write_enable (1'b0),
|
@@ -11,6 +13,8 @@ rggen_bit_field #(
|
|
11
13
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.i_sw_write_data (<%= bit_field_write_data %>),
|
12
14
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.o_sw_read_data (<%= bit_field_read_data %>),
|
13
15
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.o_sw_value (<%= bit_field_value %>),
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16
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+
.o_write_trigger (),
|
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+
.o_read_trigger (<%= read_trigger_signal %>),
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14
18
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.i_hw_write_enable (1'b0),
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15
19
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.i_hw_write_data (<%= fill_0(width) %>),
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16
20
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.i_hw_set (<%= fill_0(width) %>),
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@@ -0,0 +1,38 @@
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1
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+
# frozen_string_literal: true
|
2
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+
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3
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RgGen.define_list_item_feature(:bit_field, :type, [:ro, :rotrg]) do
|
4
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+
verilog do
|
5
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build do
|
6
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+
unless bit_field.reference?
|
7
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input :value_in, {
|
8
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+
name: "i_#{full_name}", width: width, array_size: array_size
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9
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+
}
|
10
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+
end
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+
if rotrg?
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12
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+
output :read_trigger, {
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13
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+
name: "o_#{full_name}_read_trigger", width: 1, array_size: array_size
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}
|
15
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+
end
|
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end
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+
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main_code :bit_field, from_template: true
|
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+
|
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private
|
21
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+
|
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def rotrg?
|
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bit_field.type == :rotrg
|
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+
end
|
25
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+
|
26
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+
def trigger
|
27
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rotrg? && 1 || 0
|
28
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+
end
|
29
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+
|
30
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def read_trigger_signal
|
31
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+
rotrg? && read_trigger[loop_variables] || nil
|
32
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+
end
|
33
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+
|
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def reference_or_value_in
|
35
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+
reference_bit_field || value_in[loop_variables]
|
36
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+
end
|
37
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+
end
|
38
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+
end
|
@@ -1,6 +1,7 @@
|
|
1
1
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rggen_bit_field #(
|
2
|
-
.WIDTH
|
3
|
-
.STORAGE
|
2
|
+
.WIDTH (<%= width %>),
|
3
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+
.STORAGE (0),
|
4
|
+
.EXTERNAL_READ_DATA (1)
|
4
5
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) u_bit_field (
|
5
6
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.i_clk (1'b0),
|
6
7
|
.i_rst_n (1'b0),
|
@@ -11,6 +12,8 @@ rggen_bit_field #(
|
|
11
12
|
.i_sw_write_data (<%= bit_field_write_data %>),
|
12
13
|
.o_sw_read_data (<%= bit_field_read_data %>),
|
13
14
|
.o_sw_value (<%= bit_field_value %>),
|
15
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+
.o_write_trigger (),
|
16
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+
.o_read_trigger (),
|
14
17
|
.i_hw_write_enable (1'b0),
|
15
18
|
.i_hw_write_data (<%= fill_0(width) %>),
|
16
19
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.i_hw_set (<%= fill_0(width) %>),
|
@@ -0,0 +1,16 @@
|
|
1
|
+
rggen_bit_field_w01trg #(
|
2
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+
.TRIGGER_VALUE (<%= trigger_value %>),
|
3
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+
.WIDTH (<%= width %>)
|
4
|
+
) u_bit_field (
|
5
|
+
.i_clk (<%= clock %>),
|
6
|
+
.i_rst_n (<%= reset %>),
|
7
|
+
.i_sw_valid (<%= bit_field_valid %>),
|
8
|
+
.i_sw_read_mask (<%= bit_field_read_mask %>),
|
9
|
+
.i_sw_write_enable (1'b1),
|
10
|
+
.i_sw_write_mask (<%= bit_field_write_mask %>),
|
11
|
+
.i_sw_write_data (<%= bit_field_write_data %>),
|
12
|
+
.o_sw_read_data (<%= bit_field_read_data %>),
|
13
|
+
.o_sw_value (<%= bit_field_value %>),
|
14
|
+
.i_value (<%= reference_or_value_in %>),
|
15
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+
.o_trigger (<%= trigger[loop_variables] %>)
|
16
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+
);
|
@@ -0,0 +1,28 @@
|
|
1
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+
# frozen_string_literal: true
|
2
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+
|
3
|
+
RgGen.define_list_item_feature(:bit_field, :type, [:row0trg, :row1trg]) do
|
4
|
+
verilog do
|
5
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+
build do
|
6
|
+
unless bit_field.reference?
|
7
|
+
input :value_in, {
|
8
|
+
name: "i_#{full_name}", width: width, array_size: array_size
|
9
|
+
}
|
10
|
+
end
|
11
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+
output :trigger, {
|
12
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+
name: "o_#{full_name}_trigger", width: width, array_size: array_size
|
13
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+
}
|
14
|
+
end
|
15
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+
|
16
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+
main_code :bit_field, from_template: true
|
17
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+
|
18
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+
private
|
19
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+
|
20
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+
def trigger_value
|
21
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+
bin({ row0trg: 0, row1trg: 1 }[bit_field.type], 1)
|
22
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+
end
|
23
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+
|
24
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+
def reference_or_value_in
|
25
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+
reference_bit_field || value_in[loop_variables]
|
26
|
+
end
|
27
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+
end
|
28
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+
end
|
@@ -0,0 +1,26 @@
|
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1
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+
rggen_bit_field #(
|
2
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+
.WIDTH (<%= width %>),
|
3
|
+
.INITIAL_VALUE (<%= initial_value %>),
|
4
|
+
.EXTERNAL_READ_DATA (1),
|
5
|
+
.TRIGGER (<%= trigger %>)
|
6
|
+
) u_bit_field (
|
7
|
+
.i_clk (<%= clock %>),
|
8
|
+
.i_rst_n (<%= reset %>),
|
9
|
+
.i_sw_valid (<%= bit_field_valid %>),
|
10
|
+
.i_sw_read_mask (<%= bit_field_read_mask %>),
|
11
|
+
.i_sw_write_enable (1'b1),
|
12
|
+
.i_sw_write_mask (<%= bit_field_write_mask %>),
|
13
|
+
.i_sw_write_data (<%= bit_field_write_data %>),
|
14
|
+
.o_sw_read_data (<%= bit_field_read_data %>),
|
15
|
+
.o_sw_value (<%= bit_field_value %>),
|
16
|
+
.o_write_trigger (<%= write_trigger_signal %>),
|
17
|
+
.o_read_trigger (<%= read_trigger_signal %>),
|
18
|
+
.i_hw_write_enable (1'b0),
|
19
|
+
.i_hw_write_data (<%= fill_0(width) %>),
|
20
|
+
.i_hw_set (<%= fill_0(width) %>),
|
21
|
+
.i_hw_clear (<%= fill_0(width) %>),
|
22
|
+
.i_value (<%= reference_or_value_in %>),
|
23
|
+
.i_mask (<%= fill_1(width) %>),
|
24
|
+
.o_value (<%= value_out[loop_variables] %>),
|
25
|
+
.o_value_unmasked ()
|
26
|
+
);
|
@@ -0,0 +1,48 @@
|
|
1
|
+
# frozen_string_literal: true
|
2
|
+
|
3
|
+
RgGen.define_list_item_feature(:bit_field, :type, [:rowo, :rowotrg]) do
|
4
|
+
verilog do
|
5
|
+
build do
|
6
|
+
output :value_out, {
|
7
|
+
name: "o_#{full_name}", width: width, array_size: array_size
|
8
|
+
}
|
9
|
+
unless bit_field.reference?
|
10
|
+
input :value_in, {
|
11
|
+
name: "i_#{full_name}", width: width, array_size: array_size
|
12
|
+
}
|
13
|
+
end
|
14
|
+
if rowotrg?
|
15
|
+
output :write_trigger, {
|
16
|
+
name: "o_#{full_name}_write_trigger", width: 1, array_size: array_size
|
17
|
+
}
|
18
|
+
output :read_trigger, {
|
19
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+
name: "o_#{full_name}_read_trigger", width: 1, array_size: array_size
|
20
|
+
}
|
21
|
+
end
|
22
|
+
end
|
23
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+
|
24
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main_code :bit_field, from_template: true
|
25
|
+
|
26
|
+
private
|
27
|
+
|
28
|
+
def rowotrg?
|
29
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+
bit_field.type == :rowotrg
|
30
|
+
end
|
31
|
+
|
32
|
+
def trigger
|
33
|
+
rowotrg? && 1 || 0
|
34
|
+
end
|
35
|
+
|
36
|
+
def write_trigger_signal
|
37
|
+
rowotrg? && write_trigger[loop_variables] || nil
|
38
|
+
end
|
39
|
+
|
40
|
+
def read_trigger_signal
|
41
|
+
rowotrg? && read_trigger[loop_variables] || nil
|
42
|
+
end
|
43
|
+
|
44
|
+
def reference_or_value_in
|
45
|
+
reference_bit_field || value_in[loop_variables]
|
46
|
+
end
|
47
|
+
end
|
48
|
+
end
|
@@ -13,6 +13,8 @@ rggen_bit_field #(
|
|
13
13
|
.i_sw_write_data (<%= bit_field_write_data %>),
|
14
14
|
.o_sw_read_data (<%= bit_field_read_data %>),
|
15
15
|
.o_sw_value (<%= bit_field_value %>),
|
16
|
+
.o_write_trigger (),
|
17
|
+
.o_read_trigger (),
|
16
18
|
.i_hw_write_enable (1'b0),
|
17
19
|
.i_hw_write_data (<%= fill_0(width) %>),
|
18
20
|
.i_hw_set (<%= fill_0(width) %>),
|
@@ -1,8 +1,8 @@
|
|
1
1
|
rggen_bit_field #(
|
2
2
|
.WIDTH (<%= width %>),
|
3
3
|
.INITIAL_VALUE (<%= initial_value %>),
|
4
|
-
.
|
5
|
-
.
|
4
|
+
.SW_WRITE_ONCE (<%= write_once %>),
|
5
|
+
.TRIGGER (<%= trigger %>)
|
6
6
|
) u_bit_field (
|
7
7
|
.i_clk (<%= clock %>),
|
8
8
|
.i_rst_n (<%= reset %>),
|
@@ -13,6 +13,8 @@ rggen_bit_field #(
|
|
13
13
|
.i_sw_write_data (<%= bit_field_write_data %>),
|
14
14
|
.o_sw_read_data (<%= bit_field_read_data %>),
|
15
15
|
.o_sw_value (<%= bit_field_value %>),
|
16
|
+
.o_write_trigger (<%= write_trigger_signal %>),
|
17
|
+
.o_read_trigger (<%= read_trigger_signal %>),
|
16
18
|
.i_hw_write_enable (1'b0),
|
17
19
|
.i_hw_write_data (<%= fill_0(width) %>),
|
18
20
|
.i_hw_set (<%= fill_0(width) %>),
|
@@ -0,0 +1,43 @@
|
|
1
|
+
# frozen_string_literal: true
|
2
|
+
|
3
|
+
RgGen.define_list_item_feature(:bit_field, :type, [:rw, :rwtrg, :w1]) do
|
4
|
+
verilog do
|
5
|
+
build do
|
6
|
+
output :value_out, {
|
7
|
+
name: "o_#{full_name}", width: width, array_size: array_size
|
8
|
+
}
|
9
|
+
if rwtrg?
|
10
|
+
output :write_trigger, {
|
11
|
+
name: "o_#{full_name}_write_trigger", width: 1, array_size: array_size
|
12
|
+
}
|
13
|
+
output :read_trigger, {
|
14
|
+
name: "o_#{full_name}_read_trigger", width: 1, array_size: array_size
|
15
|
+
}
|
16
|
+
end
|
17
|
+
end
|
18
|
+
|
19
|
+
main_code :bit_field, from_template: true
|
20
|
+
|
21
|
+
private
|
22
|
+
|
23
|
+
def rwtrg?
|
24
|
+
bit_field.type == :rwtrg
|
25
|
+
end
|
26
|
+
|
27
|
+
def write_once
|
28
|
+
bit_field.type == :w1 && 1 || 0
|
29
|
+
end
|
30
|
+
|
31
|
+
def trigger
|
32
|
+
rwtrg? && 1 || 0
|
33
|
+
end
|
34
|
+
|
35
|
+
def write_trigger_signal
|
36
|
+
rwtrg? && write_trigger[loop_variables] || nil
|
37
|
+
end
|
38
|
+
|
39
|
+
def read_trigger_signal
|
40
|
+
rwtrg? && read_trigger[loop_variables] || nil
|
41
|
+
end
|
42
|
+
end
|
43
|
+
end
|
@@ -12,6 +12,8 @@ rggen_bit_field #(
|
|
12
12
|
.i_sw_write_data (<%= bit_field_write_data %>),
|
13
13
|
.o_sw_read_data (<%= bit_field_read_data %>),
|
14
14
|
.o_sw_value (<%= bit_field_value %>),
|
15
|
+
.o_write_trigger (),
|
16
|
+
.o_read_trigger (),
|
15
17
|
.i_hw_write_enable (1'b0),
|
16
18
|
.i_hw_write_data (<%= fill_0(width) %>),
|
17
19
|
.i_hw_set (<%= fill_0(width) %>),
|
@@ -12,6 +12,8 @@ rggen_bit_field #(
|
|
12
12
|
.i_sw_write_data (<%= bit_field_write_data %>),
|
13
13
|
.o_sw_read_data (<%= bit_field_read_data %>),
|
14
14
|
.o_sw_value (<%= bit_field_value %>),
|
15
|
+
.o_write_trigger (),
|
16
|
+
.o_read_trigger (),
|
15
17
|
.i_hw_write_enable (1'b0),
|
16
18
|
.i_hw_write_data (<%= fill_0(width) %>),
|
17
19
|
.i_hw_set (<%= fill_0(width) %>),
|
@@ -11,6 +11,8 @@ rggen_bit_field #(
|
|
11
11
|
.i_sw_write_data (<%= bit_field_write_data %>),
|
12
12
|
.o_sw_read_data (<%= bit_field_read_data %>),
|
13
13
|
.o_sw_value (<%= bit_field_value %>),
|
14
|
+
.o_write_trigger (),
|
15
|
+
.o_read_trigger (),
|
14
16
|
.i_hw_write_enable (<%= set_signal %>),
|
15
17
|
.i_hw_write_data (<%= value_in[loop_variables] %>),
|
16
18
|
.i_hw_set (<%= fill_0(width) %>),
|
@@ -13,6 +13,8 @@ rggen_bit_field #(
|
|
13
13
|
.i_sw_write_data (<%= bit_field_write_data %>),
|
14
14
|
.o_sw_read_data (<%= bit_field_read_data %>),
|
15
15
|
.o_sw_value (<%= bit_field_value %>),
|
16
|
+
.o_write_trigger (),
|
17
|
+
.o_read_trigger (),
|
16
18
|
.i_hw_write_enable (1'b0),
|
17
19
|
.i_hw_write_data (<%= fill_0(width) %>),
|
18
20
|
.i_hw_set (<%= fill_0(width) %>),
|
@@ -12,6 +12,8 @@ rggen_bit_field #(
|
|
12
12
|
.i_sw_write_data (<%= bit_field_write_data %>),
|
13
13
|
.o_sw_read_data (<%= bit_field_read_data %>),
|
14
14
|
.o_sw_value (<%= bit_field_value %>),
|
15
|
+
.o_write_trigger (),
|
16
|
+
.o_read_trigger (),
|
15
17
|
.i_hw_write_enable (1'b0),
|
16
18
|
.i_hw_write_data (<%= fill_0(width) %>),
|
17
19
|
.i_hw_set (<%= fill_0(width) %>),
|
@@ -2,13 +2,15 @@ rggen_bit_field_w01trg #(
|
|
2
2
|
.TRIGGER_VALUE (<%= trigger_value %>),
|
3
3
|
.WIDTH (<%= width %>)
|
4
4
|
) u_bit_field (
|
5
|
-
.i_clk
|
6
|
-
.i_rst_n
|
7
|
-
.
|
8
|
-
.
|
9
|
-
.
|
10
|
-
.
|
11
|
-
.
|
12
|
-
.
|
13
|
-
.
|
5
|
+
.i_clk (<%= clock %>),
|
6
|
+
.i_rst_n (<%= reset %>),
|
7
|
+
.i_sw_valid (<%= bit_field_valid %>),
|
8
|
+
.i_sw_read_mask (<%= bit_field_read_mask %>),
|
9
|
+
.i_sw_write_enable (1'b1),
|
10
|
+
.i_sw_write_mask (<%= bit_field_write_mask %>),
|
11
|
+
.i_sw_write_data (<%= bit_field_write_data %>),
|
12
|
+
.o_sw_read_data (<%= bit_field_read_data %>),
|
13
|
+
.o_sw_value (<%= bit_field_value %>),
|
14
|
+
.i_value (<%= fill_0(width) %>),
|
15
|
+
.o_trigger (<%= trigger[loop_variables] %>)
|
14
16
|
);
|
@@ -0,0 +1,27 @@
|
|
1
|
+
rggen_bit_field #(
|
2
|
+
.WIDTH (<%= width %>),
|
3
|
+
.INITIAL_VALUE (<%= initial_value %>),
|
4
|
+
.SW_READ_ACTION (`RGGEN_READ_NONE),
|
5
|
+
.SW_WRITE_ONCE (<%= write_once %>),
|
6
|
+
.TRIGGER (<%= trigger %>)
|
7
|
+
) u_bit_field (
|
8
|
+
.i_clk (<%= clock %>),
|
9
|
+
.i_rst_n (<%= reset %>),
|
10
|
+
.i_sw_valid (<%= bit_field_valid %>),
|
11
|
+
.i_sw_read_mask (<%= bit_field_read_mask %>),
|
12
|
+
.i_sw_write_enable (1'b1),
|
13
|
+
.i_sw_write_mask (<%= bit_field_write_mask %>),
|
14
|
+
.i_sw_write_data (<%= bit_field_write_data %>),
|
15
|
+
.o_sw_read_data (<%= bit_field_read_data %>),
|
16
|
+
.o_sw_value (<%= bit_field_value %>),
|
17
|
+
.o_write_trigger (<%= write_trigger_signal %>),
|
18
|
+
.o_read_trigger (),
|
19
|
+
.i_hw_write_enable (1'b0),
|
20
|
+
.i_hw_write_data (<%= fill_0(width) %>),
|
21
|
+
.i_hw_set (<%= fill_0(width) %>),
|
22
|
+
.i_hw_clear (<%= fill_0(width) %>),
|
23
|
+
.i_value (<%= fill_0(width) %>),
|
24
|
+
.i_mask (<%= fill_1(width) %>),
|
25
|
+
.o_value (<%= value_out[loop_variables] %>),
|
26
|
+
.o_value_unmasked ()
|
27
|
+
);
|
@@ -0,0 +1,36 @@
|
|
1
|
+
# frozen_string_literal: true
|
2
|
+
|
3
|
+
RgGen.define_list_item_feature(:bit_field, :type, [:wo, :wo1, :wotrg]) do
|
4
|
+
verilog do
|
5
|
+
build do
|
6
|
+
output :value_out, {
|
7
|
+
name: "o_#{full_name}", width: width, array_size: array_size
|
8
|
+
}
|
9
|
+
if wotrg?
|
10
|
+
output :write_trigger, {
|
11
|
+
name: "o_#{full_name}_write_trigger", width: 1, array_size: array_size
|
12
|
+
}
|
13
|
+
end
|
14
|
+
end
|
15
|
+
|
16
|
+
main_code :bit_field, from_template: true
|
17
|
+
|
18
|
+
private
|
19
|
+
|
20
|
+
def wotrg?
|
21
|
+
bit_field.type == :wotrg
|
22
|
+
end
|
23
|
+
|
24
|
+
def write_once
|
25
|
+
bit_field.type == :wo1 && 1 || 0
|
26
|
+
end
|
27
|
+
|
28
|
+
def trigger
|
29
|
+
wotrg? && 1 || 0
|
30
|
+
end
|
31
|
+
|
32
|
+
def write_trigger_signal
|
33
|
+
wotrg? && write_trigger[loop_variables] || nil
|
34
|
+
end
|
35
|
+
end
|
36
|
+
end
|
@@ -12,6 +12,8 @@ rggen_bit_field #(
|
|
12
12
|
.i_sw_write_data (<%= bit_field_write_data %>),
|
13
13
|
.o_sw_read_data (<%= bit_field_read_data %>),
|
14
14
|
.o_sw_value (<%= bit_field_value %>),
|
15
|
+
.o_write_trigger (),
|
16
|
+
.o_read_trigger (),
|
15
17
|
.i_hw_write_enable (1'b0),
|
16
18
|
.i_hw_write_data (<%= fill_0(width) %>),
|
17
19
|
.i_hw_set (<%= fill_0(width) %>),
|
@@ -5,7 +5,6 @@ rggen_indirect_register #(
|
|
5
5
|
.OFFSET_ADDRESS (<%= offset_address %>),
|
6
6
|
.BUS_WIDTH (<%= bus_width %>),
|
7
7
|
.DATA_WIDTH (<%= width %>),
|
8
|
-
.VALID_BITS (<%= valid_bits %>),
|
9
8
|
.INDIRECT_INDEX_WIDTH (<%= index_width %>),
|
10
9
|
.INDIRECT_INDEX_VALUE (<%= concat(index_values) %>)
|
11
10
|
) u_register (
|
@@ -5,6 +5,11 @@ RgGen.define_list_feature(:register, :type) do
|
|
5
5
|
base_feature do
|
6
6
|
include RgGen::SystemVerilog::RTL::RegisterType
|
7
7
|
|
8
|
+
pre_code :register do |code|
|
9
|
+
register.bit_fields.empty? ||
|
10
|
+
(code << tie_off_unused_signals << nl)
|
11
|
+
end
|
12
|
+
|
8
13
|
private
|
9
14
|
|
10
15
|
def clock
|
@@ -78,6 +83,13 @@ RgGen.define_list_feature(:register, :type) do
|
|
78
83
|
def bit_field_value
|
79
84
|
register.bit_field_value
|
80
85
|
end
|
86
|
+
|
87
|
+
def tie_off_unused_signals
|
88
|
+
macro_call(
|
89
|
+
'rggen_tie_off_unused_signals',
|
90
|
+
[width, valid_bits, bit_field_read_data, bit_field_value]
|
91
|
+
)
|
92
|
+
end
|
81
93
|
end
|
82
94
|
|
83
95
|
default_feature do
|
@@ -0,0 +1,35 @@
|
|
1
|
+
rggen_wishbone_adapter #(
|
2
|
+
.ADDRESS_WIDTH (<%= address_width %>),
|
3
|
+
.LOCAL_ADDRESS_WIDTH (<%= local_address_width %>),
|
4
|
+
.BUS_WIDTH (<%= bus_width %>),
|
5
|
+
.REGISTERS (<%= total_registers %>),
|
6
|
+
.PRE_DECODE (<%= pre_decode %>),
|
7
|
+
.BASE_ADDRESS (<%= base_address %>),
|
8
|
+
.BYTE_SIZE (<%= byte_size %>),
|
9
|
+
.ERROR_STATUS (<%= error_status %>),
|
10
|
+
.DEFAULT_READ_DATA (<%= default_read_data %>),
|
11
|
+
.USE_STALL (<%= use_stall %>)
|
12
|
+
) u_adapter (
|
13
|
+
.i_clk (<%= register_block.clock %>),
|
14
|
+
.i_rst_n (<%= register_block.reset %>),
|
15
|
+
.i_wb_cyc (<%= wb_cyc %>),
|
16
|
+
.i_wb_stb (<%= wb_stb %>),
|
17
|
+
.o_wb_stall (<%= wb_stall %>),
|
18
|
+
.i_wb_adr (<%= wb_adr %>),
|
19
|
+
.i_wb_we (<%= wb_we %>),
|
20
|
+
.i_wb_dat (<%= wb_dat_i %>),
|
21
|
+
.i_wb_sel (<%= wb_sel %>),
|
22
|
+
.o_wb_ack (<%= wb_ack %>),
|
23
|
+
.o_wb_err (<%= wb_err %>),
|
24
|
+
.o_wb_rty (<%= wb_rty %>),
|
25
|
+
.o_wb_dat (<%= wb_dat_o %>),
|
26
|
+
.o_register_valid (<%= register_block.register_valid %>),
|
27
|
+
.o_register_access (<%= register_block.register_access %>),
|
28
|
+
.o_register_address (<%= register_block.register_address %>),
|
29
|
+
.o_register_write_data (<%= register_block.register_write_data %>),
|
30
|
+
.o_register_strobe (<%= register_block.register_strobe %>),
|
31
|
+
.i_register_active (<%= register_block.register_active %>),
|
32
|
+
.i_register_ready (<%= register_block.register_ready %>),
|
33
|
+
.i_register_status (<%= register_block.register_status %>),
|
34
|
+
.i_register_read_data (<%= register_block.register_read_data %>)
|
35
|
+
);
|
@@ -0,0 +1,47 @@
|
|
1
|
+
# frozen_string_literal: true
|
2
|
+
|
3
|
+
RgGen.define_list_item_feature(:register_block, :protocol, :wishbone) do
|
4
|
+
verilog do
|
5
|
+
build do
|
6
|
+
parameter :use_stall, {
|
7
|
+
name: 'USE_STALL', default: 1
|
8
|
+
}
|
9
|
+
|
10
|
+
input :wb_cyc, {
|
11
|
+
name: 'i_wb_cyc', width: 1
|
12
|
+
}
|
13
|
+
input :wb_stb, {
|
14
|
+
name: 'i_wb_stb', width: 1
|
15
|
+
}
|
16
|
+
output :wb_stall, {
|
17
|
+
name: 'o_wb_stall', width: 1
|
18
|
+
}
|
19
|
+
input :wb_adr, {
|
20
|
+
name: 'i_wb_adr', width: address_width
|
21
|
+
}
|
22
|
+
input :wb_we, {
|
23
|
+
name: 'i_wb_we', width: 1
|
24
|
+
}
|
25
|
+
input :wb_dat_i, {
|
26
|
+
name: 'i_wb_dat', width: bus_width
|
27
|
+
}
|
28
|
+
input :wb_sel, {
|
29
|
+
name: 'i_wb_sel', width: bus_width / 8
|
30
|
+
}
|
31
|
+
output :wb_ack, {
|
32
|
+
name: 'o_wb_ack', width: 1
|
33
|
+
}
|
34
|
+
output :wb_err, {
|
35
|
+
name: 'o_wb_err', width: 1
|
36
|
+
}
|
37
|
+
output :wb_rty, {
|
38
|
+
name: 'o_wb_rty', width: 1
|
39
|
+
}
|
40
|
+
output :wb_dat_o, {
|
41
|
+
name: 'o_wb_dat', width: bus_width
|
42
|
+
}
|
43
|
+
end
|
44
|
+
|
45
|
+
main_code :register_block, from_template: true
|
46
|
+
end
|
47
|
+
end
|
data/lib/rggen/verilog.rb
CHANGED
@@ -8,41 +8,43 @@ require_relative 'verilog/component'
|
|
8
8
|
require_relative 'verilog/feature'
|
9
9
|
require_relative 'verilog/factories'
|
10
10
|
|
11
|
-
|
12
|
-
|
13
|
-
extend Core::Plugin
|
11
|
+
RgGen.setup_plugin :'rggen-verilog' do |plugin|
|
12
|
+
plugin.version RgGen::Verilog::VERSION
|
14
13
|
|
15
|
-
|
16
|
-
|
17
|
-
|
18
|
-
|
19
|
-
|
20
|
-
|
21
|
-
plugin.files [
|
22
|
-
'verilog/bit_field/type',
|
23
|
-
'verilog/bit_field/type/rc_w0c_w1c_wc_woc',
|
24
|
-
'verilog/bit_field/type/ro',
|
25
|
-
'verilog/bit_field/type/rof',
|
26
|
-
'verilog/bit_field/type/rs_w0s_w1s_ws_wos',
|
27
|
-
'verilog/bit_field/type/rw_w1_wo_wo1',
|
28
|
-
'verilog/bit_field/type/rwc',
|
29
|
-
'verilog/bit_field/type/rwe_rwl',
|
30
|
-
'verilog/bit_field/type/rws',
|
31
|
-
'verilog/bit_field/type/w0crs_w0src_w1crs_w1src_wcrs_wsrc',
|
32
|
-
'verilog/bit_field/type/w0t_w1t',
|
33
|
-
'verilog/bit_field/type/w0trg_w1trg',
|
34
|
-
'verilog/bit_field/type/wrc_wrs',
|
35
|
-
'verilog/bit_field/verilog_top',
|
36
|
-
'verilog/register/type',
|
37
|
-
'verilog/register/type/external',
|
38
|
-
'verilog/register/type/indirect',
|
39
|
-
'verilog/register/verilog_top',
|
40
|
-
'verilog/register_block/protocol',
|
41
|
-
'verilog/register_block/protocol/apb',
|
42
|
-
'verilog/register_block/protocol/axi4lite',
|
43
|
-
'verilog/register_block/verilog_top',
|
44
|
-
'verilog/register_file/verilog_top'
|
45
|
-
]
|
46
|
-
end
|
14
|
+
plugin.register_component :verilog do
|
15
|
+
component RgGen::Verilog::Component,
|
16
|
+
RgGen::Verilog::ComponentFactory
|
17
|
+
feature RgGen::Verilog::Feature,
|
18
|
+
RgGen::Verilog::FeatureFactory
|
47
19
|
end
|
20
|
+
|
21
|
+
plugin.files [
|
22
|
+
'verilog/register_block/verilog_top',
|
23
|
+
'verilog/register_block/protocol',
|
24
|
+
'verilog/register_block/protocol/apb',
|
25
|
+
'verilog/register_block/protocol/axi4lite',
|
26
|
+
'verilog/register_block/protocol/wishbone',
|
27
|
+
'verilog/register_file/verilog_top',
|
28
|
+
'verilog/register/verilog_top',
|
29
|
+
'verilog/register/type',
|
30
|
+
'verilog/register/type/external',
|
31
|
+
'verilog/register/type/indirect',
|
32
|
+
'verilog/bit_field/verilog_top',
|
33
|
+
'verilog/bit_field/type',
|
34
|
+
'verilog/bit_field/type/rc_w0c_w1c_wc_woc',
|
35
|
+
'verilog/bit_field/type/ro_rotrg',
|
36
|
+
'verilog/bit_field/type/rof',
|
37
|
+
'verilog/bit_field/type/row0trg_row1trg',
|
38
|
+
'verilog/bit_field/type/rowo_rowotrg',
|
39
|
+
'verilog/bit_field/type/rs_w0s_w1s_ws_wos',
|
40
|
+
'verilog/bit_field/type/rw_rwtrg_w1',
|
41
|
+
'verilog/bit_field/type/rwc',
|
42
|
+
'verilog/bit_field/type/rwe_rwl',
|
43
|
+
'verilog/bit_field/type/rws',
|
44
|
+
'verilog/bit_field/type/w0crs_w0src_w1crs_w1src_wcrs_wsrc',
|
45
|
+
'verilog/bit_field/type/w0t_w1t',
|
46
|
+
'verilog/bit_field/type/w0trg_w1trg',
|
47
|
+
'verilog/bit_field/type/wo_wo1_wotrg',
|
48
|
+
'verilog/bit_field/type/wrc_wrs'
|
49
|
+
]
|
48
50
|
end
|
metadata
CHANGED
@@ -1,14 +1,14 @@
|
|
1
1
|
--- !ruby/object:Gem::Specification
|
2
2
|
name: rggen-verilog
|
3
3
|
version: !ruby/object:Gem::Version
|
4
|
-
version: 0.
|
4
|
+
version: 0.5.0
|
5
5
|
platform: ruby
|
6
6
|
authors:
|
7
7
|
- Taichi Ishitani
|
8
8
|
autorequire:
|
9
9
|
bindir: bin
|
10
10
|
cert_chain: []
|
11
|
-
date:
|
11
|
+
date: 2022-07-05 00:00:00.000000000 Z
|
12
12
|
dependencies:
|
13
13
|
- !ruby/object:Gem::Dependency
|
14
14
|
name: rggen-systemverilog
|
@@ -16,14 +16,14 @@ dependencies:
|
|
16
16
|
requirements:
|
17
17
|
- - ">="
|
18
18
|
- !ruby/object:Gem::Version
|
19
|
-
version: 0.
|
19
|
+
version: 0.27.0
|
20
20
|
type: :runtime
|
21
21
|
prerelease: false
|
22
22
|
version_requirements: !ruby/object:Gem::Requirement
|
23
23
|
requirements:
|
24
24
|
- - ">="
|
25
25
|
- !ruby/object:Gem::Version
|
26
|
-
version: 0.
|
26
|
+
version: 0.27.0
|
27
27
|
- !ruby/object:Gem::Dependency
|
28
28
|
name: bundler
|
29
29
|
requirement: !ruby/object:Gem::Requirement
|
@@ -52,14 +52,18 @@ files:
|
|
52
52
|
- lib/rggen/verilog/bit_field/type.rb
|
53
53
|
- lib/rggen/verilog/bit_field/type/rc_w0c_w1c_wc_woc.erb
|
54
54
|
- lib/rggen/verilog/bit_field/type/rc_w0c_w1c_wc_woc.rb
|
55
|
-
- lib/rggen/verilog/bit_field/type/
|
56
|
-
- lib/rggen/verilog/bit_field/type/
|
55
|
+
- lib/rggen/verilog/bit_field/type/ro_rotrg.erb
|
56
|
+
- lib/rggen/verilog/bit_field/type/ro_rotrg.rb
|
57
57
|
- lib/rggen/verilog/bit_field/type/rof.erb
|
58
58
|
- lib/rggen/verilog/bit_field/type/rof.rb
|
59
|
+
- lib/rggen/verilog/bit_field/type/row0trg_row1trg.erb
|
60
|
+
- lib/rggen/verilog/bit_field/type/row0trg_row1trg.rb
|
61
|
+
- lib/rggen/verilog/bit_field/type/rowo_rowotrg.erb
|
62
|
+
- lib/rggen/verilog/bit_field/type/rowo_rowotrg.rb
|
59
63
|
- lib/rggen/verilog/bit_field/type/rs_w0s_w1s_ws_wos.erb
|
60
64
|
- lib/rggen/verilog/bit_field/type/rs_w0s_w1s_ws_wos.rb
|
61
|
-
- lib/rggen/verilog/bit_field/type/
|
62
|
-
- lib/rggen/verilog/bit_field/type/
|
65
|
+
- lib/rggen/verilog/bit_field/type/rw_rwtrg_w1.erb
|
66
|
+
- lib/rggen/verilog/bit_field/type/rw_rwtrg_w1.rb
|
63
67
|
- lib/rggen/verilog/bit_field/type/rwc.erb
|
64
68
|
- lib/rggen/verilog/bit_field/type/rwc.rb
|
65
69
|
- lib/rggen/verilog/bit_field/type/rwe_rwl.erb
|
@@ -72,6 +76,8 @@ files:
|
|
72
76
|
- lib/rggen/verilog/bit_field/type/w0t_w1t.rb
|
73
77
|
- lib/rggen/verilog/bit_field/type/w0trg_w1trg.erb
|
74
78
|
- lib/rggen/verilog/bit_field/type/w0trg_w1trg.rb
|
79
|
+
- lib/rggen/verilog/bit_field/type/wo_wo1_wotrg.erb
|
80
|
+
- lib/rggen/verilog/bit_field/type/wo_wo1_wotrg.rb
|
75
81
|
- lib/rggen/verilog/bit_field/type/wrc_wrs.erb
|
76
82
|
- lib/rggen/verilog/bit_field/type/wrc_wrs.rb
|
77
83
|
- lib/rggen/verilog/bit_field/verilog_top.rb
|
@@ -90,10 +96,11 @@ files:
|
|
90
96
|
- lib/rggen/verilog/register_block/protocol/apb.rb
|
91
97
|
- lib/rggen/verilog/register_block/protocol/axi4lite.erb
|
92
98
|
- lib/rggen/verilog/register_block/protocol/axi4lite.rb
|
99
|
+
- lib/rggen/verilog/register_block/protocol/wishbone.erb
|
100
|
+
- lib/rggen/verilog/register_block/protocol/wishbone.rb
|
93
101
|
- lib/rggen/verilog/register_block/verilog_macros.erb
|
94
102
|
- lib/rggen/verilog/register_block/verilog_top.rb
|
95
103
|
- lib/rggen/verilog/register_file/verilog_top.rb
|
96
|
-
- lib/rggen/verilog/setup.rb
|
97
104
|
- lib/rggen/verilog/utility.rb
|
98
105
|
- lib/rggen/verilog/utility/local_scope.rb
|
99
106
|
- lib/rggen/verilog/version.rb
|
@@ -101,8 +108,9 @@ homepage: https://github.com/rggen/rggen-verilog
|
|
101
108
|
licenses:
|
102
109
|
- MIT
|
103
110
|
metadata:
|
104
|
-
bug_tracker_uri: https://github.com/rggen/rggen
|
111
|
+
bug_tracker_uri: https://github.com/rggen/rggen/issues
|
105
112
|
mailing_list_uri: https://groups.google.com/d/forum/rggen
|
113
|
+
rubygems_mfa_required: 'true'
|
106
114
|
source_code_uri: https://github.com/rggen/rggen-verilog
|
107
115
|
wiki_uri: https://github.com/rggen/rggen/wiki
|
108
116
|
post_install_message:
|
@@ -113,15 +121,15 @@ required_ruby_version: !ruby/object:Gem::Requirement
|
|
113
121
|
requirements:
|
114
122
|
- - ">="
|
115
123
|
- !ruby/object:Gem::Version
|
116
|
-
version: '2.
|
124
|
+
version: '2.6'
|
117
125
|
required_rubygems_version: !ruby/object:Gem::Requirement
|
118
126
|
requirements:
|
119
127
|
- - ">="
|
120
128
|
- !ruby/object:Gem::Version
|
121
129
|
version: '0'
|
122
130
|
requirements: []
|
123
|
-
rubygems_version: 3.
|
131
|
+
rubygems_version: 3.3.3
|
124
132
|
signing_key:
|
125
133
|
specification_version: 4
|
126
|
-
summary: rggen-verilog-0.
|
134
|
+
summary: rggen-verilog-0.5.0
|
127
135
|
test_files: []
|
@@ -1,21 +0,0 @@
|
|
1
|
-
# frozen_string_literal: true
|
2
|
-
|
3
|
-
RgGen.define_list_item_feature(:bit_field, :type, :ro) do
|
4
|
-
verilog do
|
5
|
-
build do
|
6
|
-
unless bit_field.reference?
|
7
|
-
input :value_in, {
|
8
|
-
name: "i_#{full_name}", width: width, array_size: array_size
|
9
|
-
}
|
10
|
-
end
|
11
|
-
end
|
12
|
-
|
13
|
-
main_code :bit_field, from_template: true
|
14
|
-
|
15
|
-
private
|
16
|
-
|
17
|
-
def reference_or_value_in
|
18
|
-
bit_field.reference? && reference_bit_field || value_in[loop_variables]
|
19
|
-
end
|
20
|
-
end
|
21
|
-
end
|
@@ -1,23 +0,0 @@
|
|
1
|
-
# frozen_string_literal: true
|
2
|
-
|
3
|
-
RgGen.define_list_item_feature(:bit_field, :type, [:rw, :w1, :wo, :wo1]) do
|
4
|
-
verilog do
|
5
|
-
build do
|
6
|
-
output :value_out, {
|
7
|
-
name: "o_#{full_name}", width: width, array_size: array_size
|
8
|
-
}
|
9
|
-
end
|
10
|
-
|
11
|
-
main_code :bit_field, from_template: true
|
12
|
-
|
13
|
-
private
|
14
|
-
|
15
|
-
def read_action
|
16
|
-
bit_field.readable? && '`RGGEN_READ_DEFAULT' || '`RGGEN_READ_NONE'
|
17
|
-
end
|
18
|
-
|
19
|
-
def write_once
|
20
|
-
[:w1, :wo1].include?(bit_field.type) && 1 || 0
|
21
|
-
end
|
22
|
-
end
|
23
|
-
end
|
data/lib/rggen/verilog/setup.rb
DELETED
@@ -1,11 +0,0 @@
|
|
1
|
-
# frozen_string_literal: true
|
2
|
-
|
3
|
-
require 'rggen/verilog'
|
4
|
-
|
5
|
-
RgGen.register_plugin RgGen::Verilog do |builder|
|
6
|
-
builder.load_plugin 'rggen/systemverilog/rtl/setup'
|
7
|
-
builder.enable :register_block, [:verilog_top]
|
8
|
-
builder.enable :register_file, [:verilog_top]
|
9
|
-
builder.enable :register, [:verilog_top]
|
10
|
-
builder.enable :bit_field, [:verilog_top]
|
11
|
-
end
|