rggen-verilog 0.3.1 → 0.4.1

checksums.yaml

@@ -1,7 +1,7 @@
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data/LICENSE

@@ -1,6 +1,6 @@
 The MIT License (MIT)
 
-Copyright (c) 2020-2021 Taichi Ishitani
+Copyright (c) 2020-2022 Taichi Ishitani
 
 Permission is hereby granted, free of charge, to any person obtaining a copy
 of this software and associated documentation files (the "Software"), to deal

data/README.md

@@ -67,7 +67,7 @@ Feedbacks, bus reports, questions and etc. are welcome! You can post them bu usi
 
 ## Copyright & License
 
-Copyright © 2020-2021 Taichi Ishitani. RgGen::Verilog is licensed under the [MIT License](https://opensource.org/licenses/MIT), see [LICENSE](LICENSE) for futher details.
+Copyright © 2020-2022 Taichi Ishitani. RgGen::Verilog is licensed under the [MIT License](https://opensource.org/licenses/MIT), see [LICENSE](LICENSE) for futher details.
 
 ## Code of Conduct
 

data/lib/rggen/verilog/bit_field/type/rc_w0c_w1c_wc_woc.erb

@@ -13,6 +13,8 @@ rggen_bit_field #(
   .i_sw_write_data    (<%= bit_field_write_data %>),
   .o_sw_read_data     (<%= bit_field_read_data %>),
   .o_sw_value         (<%= bit_field_value %>),
+  .o_write_trigger    (),
+  .o_read_trigger     (),
   .i_hw_write_enable  (1'b0),
   .i_hw_write_data    (<%= fill_0(width) %>),
   .i_hw_set           (<%= set[loop_variables] %>),

data/lib/rggen/verilog/bit_field/type/{ro.erb → ro_rotrg.erb}

@@ -1,9 +1,11 @@
 rggen_bit_field #(
-  .WIDTH    (<%= width %>),
-  .STORAGE  (0)
+  .WIDTH              (<%= width %>),
+  .STORAGE            (0),
+  .EXTERNAL_READ_DATA (1),
+  .TRIGGER            (<%= trigger %>)
 ) u_bit_field (
-  .i_clk              (1'b0),
-  .i_rst_n            (1'b0),
+  .i_clk              (<%= clock %>),
+  .i_rst_n            (<%= reset %>),
   .i_sw_valid         (<%= bit_field_valid %>),
   .i_sw_read_mask     (<%= bit_field_read_mask %>),
   .i_sw_write_enable  (1'b0),
@@ -11,6 +13,8 @@ rggen_bit_field #(
   .i_sw_write_data    (<%= bit_field_write_data %>),
   .o_sw_read_data     (<%= bit_field_read_data %>),
   .o_sw_value         (<%= bit_field_value %>),
+  .o_write_trigger    (),
+  .o_read_trigger     (<%= read_trigger_signal %>),
   .i_hw_write_enable  (1'b0),
   .i_hw_write_data    (<%= fill_0(width) %>),
   .i_hw_set           (<%= fill_0(width) %>),

data/lib/rggen/verilog/bit_field/type/ro_rotrg.rb

@@ -0,0 +1,38 @@
+# frozen_string_literal: true
+
+RgGen.define_list_item_feature(:bit_field, :type, [:ro, :rotrg]) do
+  verilog do
+    build do
+      unless bit_field.reference?
+        input :value_in, {
+          name: "i_#{full_name}", width: width, array_size: array_size
+        }
+      end
+      if rotrg?
+        output :read_trigger, {
+          name: "o_#{full_name}_read_trigger", width: 1, array_size: array_size
+        }
+      end
+    end
+
+    main_code :bit_field, from_template: true
+
+    private
+
+    def rotrg?
+      bit_field.type == :rotrg
+    end
+
+    def trigger
+      rotrg? && 1 || 0
+    end
+
+    def read_trigger_signal
+      rotrg? && read_trigger[loop_variables] || nil
+    end
+
+    def reference_or_value_in
+      reference_bit_field || value_in[loop_variables]
+    end
+  end
+end

data/lib/rggen/verilog/bit_field/type/rof.erb

@@ -1,6 +1,7 @@
 rggen_bit_field #(
-  .WIDTH    (<%= width %>),
-  .STORAGE  (0)
+  .WIDTH              (<%= width %>),
+  .STORAGE            (0),
+  .EXTERNAL_READ_DATA (1)
 ) u_bit_field (
   .i_clk              (1'b0),
   .i_rst_n            (1'b0),
@@ -11,6 +12,8 @@ rggen_bit_field #(
   .i_sw_write_data    (<%= bit_field_write_data %>),
   .o_sw_read_data     (<%= bit_field_read_data %>),
   .o_sw_value         (<%= bit_field_value %>),
+  .o_write_trigger    (),
+  .o_read_trigger     (),
   .i_hw_write_enable  (1'b0),
   .i_hw_write_data    (<%= fill_0(width) %>),
   .i_hw_set           (<%= fill_0(width) %>),

data/lib/rggen/verilog/bit_field/type/rowo_rowotrg.erb

@@ -0,0 +1,26 @@
+rggen_bit_field #(
+  .WIDTH              (<%= width %>),
+  .INITIAL_VALUE      (<%= initial_value %>),
+  .EXTERNAL_READ_DATA (1),
+  .TRIGGER            (<%= trigger %>)
+) u_bit_field (
+  .i_clk              (<%= clock %>),
+  .i_rst_n            (<%= reset %>),
+  .i_sw_valid         (<%= bit_field_valid %>),
+  .i_sw_read_mask     (<%= bit_field_read_mask %>),
+  .i_sw_write_enable  (1'b1),
+  .i_sw_write_mask    (<%= bit_field_write_mask %>),
+  .i_sw_write_data    (<%= bit_field_write_data %>),
+  .o_sw_read_data     (<%= bit_field_read_data %>),
+  .o_sw_value         (<%= bit_field_value %>),
+  .o_write_trigger    (<%= write_trigger_signal %>),
+  .o_read_trigger     (<%= read_trigger_signal %>),
+  .i_hw_write_enable  (1'b0),
+  .i_hw_write_data    (<%= fill_0(width) %>),
+  .i_hw_set           (<%= fill_0(width) %>),
+  .i_hw_clear         (<%= fill_0(width) %>),
+  .i_value            (<%= reference_or_value_in %>),
+  .i_mask             (<%= fill_1(width) %>),
+  .o_value            (<%= value_out[loop_variables] %>),
+  .o_value_unmasked   ()
+);

data/lib/rggen/verilog/bit_field/type/rowo_rowotrg.rb

@@ -0,0 +1,48 @@
+# frozen_string_literal: true
+
+RgGen.define_list_item_feature(:bit_field, :type, [:rowo, :rowotrg]) do
+  verilog do
+    build do
+      output :value_out, {
+        name: "o_#{full_name}", width: width, array_size: array_size
+      }
+      unless bit_field.reference?
+        input :value_in, {
+          name: "i_#{full_name}", width: width, array_size: array_size
+        }
+      end
+      if rowotrg?
+        output :write_trigger, {
+          name: "o_#{full_name}_write_trigger", width: 1, array_size: array_size
+        }
+        output :read_trigger, {
+          name: "o_#{full_name}_read_trigger", width: 1, array_size: array_size
+        }
+      end
+    end
+
+    main_code :bit_field, from_template: true
+
+    private
+
+    def rowotrg?
+      bit_field.type == :rowotrg
+    end
+
+    def trigger
+      rowotrg? && 1 || 0
+    end
+
+    def write_trigger_signal
+      rowotrg? && write_trigger[loop_variables] || nil
+    end
+
+    def read_trigger_signal
+      rowotrg? && read_trigger[loop_variables] || nil
+    end
+
+    def reference_or_value_in
+      reference_bit_field || value_in[loop_variables]
+    end
+  end
+end

data/lib/rggen/verilog/bit_field/type/rs_w0s_w1s_ws_wos.erb

@@ -13,6 +13,8 @@ rggen_bit_field #(
   .i_sw_write_data    (<%= bit_field_write_data %>),
   .o_sw_read_data     (<%= bit_field_read_data %>),
   .o_sw_value         (<%= bit_field_value %>),
+  .o_write_trigger    (),
+  .o_read_trigger     (),
   .i_hw_write_enable  (1'b0),
   .i_hw_write_data    (<%= fill_0(width) %>),
   .i_hw_set           (<%= fill_0(width) %>),

data/lib/rggen/verilog/bit_field/type/{rw_w1_wo_wo1.erb → rw_rwtrg_w1.erb}

@@ -1,8 +1,8 @@
 rggen_bit_field #(
   .WIDTH          (<%= width %>),
   .INITIAL_VALUE  (<%= initial_value %>),
-  .SW_READ_ACTION (<%= read_action %>),
-  .SW_WRITE_ONCE  (<%= write_once %>)
+  .SW_WRITE_ONCE  (<%= write_once %>),
+  .TRIGGER        (<%= trigger %>)
 ) u_bit_field (
   .i_clk              (<%= clock %>),
   .i_rst_n            (<%= reset %>),
@@ -13,6 +13,8 @@ rggen_bit_field #(
   .i_sw_write_data    (<%= bit_field_write_data %>),
   .o_sw_read_data     (<%= bit_field_read_data %>),
   .o_sw_value         (<%= bit_field_value %>),
+  .o_write_trigger    (<%= write_trigger_signal %>),
+  .o_read_trigger     (<%= read_trigger_signal %>),
   .i_hw_write_enable  (1'b0),
   .i_hw_write_data    (<%= fill_0(width) %>),
   .i_hw_set           (<%= fill_0(width) %>),

data/lib/rggen/verilog/bit_field/type/rw_rwtrg_w1.rb

@@ -0,0 +1,43 @@
+# frozen_string_literal: true
+
+RgGen.define_list_item_feature(:bit_field, :type, [:rw, :rwtrg, :w1]) do
+  verilog do
+    build do
+      output :value_out, {
+        name: "o_#{full_name}", width: width, array_size: array_size
+      }
+      if rwtrg?
+        output :write_trigger, {
+          name: "o_#{full_name}_write_trigger", width: 1, array_size: array_size
+        }
+        output :read_trigger, {
+          name: "o_#{full_name}_read_trigger", width: 1, array_size: array_size
+        }
+      end
+    end
+
+    main_code :bit_field, from_template: true
+
+    private
+
+    def rwtrg?
+      bit_field.type == :rwtrg
+    end
+
+    def write_once
+      bit_field.type == :w1 && 1 || 0
+    end
+
+    def trigger
+      rwtrg? && 1 || 0
+    end
+
+    def write_trigger_signal
+      rwtrg? && write_trigger[loop_variables] || nil
+    end
+
+    def read_trigger_signal
+      rwtrg? && read_trigger[loop_variables] || nil
+    end
+  end
+end

data/lib/rggen/verilog/bit_field/type/rwc.erb

@@ -12,6 +12,8 @@ rggen_bit_field #(
   .i_sw_write_data    (<%= bit_field_write_data %>),
   .o_sw_read_data     (<%= bit_field_read_data %>),
   .o_sw_value         (<%= bit_field_value %>),
+  .o_write_trigger    (),
+  .o_read_trigger     (),
   .i_hw_write_enable  (1'b0),
   .i_hw_write_data    (<%= fill_0(width) %>),
   .i_hw_set           (<%= fill_0(width) %>),

data/lib/rggen/verilog/bit_field/type/rwe_rwl.erb

@@ -12,6 +12,8 @@ rggen_bit_field #(
   .i_sw_write_data    (<%= bit_field_write_data %>),
   .o_sw_read_data     (<%= bit_field_read_data %>),
   .o_sw_value         (<%= bit_field_value %>),
+  .o_write_trigger    (),
+  .o_read_trigger     (),
   .i_hw_write_enable  (1'b0),
   .i_hw_write_data    (<%= fill_0(width) %>),
   .i_hw_set           (<%= fill_0(width) %>),

data/lib/rggen/verilog/bit_field/type/rws.erb

@@ -11,6 +11,8 @@ rggen_bit_field #(
   .i_sw_write_data    (<%= bit_field_write_data %>),
   .o_sw_read_data     (<%= bit_field_read_data %>),
   .o_sw_value         (<%= bit_field_value %>),
+  .o_write_trigger    (),
+  .o_read_trigger     (),
   .i_hw_write_enable  (<%= set_signal %>),
   .i_hw_write_data    (<%= value_in[loop_variables] %>),
   .i_hw_set           (<%= fill_0(width) %>),

data/lib/rggen/verilog/bit_field/type/w0crs_w0src_w1crs_w1src_wcrs_wsrc.erb

@@ -13,6 +13,8 @@ rggen_bit_field #(
   .i_sw_write_data    (<%= bit_field_write_data %>),
   .o_sw_read_data     (<%= bit_field_read_data %>),
   .o_sw_value         (<%= bit_field_value %>),
+  .o_write_trigger    (),
+  .o_read_trigger     (),
   .i_hw_write_enable  (1'b0),
   .i_hw_write_data    (<%= fill_0(width) %>),
   .i_hw_set           (<%= fill_0(width) %>),

data/lib/rggen/verilog/bit_field/type/w0t_w1t.erb

@@ -12,6 +12,8 @@ rggen_bit_field #(
   .i_sw_write_data    (<%= bit_field_write_data %>),
   .o_sw_read_data     (<%= bit_field_read_data %>),
   .o_sw_value         (<%= bit_field_value %>),
+  .o_write_trigger    (),
+  .o_read_trigger     (),
   .i_hw_write_enable  (1'b0),
   .i_hw_write_data    (<%= fill_0(width) %>),
   .i_hw_set           (<%= fill_0(width) %>),

data/lib/rggen/verilog/bit_field/type/wo_wo1_wotrg.erb

@@ -0,0 +1,27 @@
+rggen_bit_field #(
+  .WIDTH          (<%= width %>),
+  .INITIAL_VALUE  (<%= initial_value %>),
+  .SW_READ_ACTION (`RGGEN_READ_NONE),
+  .SW_WRITE_ONCE  (<%= write_once %>),
+  .TRIGGER        (<%= trigger %>)
+) u_bit_field (
+  .i_clk              (<%= clock %>),
+  .i_rst_n            (<%= reset %>),
+  .i_sw_valid         (<%= bit_field_valid %>),
+  .i_sw_read_mask     (<%= bit_field_read_mask %>),
+  .i_sw_write_enable  (1'b1),
+  .i_sw_write_mask    (<%= bit_field_write_mask %>),
+  .i_sw_write_data    (<%= bit_field_write_data %>),
+  .o_sw_read_data     (<%= bit_field_read_data %>),
+  .o_sw_value         (<%= bit_field_value %>),
+  .o_write_trigger    (<%= write_trigger_signal %>),
+  .o_read_trigger     (),
+  .i_hw_write_enable  (1'b0),
+  .i_hw_write_data    (<%= fill_0(width) %>),
+  .i_hw_set           (<%= fill_0(width) %>),
+  .i_hw_clear         (<%= fill_0(width) %>),
+  .i_value            (<%= fill_0(width) %>),
+  .i_mask             (<%= fill_1(width) %>),
+  .o_value            (<%= value_out[loop_variables] %>),
+  .o_value_unmasked   ()
+);

data/lib/rggen/verilog/bit_field/type/wo_wo1_wotrg.rb

@@ -0,0 +1,36 @@
+# frozen_string_literal: true
+
+RgGen.define_list_item_feature(:bit_field, :type, [:wo, :wo1, :wotrg]) do
+  verilog do
+    build do
+      output :value_out, {
+        name: "o_#{full_name}", width: width, array_size: array_size
+      }
+      if wotrg?
+        output :write_trigger, {
+          name: "o_#{full_name}_write_trigger", width: 1, array_size: array_size
+        }
+      end
+    end
+
+    main_code :bit_field, from_template: true
+
+    private
+
+    def wotrg?
+      bit_field.type == :wotrg
+    end
+
+    def write_once
+      bit_field.type == :wo1 && 1 || 0
+    end
+
+    def trigger
+      wotrg? && 1 || 0
+    end
+
+    def write_trigger_signal
+      wotrg? && write_trigger[loop_variables] || nil
+    end
+  end
+end

data/lib/rggen/verilog/bit_field/type/wrc_wrs.erb

@@ -12,6 +12,8 @@ rggen_bit_field #(
   .i_sw_write_data    (<%= bit_field_write_data %>),
   .o_sw_read_data     (<%= bit_field_read_data %>),
   .o_sw_value         (<%= bit_field_value %>),
+  .o_write_trigger    (),
+  .o_read_trigger     (),
   .i_hw_write_enable  (1'b0),
   .i_hw_write_data    (<%= fill_0(width) %>),
   .i_hw_set           (<%= fill_0(width) %>),

data/lib/rggen/verilog/bit_field/verilog_top.rb

@@ -60,7 +60,7 @@ RgGen.define_simple_feature(:bit_field, :verilog_top) do
       if !bit_field.initial_value_array?
         sized_initial_value
       elsif bit_field.fixed_initial_value?
-        concat(sized_initial_values)
+        merged_initial_values
       else
         repeat(bit_field.sequence_size, sized_initial_value)
       end
@@ -70,11 +70,13 @@ RgGen.define_simple_feature(:bit_field, :verilog_top) do
       hex(bit_field.register_map.initial_value, bit_field.width)
     end
 
-    def sized_initial_values
-      bit_field
-        .initial_values
-        .reverse
-        .map { |v| hex(v, bit_field.width) }
+    def merged_initial_values
+      value =
+        bit_field
+          .initial_values
+          .map.with_index { |v, i| v << (i * bit_field.width) }
+          .inject(:|)
+      hex(value, bit_field.width * bit_field.sequence_size)
     end
 
     def loop_size

data/lib/rggen/verilog/register/type/default.erb

@@ -5,7 +5,6 @@ rggen_default_register #(
   .OFFSET_ADDRESS (<%= offset_address %>),
   .BUS_WIDTH      (<%= bus_width %>),
   .DATA_WIDTH     (<%= width %>),
-  .VALID_BITS     (<%= valid_bits %>),
   .REGISTER_INDEX (<%= register_index %>)
 ) u_register (
   .i_clk                  (<%= clock %>),

data/lib/rggen/verilog/register/type/indirect.erb

@@ -5,7 +5,6 @@ rggen_indirect_register #(
   .OFFSET_ADDRESS       (<%= offset_address %>),
   .BUS_WIDTH            (<%= bus_width %>),
   .DATA_WIDTH           (<%= width %>),
-  .VALID_BITS           (<%= valid_bits %>),
   .INDIRECT_INDEX_WIDTH (<%= index_width %>),
   .INDIRECT_INDEX_VALUE (<%= concat(index_values) %>)
 ) u_register (

data/lib/rggen/verilog/register/type.rb

@@ -5,6 +5,11 @@ RgGen.define_list_feature(:register, :type) do
     base_feature do
       include RgGen::SystemVerilog::RTL::RegisterType
 
+      pre_code :register do |code|
+        register.bit_fields.empty? ||
+          (code << tie_off_unused_signals << nl)
+      end
+
       private
 
       def clock
@@ -78,6 +83,13 @@ RgGen.define_list_feature(:register, :type) do
       def bit_field_value
         register.bit_field_value
       end
+
+      def tie_off_unused_signals
+        macro_call(
+          'rggen_tie_off_unused_signals',
+          [width, valid_bits, bit_field_read_data, bit_field_value]
+        )
+      end
     end
 
     default_feature do

data/lib/rggen/verilog/register_block/protocol/wishbone.erb

@@ -0,0 +1,35 @@
+rggen_wishbone_adapter #(
+  .ADDRESS_WIDTH        (<%= address_width %>),
+  .LOCAL_ADDRESS_WIDTH  (<%= local_address_width %>),
+  .BUS_WIDTH            (<%= bus_width %>),
+  .REGISTERS            (<%= total_registers %>),
+  .PRE_DECODE           (<%= pre_decode %>),
+  .BASE_ADDRESS         (<%= base_address %>),
+  .BYTE_SIZE            (<%= byte_size %>),
+  .ERROR_STATUS         (<%= error_status %>),
+  .DEFAULT_READ_DATA    (<%= default_read_data %>),
+  .USE_STALL            (<%= use_stall %>)
+) u_adapter (
+  .i_clk                  (<%= register_block.clock %>),
+  .i_rst_n                (<%= register_block.reset %>),
+  .i_wb_cyc               (<%= wb_cyc %>),
+  .i_wb_stb               (<%= wb_stb %>),
+  .o_wb_stall             (<%= wb_stall %>),
+  .i_wb_adr               (<%= wb_adr %>),
+  .i_wb_we                (<%= wb_we %>),
+  .i_wb_dat               (<%= wb_dat_i %>),
+  .i_wb_sel               (<%= wb_sel %>),
+  .o_wb_ack               (<%= wb_ack %>),
+  .o_wb_err               (<%= wb_err %>),
+  .o_wb_rty               (<%= wb_rty %>),
+  .o_wb_dat               (<%= wb_dat_o %>),
+  .o_register_valid       (<%= register_block.register_valid %>),
+  .o_register_access      (<%= register_block.register_access %>),
+  .o_register_address     (<%= register_block.register_address %>),
+  .o_register_write_data  (<%= register_block.register_write_data %>),
+  .o_register_strobe      (<%= register_block.register_strobe %>),
+  .i_register_active      (<%= register_block.register_active %>),
+  .i_register_ready       (<%= register_block.register_ready %>),
+  .i_register_status      (<%= register_block.register_status %>),
+  .i_register_read_data   (<%= register_block.register_read_data %>)
+);

data/lib/rggen/verilog/register_block/protocol/wishbone.rb

@@ -0,0 +1,47 @@
+# frozen_string_literal: true
+
+RgGen.define_list_item_feature(:register_block, :protocol, :wishbone) do
+  verilog do
+    build do
+      parameter :use_stall, {
+        name: 'USE_STALL', default: 1
+      }
+
+      input :wb_cyc, {
+        name: 'i_wb_cyc', width: 1
+      }
+      input :wb_stb, {
+        name: 'i_wb_stb', width: 1
+      }
+      output :wb_stall, {
+        name: 'o_wb_stall', width: 1
+      }
+      input :wb_adr, {
+        name: 'i_wb_adr', width: address_width
+      }
+      input :wb_we, {
+        name: 'i_wb_we', width: 1
+      }
+      input :wb_dat_i, {
+        name: 'i_wb_dat', width: bus_width
+      }
+      input :wb_sel, {
+        name: 'i_wb_sel', width: bus_width / 8
+      }
+      output :wb_ack, {
+        name: 'o_wb_ack', width: 1
+      }
+      output :wb_err, {
+        name: 'o_wb_err', width: 1
+      }
+      output :wb_rty, {
+        name: 'o_wb_rty', width: 1
+      }
+      output :wb_dat_o, {
+        name: 'o_wb_dat', width: bus_width
+      }
+    end
+
+    main_code :register_block, from_template: true
+  end
+end

data/lib/rggen/verilog/version.rb

@@ -2,6 +2,6 @@
 
 module RgGen
   module Verilog
-    VERSION = '0.3.1'
+    VERSION = '0.4.1'
   end
 end

data/lib/rggen/verilog.rb

@@ -21,16 +21,18 @@ module RgGen
       plugin.files [
         'verilog/bit_field/type',
         'verilog/bit_field/type/rc_w0c_w1c_wc_woc',
-        'verilog/bit_field/type/ro',
+        'verilog/bit_field/type/ro_rotrg',
         'verilog/bit_field/type/rof',
+        'verilog/bit_field/type/rowo_rowotrg',
         'verilog/bit_field/type/rs_w0s_w1s_ws_wos',
-        'verilog/bit_field/type/rw_w1_wo_wo1',
+        'verilog/bit_field/type/rw_rwtrg_w1',
         'verilog/bit_field/type/rwc',
         'verilog/bit_field/type/rwe_rwl',
         'verilog/bit_field/type/rws',
         'verilog/bit_field/type/w0crs_w0src_w1crs_w1src_wcrs_wsrc',
         'verilog/bit_field/type/w0t_w1t',
         'verilog/bit_field/type/w0trg_w1trg',
+        'verilog/bit_field/type/wo_wo1_wotrg',
         'verilog/bit_field/type/wrc_wrs',
         'verilog/bit_field/verilog_top',
         'verilog/register/type',
@@ -40,6 +42,7 @@ module RgGen
         'verilog/register_block/protocol',
         'verilog/register_block/protocol/apb',
         'verilog/register_block/protocol/axi4lite',
+        'verilog/register_block/protocol/wishbone',
         'verilog/register_block/verilog_top',
         'verilog/register_file/verilog_top'
       ]

metadata

@@ -1,14 +1,14 @@
 --- !ruby/object:Gem::Specification
 name: rggen-verilog
 version: !ruby/object:Gem::Version
-  version: 0.3.1
+  version: 0.4.1
 platform: ruby
 authors:
 - Taichi Ishitani
 autorequire: 
 bindir: bin
 cert_chain: []
-date: 2021-05-16 00:00:00.000000000 Z
+date: 2022-06-07 00:00:00.000000000 Z
 dependencies:
 - !ruby/object:Gem::Dependency
   name: rggen-systemverilog
@@ -16,14 +16,14 @@ dependencies:
     requirements:
     - - ">="
       - !ruby/object:Gem::Version
-        version: 0.25.0
+        version: 0.26.0
   type: :runtime
   prerelease: false
   version_requirements: !ruby/object:Gem::Requirement
     requirements:
     - - ">="
       - !ruby/object:Gem::Version
-        version: 0.25.0
+        version: 0.26.0
 - !ruby/object:Gem::Dependency
   name: bundler
   requirement: !ruby/object:Gem::Requirement
@@ -52,14 +52,16 @@ files:
 - lib/rggen/verilog/bit_field/type.rb
 - lib/rggen/verilog/bit_field/type/rc_w0c_w1c_wc_woc.erb
 - lib/rggen/verilog/bit_field/type/rc_w0c_w1c_wc_woc.rb
-- lib/rggen/verilog/bit_field/type/ro.erb
-- lib/rggen/verilog/bit_field/type/ro.rb
+- lib/rggen/verilog/bit_field/type/ro_rotrg.erb
+- lib/rggen/verilog/bit_field/type/ro_rotrg.rb
 - lib/rggen/verilog/bit_field/type/rof.erb
 - lib/rggen/verilog/bit_field/type/rof.rb
+- lib/rggen/verilog/bit_field/type/rowo_rowotrg.erb
+- lib/rggen/verilog/bit_field/type/rowo_rowotrg.rb
 - lib/rggen/verilog/bit_field/type/rs_w0s_w1s_ws_wos.erb
 - lib/rggen/verilog/bit_field/type/rs_w0s_w1s_ws_wos.rb
-- lib/rggen/verilog/bit_field/type/rw_w1_wo_wo1.erb
-- lib/rggen/verilog/bit_field/type/rw_w1_wo_wo1.rb
+- lib/rggen/verilog/bit_field/type/rw_rwtrg_w1.erb
+- lib/rggen/verilog/bit_field/type/rw_rwtrg_w1.rb
 - lib/rggen/verilog/bit_field/type/rwc.erb
 - lib/rggen/verilog/bit_field/type/rwc.rb
 - lib/rggen/verilog/bit_field/type/rwe_rwl.erb
@@ -72,6 +74,8 @@ files:
 - lib/rggen/verilog/bit_field/type/w0t_w1t.rb
 - lib/rggen/verilog/bit_field/type/w0trg_w1trg.erb
 - lib/rggen/verilog/bit_field/type/w0trg_w1trg.rb
+- lib/rggen/verilog/bit_field/type/wo_wo1_wotrg.erb
+- lib/rggen/verilog/bit_field/type/wo_wo1_wotrg.rb
 - lib/rggen/verilog/bit_field/type/wrc_wrs.erb
 - lib/rggen/verilog/bit_field/type/wrc_wrs.rb
 - lib/rggen/verilog/bit_field/verilog_top.rb
@@ -90,6 +94,8 @@ files:
 - lib/rggen/verilog/register_block/protocol/apb.rb
 - lib/rggen/verilog/register_block/protocol/axi4lite.erb
 - lib/rggen/verilog/register_block/protocol/axi4lite.rb
+- lib/rggen/verilog/register_block/protocol/wishbone.erb
+- lib/rggen/verilog/register_block/protocol/wishbone.rb
 - lib/rggen/verilog/register_block/verilog_macros.erb
 - lib/rggen/verilog/register_block/verilog_top.rb
 - lib/rggen/verilog/register_file/verilog_top.rb
@@ -103,6 +109,7 @@ licenses:
 metadata:
   bug_tracker_uri: https://github.com/rggen/rggen-verilog/issues
   mailing_list_uri: https://groups.google.com/d/forum/rggen
+  rubygems_mfa_required: 'true'
   source_code_uri: https://github.com/rggen/rggen-verilog
   wiki_uri: https://github.com/rggen/rggen/wiki
 post_install_message: 
@@ -113,15 +120,15 @@ required_ruby_version: !ruby/object:Gem::Requirement
   requirements:
   - - ">="
     - !ruby/object:Gem::Version
-      version: '2.5'
+      version: '2.6'
 required_rubygems_version: !ruby/object:Gem::Requirement
   requirements:
   - - ">="
     - !ruby/object:Gem::Version
       version: '0'
 requirements: []
-rubygems_version: 3.2.3
+rubygems_version: 3.3.3
 signing_key: 
 specification_version: 4
-summary: rggen-verilog-0.3.1
+summary: rggen-verilog-0.4.1
 test_files: []

data/lib/rggen/verilog/bit_field/type/ro.rb

@@ -1,21 +0,0 @@
-# frozen_string_literal: true
-
-RgGen.define_list_item_feature(:bit_field, :type, :ro) do
-  verilog do
-    build do
-      unless bit_field.reference?
-        input :value_in, {
-          name: "i_#{full_name}", width: width, array_size: array_size
-        }
-      end
-    end
-
-    main_code :bit_field, from_template: true
-
-    private
-
-    def reference_or_value_in
-      bit_field.reference? && reference_bit_field || value_in[loop_variables]
-    end
-  end
-end

data/lib/rggen/verilog/bit_field/type/rw_w1_wo_wo1.rb

@@ -1,23 +0,0 @@
-# frozen_string_literal: true
-
-RgGen.define_list_item_feature(:bit_field, :type, [:rw, :w1, :wo, :wo1]) do
-  verilog do
-    build do
-      output :value_out, {
-        name: "o_#{full_name}", width: width, array_size: array_size
-      }
-    end
-
-    main_code :bit_field, from_template: true
-
-    private
-
-    def read_action
-      bit_field.readable? && '`RGGEN_READ_DEFAULT' || '`RGGEN_READ_NONE'
-    end
-
-    def write_once
-      [:w1, :wo1].include?(bit_field.type) && 1 || 0
-    end
-  end
-end