rggen-verilog 0.3.0 → 0.3.1

checksums.yaml

@@ -1,7 +1,7 @@
 ---
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+  metadata.gz: 7071aa165eea26e8fc35de9ce6fd6a026aa5def4b29075d709f2d3db6ad74f89
+  data.tar.gz: e805e0399138162446f3e5d3ea5b49a95b15167792acf650f142a14d9f3f53a3
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+  data.tar.gz: e285f84c954580f58eabed0e40a709d9bf1f76e3b2f96cafc8588f0807aecd379d983e621eb9e21c80a8b8eaaf60eaaa79998aa7d3cf2b783ba8c2c28981c84f

data/lib/rggen/verilog/bit_field/type/rs_w0s_w1s_ws_wos.erb

@@ -18,7 +18,7 @@ rggen_bit_field #(
   .i_hw_set           (<%= fill_0(width) %>),
   .i_hw_clear         (<%= clear[loop_variables] %>),
   .i_value            (<%= fill_0(width) %>),
-  .i_mask             (<%= mask %>),
+  .i_mask             (<%= fill_1(width) %>),
   .o_value            (<%= value_out[loop_variables] %>),
   .o_value_unmasked   ()
 );

data/lib/rggen/verilog/register_block/verilog_top.rb

@@ -88,7 +88,20 @@ RgGen.define_simple_feature(:register_block, :verilog_top) do
     end
 
     def ports
-      register_block.declarations[:port]
+      register_block
+        .declarations[:port]
+        .yield_self(&method(:sort_port_declarations))
+    end
+
+    def sort_port_declarations(declarations)
+      declarations
+        .partition(&method(:clock_or_reset?))
+        .flatten
+    end
+
+    def clock_or_reset?(declaration)
+      [clock.to_s, reset.to_s]
+        .any? { |port_name| declaration.include?(port_name) }
     end
 
     def variables

data/lib/rggen/verilog/setup.rb

@@ -1,9 +1,9 @@
 # frozen_string_literal: true
 
 require 'rggen/verilog'
-require 'rggen/systemverilog/rtl/setup'
 
 RgGen.register_plugin RgGen::Verilog do |builder|
+  builder.load_plugin 'rggen/systemverilog/rtl/setup'
   builder.enable :register_block, [:verilog_top]
   builder.enable :register_file, [:verilog_top]
   builder.enable :register, [:verilog_top]

data/lib/rggen/verilog/version.rb

@@ -2,6 +2,6 @@
 
 module RgGen
   module Verilog
-    VERSION = '0.3.0'
+    VERSION = '0.3.1'
   end
 end

metadata

@@ -1,14 +1,14 @@
 --- !ruby/object:Gem::Specification
 name: rggen-verilog
 version: !ruby/object:Gem::Version
-  version: 0.3.0
+  version: 0.3.1
 platform: ruby
 authors:
 - Taichi Ishitani
 autorequire: 
 bindir: bin
 cert_chain: []
-date: 2021-02-28 00:00:00.000000000 Z
+date: 2021-05-16 00:00:00.000000000 Z
 dependencies:
 - !ruby/object:Gem::Dependency
   name: rggen-systemverilog
@@ -123,5 +123,5 @@ requirements: []
 rubygems_version: 3.2.3
 signing_key: 
 specification_version: 4
-summary: rggen-verilog-0.3.0
+summary: rggen-verilog-0.3.1
 test_files: []