rggen-verilog 0.13.0 → 0.13.1

checksums.yaml

@@ -1,7 +1,7 @@
 ---
 SHA256:
-  metadata.gz: 17ad07e3cc71d30ed31d55a9221a7b2f9d258affbeccf2579f5edb69c8d5afae
-  data.tar.gz: f0be0a0ae406237db5afbd407ec5975b4d06ede79776209dd9196f8eeff64f24
+  metadata.gz: 5ce114ffe9df74368c2efa6381b5047dd1b9e986d7aece4ec65527e5688fef78
+  data.tar.gz: 3298da0b203debd3d77454ebc60a2b996481b67c09006d03573cc85656bd9af2
 SHA512:
-  metadata.gz: d1819a36b2dab2e3ed36f3fdb9da9d283518dad03f123386eb1c6621f640bfd23c3aa7c1b2608a699140dbde9fe30d7fa5144ad5961abcadc881257b40ce88d9
-  data.tar.gz: a49180376e08f244a4e66c77fbf03a700f6e9d4d3ce7af0147a0e2a88a95216d346359a9a151daa2fa8045bcafa33a53783ddf4484bdb8ab3eb7a5bd1dad2c0b
+  metadata.gz: 7d04d88597e9fccedf359e58688a7e3c7c7df59d50ce46658800842944f7b4dc351d0ab5a8578bc202bb4c72e09004f7c277abd054e864b813b7762b4c7b633a
+  data.tar.gz: 924003d8e400828f112a141bcfc3bcc9d4fa5926183bea7fd752e44cadc5e1951fc6c97b6144345f9bc1e3da951c21a45b58be480a139f9c86debdf728a097c8

data/lib/rggen/verilog/rtl/bit_field/type/custom.erb

@@ -4,16 +4,17 @@ rggen_bit_field #(
   .SW_READ_ACTION     (<%= sw_read_action %>),
   .SW_WRITE_ACTION    (<%= sw_write_action %>),
   .SW_WRITE_ONCE      (<%= write_once %>),
+  .HW_ACCESS          (<%= hw_access %>),
   .STORAGE            (<%= storage %>),
   .EXTERNAL_READ_DATA (<%= external_read_data %>),
   .TRIGGER            (<%= trigger %>)
 ) u_bit_field (
   .i_clk              (<%= clock %>),
   .i_rst_n            (<%= reset %>),
-  .i_sw_valid         (<%= bit_field_valid %>),
-  .i_sw_read_mask     (<%= bit_field_read_mask %>),
+  .i_sw_read_valid    (<%= bit_field_read_valid %>),
+  .i_sw_write_valid   (<%= bit_field_write_valid %>),
   .i_sw_write_enable  (1'b1),
-  .i_sw_write_mask    (<%= bit_field_write_mask %>),
+  .i_sw_mask          (<%= bit_field_mask %>),
   .i_sw_write_data    (<%= bit_field_write_data %>),
   .o_sw_read_data     (<%= bit_field_read_data %>),
   .o_sw_value         (<%= bit_field_value %>),

data/lib/rggen/verilog/rtl/bit_field/type/custom.rb

@@ -82,6 +82,15 @@ RgGen.define_list_item_feature(:bit_field, :type, :custom) do
       bit_field.sw_write_once? && 1 || 0
     end
 
+    def hw_access
+      values = [
+        bit_field.hw_clear? && 1 || 0,
+        bit_field.hw_set? && 1 || 0,
+        bit_field.hw_write? && 1 || 0
+      ]
+      "3'b#{values.join}"
+    end
+
     def storage
       external_read_data? && 0 || 1
     end

data/lib/rggen/verilog/rtl/bit_field/type/rc_w0c_w1c_wc_woc.erb

@@ -2,14 +2,16 @@ rggen_bit_field #(
   .WIDTH            (<%= width %>),
   .INITIAL_VALUE    (<%= initial_value %>),
   .SW_READ_ACTION   (<%= read_action %>),
-  .SW_WRITE_ACTION  (<%= write_action %>)
+  .SW_WRITE_ACTION  (<%= write_action %>),
+  .HW_ACCESS        (3'b010),
+  .EXTERNAL_MASK    (<%= external_mask %>)
 ) u_bit_field (
   .i_clk              (<%= clock %>),
   .i_rst_n            (<%= reset %>),
-  .i_sw_valid         (<%= bit_field_valid %>),
-  .i_sw_read_mask     (<%= bit_field_read_mask %>),
-  .i_sw_write_enable  (<%= write_enable %>),
-  .i_sw_write_mask    (<%= bit_field_write_mask %>),
+  .i_sw_read_valid    (<%= bit_field_read_valid %>),
+  .i_sw_write_valid   (<%= bit_field_write_valid %>),
+  .i_sw_write_enable  (1'b1),
+  .i_sw_mask          (<%= bit_field_mask %>),
   .i_sw_write_data    (<%= bit_field_write_data %>),
   .o_sw_read_data     (<%= bit_field_read_data %>),
   .o_sw_value         (<%= bit_field_value %>),

data/lib/rggen/verilog/rtl/bit_field/type/rc_w0c_w1c_wc_woc.rb

@@ -40,8 +40,8 @@ RgGen.define_list_item_feature(:bit_field, :type, [:rc, :w0c, :w1c, :wc, :woc])
       }[bit_field.type]
     end
 
-    def write_enable
-      bit_field.writable? && bin(1, 1) || bin(0, 1)
+    def external_mask
+      bit_field.reference? && bin(1, 1) || bin(0, 1)
     end
 
     def value_out_unmasked

data/lib/rggen/verilog/rtl/bit_field/type/ro_rotrg.erb

@@ -6,10 +6,10 @@ rggen_bit_field #(
 ) u_bit_field (
   .i_clk              (<%= clock %>),
   .i_rst_n            (<%= reset %>),
-  .i_sw_valid         (<%= bit_field_valid %>),
-  .i_sw_read_mask     (<%= bit_field_read_mask %>),
+  .i_sw_read_valid    (<%= bit_field_read_valid %>),
+  .i_sw_write_valid   (<%= bit_field_write_valid %>),
   .i_sw_write_enable  (1'b0),
-  .i_sw_write_mask    (<%= bit_field_write_mask %>),
+  .i_sw_mask          (<%= bit_field_mask %>),
   .i_sw_write_data    (<%= bit_field_write_data %>),
   .o_sw_read_data     (<%= bit_field_read_data %>),
   .o_sw_value         (<%= bit_field_value %>),

data/lib/rggen/verilog/rtl/bit_field/type/rof.erb

@@ -5,10 +5,10 @@ rggen_bit_field #(
 ) u_bit_field (
   .i_clk              (1'b0),
   .i_rst_n            (1'b0),
-  .i_sw_valid         (<%= bit_field_valid %>),
-  .i_sw_read_mask     (<%= bit_field_read_mask %>),
+  .i_sw_read_valid    (<%= bit_field_read_valid %>),
+  .i_sw_write_valid   (<%= bit_field_write_valid %>),
   .i_sw_write_enable  (1'b0),
-  .i_sw_write_mask    (<%= bit_field_write_mask %>),
+  .i_sw_mask          (<%= bit_field_mask %>),
   .i_sw_write_data    (<%= bit_field_write_data %>),
   .o_sw_read_data     (<%= bit_field_read_data %>),
   .o_sw_value         (<%= bit_field_value %>),

data/lib/rggen/verilog/rtl/bit_field/type/rohw.erb

@@ -1,14 +1,15 @@
 rggen_bit_field #(
   .WIDTH            (<%= width %>),
   .INITIAL_VALUE    (<%= initial_value %>),
-  .SW_WRITE_ACTION  (`RGGEN_WRITE_NONE)
+  .SW_WRITE_ACTION  (`RGGEN_WRITE_NONE),
+  .HW_ACCESS        (3'b001)
 ) u_bit_field (
   .i_clk              (<%= clock %>),
   .i_rst_n            (<%= reset %>),
-  .i_sw_valid         (<%= bit_field_valid %>),
-  .i_sw_read_mask     (<%= bit_field_read_mask %>),
+  .i_sw_read_valid    (<%= bit_field_read_valid %>),
+  .i_sw_write_valid   (<%= bit_field_write_valid %>),
   .i_sw_write_enable  (1'b1),
-  .i_sw_write_mask    (<%= bit_field_write_mask %>),
+  .i_sw_mask          (<%= bit_field_mask %>),
   .i_sw_write_data    (<%= bit_field_write_data %>),
   .o_sw_read_data     (<%= bit_field_read_data %>),
   .o_sw_value         (<%= bit_field_value %>),

data/lib/rggen/verilog/rtl/bit_field/type/row0trg_row1trg.erb

@@ -4,10 +4,10 @@ rggen_bit_field_w01trg #(
 ) u_bit_field (
   .i_clk              (<%= clock %>),
   .i_rst_n            (<%= reset %>),
-  .i_sw_valid         (<%= bit_field_valid %>),
-  .i_sw_read_mask     (<%= bit_field_read_mask %>),
+  .i_sw_read_valid    (<%= bit_field_read_valid %>),
+  .i_sw_write_valid   (<%= bit_field_write_valid %>),
   .i_sw_write_enable  (1'b1),
-  .i_sw_write_mask    (<%= bit_field_write_mask %>),
+  .i_sw_mask          (<%= bit_field_mask %>),
   .i_sw_write_data    (<%= bit_field_write_data %>),
   .o_sw_read_data     (<%= bit_field_read_data %>),
   .o_sw_value         (<%= bit_field_value %>),

data/lib/rggen/verilog/rtl/bit_field/type/rowo_rowotrg.erb

@@ -6,10 +6,10 @@ rggen_bit_field #(
 ) u_bit_field (
   .i_clk              (<%= clock %>),
   .i_rst_n            (<%= reset %>),
-  .i_sw_valid         (<%= bit_field_valid %>),
-  .i_sw_read_mask     (<%= bit_field_read_mask %>),
+  .i_sw_read_valid    (<%= bit_field_read_valid %>),
+  .i_sw_write_valid   (<%= bit_field_write_valid %>),
   .i_sw_write_enable  (1'b1),
-  .i_sw_write_mask    (<%= bit_field_write_mask %>),
+  .i_sw_mask          (<%= bit_field_mask %>),
   .i_sw_write_data    (<%= bit_field_write_data %>),
   .o_sw_read_data     (<%= bit_field_read_data %>),
   .o_sw_value         (<%= bit_field_value %>),

data/lib/rggen/verilog/rtl/bit_field/type/rs_w0s_w1s_ws_wos.erb

@@ -2,14 +2,15 @@ rggen_bit_field #(
   .WIDTH            (<%= width %>),
   .INITIAL_VALUE    (<%= initial_value %>),
   .SW_READ_ACTION   (<%= read_action %>),
-  .SW_WRITE_ACTION  (<%= write_action %>)
+  .SW_WRITE_ACTION  (<%= write_action %>),
+  .HW_ACCESS        (3'b100)
 ) u_bit_field (
   .i_clk              (<%= clock %>),
   .i_rst_n            (<%= reset %>),
-  .i_sw_valid         (<%= bit_field_valid %>),
-  .i_sw_read_mask     (<%= bit_field_read_mask %>),
-  .i_sw_write_enable  (<%= write_enable %>),
-  .i_sw_write_mask    (<%= bit_field_write_mask %>),
+  .i_sw_read_valid    (<%= bit_field_read_valid %>),
+  .i_sw_write_valid   (<%= bit_field_write_valid %>),
+  .i_sw_write_enable  (1'b1),
+  .i_sw_mask          (<%= bit_field_mask %>),
   .i_sw_write_data    (<%= bit_field_write_data %>),
   .o_sw_read_data     (<%= bit_field_read_data %>),
   .o_sw_value         (<%= bit_field_value %>),

data/lib/rggen/verilog/rtl/bit_field/type/rs_w0s_w1s_ws_wos.rb

@@ -34,9 +34,5 @@ RgGen.define_list_item_feature(:bit_field, :type, [:rs, :w0s, :w1s, :ws, :wos])
         wos: '`RGGEN_WRITE_SET'
       }[bit_field.type]
     end
-
-    def write_enable
-      bit_field.writable? && bin(1, 1) || bin(0, 1)
-    end
   end
 end

data/lib/rggen/verilog/rtl/bit_field/type/rw_rwtrg_w1.erb

@@ -6,10 +6,10 @@ rggen_bit_field #(
 ) u_bit_field (
   .i_clk              (<%= clock %>),
   .i_rst_n            (<%= reset %>),
-  .i_sw_valid         (<%= bit_field_valid %>),
-  .i_sw_read_mask     (<%= bit_field_read_mask %>),
+  .i_sw_read_valid    (<%= bit_field_read_valid %>),
+  .i_sw_write_valid   (<%= bit_field_write_valid %>),
   .i_sw_write_enable  (1'b1),
-  .i_sw_write_mask    (<%= bit_field_write_mask %>),
+  .i_sw_mask          (<%= bit_field_mask %>),
   .i_sw_write_data    (<%= bit_field_write_data %>),
   .o_sw_read_data     (<%= bit_field_read_data %>),
   .o_sw_value         (<%= bit_field_value %>),

data/lib/rggen/verilog/rtl/bit_field/type/rwc.erb

@@ -1,14 +1,15 @@
 rggen_bit_field #(
   .WIDTH          (<%= width %>),
   .INITIAL_VALUE  (<%= initial_value %>),
+  .HW_ACCESS      (3'b100),
   .HW_CLEAR_WIDTH (1)
 ) u_bit_field (
   .i_clk              (<%= clock %>),
   .i_rst_n            (<%= reset %>),
-  .i_sw_valid         (<%= bit_field_valid %>),
-  .i_sw_read_mask     (<%= bit_field_read_mask %>),
+  .i_sw_read_valid    (<%= bit_field_read_valid %>),
+  .i_sw_write_valid   (<%= bit_field_write_valid %>),
   .i_sw_write_enable  (1'b1),
-  .i_sw_write_mask    (<%= bit_field_write_mask %>),
+  .i_sw_mask          (<%= bit_field_mask %>),
   .i_sw_write_data    (<%= bit_field_write_data %>),
   .o_sw_read_data     (<%= bit_field_read_data %>),
   .o_sw_value         (<%= bit_field_value %>),

data/lib/rggen/verilog/rtl/bit_field/type/rwe_rwl.erb

@@ -1,14 +1,15 @@
 rggen_bit_field #(
   .WIDTH                    (<%= width %>),
   .INITIAL_VALUE            (<%= initial_value %>),
+  .SW_WRITE_CONTROL         (1'b1),
   .SW_WRITE_ENABLE_POLARITY (<%= control_signal_polarity %>)
 ) u_bit_field (
   .i_clk              (<%= clock %>),
   .i_rst_n            (<%= reset %>),
-  .i_sw_valid         (<%= bit_field_valid %>),
-  .i_sw_read_mask     (<%= bit_field_read_mask %>),
+  .i_sw_read_valid    (<%= bit_field_read_valid %>),
+  .i_sw_write_valid   (<%= bit_field_write_valid %>),
   .i_sw_write_enable  (<%= control_signal %>),
-  .i_sw_write_mask    (<%= bit_field_write_mask %>),
+  .i_sw_mask          (<%= bit_field_mask %>),
   .i_sw_write_data    (<%= bit_field_write_data %>),
   .o_sw_read_data     (<%= bit_field_read_data %>),
   .o_sw_value         (<%= bit_field_value %>),

data/lib/rggen/verilog/rtl/bit_field/type/rwhw.erb

@@ -1,13 +1,14 @@
 rggen_bit_field #(
   .WIDTH          (<%= width %>),
-  .INITIAL_VALUE  (<%= initial_value %>)
+  .INITIAL_VALUE  (<%= initial_value %>),
+  .HW_ACCESS      (3'b001)
 ) u_bit_field (
   .i_clk              (<%= clock %>),
   .i_rst_n            (<%= reset %>),
-  .i_sw_valid         (<%= bit_field_valid %>),
-  .i_sw_read_mask     (<%= bit_field_read_mask %>),
+  .i_sw_read_valid    (<%= bit_field_read_valid %>),
+  .i_sw_write_valid   (<%= bit_field_write_valid %>),
   .i_sw_write_enable  (1'b1),
-  .i_sw_write_mask    (<%= bit_field_write_mask %>),
+  .i_sw_mask          (<%= bit_field_mask %>),
   .i_sw_write_data    (<%= bit_field_write_data %>),
   .o_sw_read_data     (<%= bit_field_read_data %>),
   .o_sw_value         (<%= bit_field_value %>),

data/lib/rggen/verilog/rtl/bit_field/type/rws.erb

@@ -1,14 +1,15 @@
 rggen_bit_field #(
   .WIDTH          (<%= width %>),
   .INITIAL_VALUE  (<%= initial_value %>),
+  .HW_ACCESS      (3'b010),
   .HW_SET_WIDTH   (1)
 ) u_bit_field (
   .i_clk              (<%= clock %>),
   .i_rst_n            (<%= reset %>),
-  .i_sw_valid         (<%= bit_field_valid %>),
-  .i_sw_read_mask     (<%= bit_field_read_mask %>),
+  .i_sw_read_valid    (<%= bit_field_read_valid %>),
+  .i_sw_write_valid   (<%= bit_field_write_valid %>),
   .i_sw_write_enable  (1'b1),
-  .i_sw_write_mask    (<%= bit_field_write_mask %>),
+  .i_sw_mask          (<%= bit_field_mask %>),
   .i_sw_write_data    (<%= bit_field_write_data %>),
   .o_sw_read_data     (<%= bit_field_read_data %>),
   .o_sw_value         (<%= bit_field_value %>),

data/lib/rggen/verilog/rtl/bit_field/type/w0crs_w0src_w1crs_w1src_wcrs_wsrc.erb

@@ -6,10 +6,10 @@ rggen_bit_field #(
 ) u_bit_field (
   .i_clk              (<%= clock %>),
   .i_rst_n            (<%= reset %>),
-  .i_sw_valid         (<%= bit_field_valid %>),
-  .i_sw_read_mask     (<%= bit_field_read_mask %>),
+  .i_sw_read_valid    (<%= bit_field_read_valid %>),
+  .i_sw_write_valid   (<%= bit_field_write_valid %>),
   .i_sw_write_enable  (1'b1),
-  .i_sw_write_mask    (<%= bit_field_write_mask %>),
+  .i_sw_mask          (<%= bit_field_mask %>),
   .i_sw_write_data    (<%= bit_field_write_data %>),
   .o_sw_read_data     (<%= bit_field_read_data %>),
   .o_sw_value         (<%= bit_field_value %>),

data/lib/rggen/verilog/rtl/bit_field/type/w0t_w1t.erb

@@ -5,10 +5,10 @@ rggen_bit_field #(
 ) u_bit_field (
   .i_clk              (<%= clock %>),
   .i_rst_n            (<%= reset %>),
-  .i_sw_valid         (<%= bit_field_valid %>),
-  .i_sw_read_mask     (<%= bit_field_read_mask %>),
+  .i_sw_read_valid    (<%= bit_field_read_valid %>),
+  .i_sw_write_valid   (<%= bit_field_write_valid %>),
   .i_sw_write_enable  (1'b1),
-  .i_sw_write_mask    (<%= bit_field_write_mask %>),
+  .i_sw_mask          (<%= bit_field_mask %>),
   .i_sw_write_data    (<%= bit_field_write_data %>),
   .o_sw_read_data     (<%= bit_field_read_data %>),
   .o_sw_value         (<%= bit_field_value %>),

data/lib/rggen/verilog/rtl/bit_field/type/w0trg_w1trg.erb

@@ -4,10 +4,10 @@ rggen_bit_field_w01trg #(
 ) u_bit_field (
   .i_clk              (<%= clock %>),
   .i_rst_n            (<%= reset %>),
-  .i_sw_valid         (<%= bit_field_valid %>),
-  .i_sw_read_mask     (<%= bit_field_read_mask %>),
+  .i_sw_read_valid    (<%= bit_field_read_valid %>),
+  .i_sw_write_valid   (<%= bit_field_write_valid %>),
   .i_sw_write_enable  (1'b1),
-  .i_sw_write_mask    (<%= bit_field_write_mask %>),
+  .i_sw_mask          (<%= bit_field_mask %>),
   .i_sw_write_data    (<%= bit_field_write_data %>),
   .o_sw_read_data     (<%= bit_field_read_data %>),
   .o_sw_value         (<%= bit_field_value %>),

data/lib/rggen/verilog/rtl/bit_field/type/wo_wo1_wotrg.erb

@@ -7,10 +7,10 @@ rggen_bit_field #(
 ) u_bit_field (
   .i_clk              (<%= clock %>),
   .i_rst_n            (<%= reset %>),
-  .i_sw_valid         (<%= bit_field_valid %>),
-  .i_sw_read_mask     (<%= bit_field_read_mask %>),
+  .i_sw_read_valid    (<%= bit_field_read_valid %>),
+  .i_sw_write_valid   (<%= bit_field_write_valid %>),
   .i_sw_write_enable  (1'b1),
-  .i_sw_write_mask    (<%= bit_field_write_mask %>),
+  .i_sw_mask          (<%= bit_field_mask %>),
   .i_sw_write_data    (<%= bit_field_write_data %>),
   .o_sw_read_data     (<%= bit_field_read_data %>),
   .o_sw_value         (<%= bit_field_value %>),

data/lib/rggen/verilog/rtl/bit_field/type/wrc_wrs.erb

@@ -5,10 +5,10 @@ rggen_bit_field #(
 ) u_bit_field (
   .i_clk              (<%= clock %>),
   .i_rst_n            (<%= reset %>),
-  .i_sw_valid         (<%= bit_field_valid %>),
-  .i_sw_read_mask     (<%= bit_field_read_mask %>),
+  .i_sw_read_valid    (<%= bit_field_read_valid %>),
+  .i_sw_write_valid   (<%= bit_field_write_valid %>),
   .i_sw_write_enable  (1'b1),
-  .i_sw_write_mask    (<%= bit_field_write_mask %>),
+  .i_sw_mask          (<%= bit_field_mask %>),
   .i_sw_write_data    (<%= bit_field_write_data %>),
   .o_sw_read_data     (<%= bit_field_read_data %>),
   .o_sw_value         (<%= bit_field_value %>),

data/lib/rggen/verilog/rtl/bit_field/type.rb

@@ -44,16 +44,16 @@ RgGen.define_list_feature(:bit_field, :type) do
         register_block.reset
       end
 
-      def bit_field_valid
-        register.bit_field_valid
+      def bit_field_read_valid
+        register.bit_field_read_valid
       end
 
-      def bit_field_read_mask
-        register.bit_field_read_mask[lsb, width]
+      def bit_field_write_valid
+        register.bit_field_write_valid
       end
 
-      def bit_field_write_mask
-        register.bit_field_write_mask[lsb, width]
+      def bit_field_mask
+        register.bit_field_mask[lsb, width]
       end
 
       def bit_field_write_data

data/lib/rggen/verilog/rtl/register/type/default.erb

@@ -6,22 +6,22 @@ rggen_default_register #(
   .BUS_WIDTH      (<%= bus_width %>),
   .DATA_WIDTH     (<%= width %>)
 ) u_register (
-  .i_clk                  (<%= clock %>),
-  .i_rst_n                (<%= reset %>),
-  .i_register_valid       (<%= register_valid %>),
-  .i_register_access      (<%= register_access %>),
-  .i_register_address     (<%= register_address %>),
-  .i_register_write_data  (<%= register_write_data %>),
-  .i_register_strobe      (<%= register_strobe %>),
-  .o_register_active      (<%= register_active %>),
-  .o_register_ready       (<%= register_ready %>),
-  .o_register_status      (<%= register_status %>),
-  .o_register_read_data   (<%= register_read_data %>),
-  .o_register_value       (<%= register_value %>),
-  .o_bit_field_valid      (<%= bit_field_valid %>),
-  .o_bit_field_read_mask  (<%= bit_field_read_mask %>),
-  .o_bit_field_write_mask (<%= bit_field_write_mask %>),
-  .o_bit_field_write_data (<%= bit_field_write_data %>),
-  .i_bit_field_read_data  (<%= bit_field_read_data %>),
-  .i_bit_field_value      (<%= bit_field_value %>)
+  .i_clk                    (<%= clock %>),
+  .i_rst_n                  (<%= reset %>),
+  .i_register_valid         (<%= register_valid %>),
+  .i_register_access        (<%= register_access %>),
+  .i_register_address       (<%= register_address %>),
+  .i_register_write_data    (<%= register_write_data %>),
+  .i_register_strobe        (<%= register_strobe %>),
+  .o_register_active        (<%= register_active %>),
+  .o_register_ready         (<%= register_ready %>),
+  .o_register_status        (<%= register_status %>),
+  .o_register_read_data     (<%= register_read_data %>),
+  .o_register_value         (<%= register_value %>),
+  .o_bit_field_read_valid   (<%= bit_field_read_valid %>),
+  .o_bit_field_write_valid  (<%= bit_field_write_valid %>),
+  .o_bit_field_mask         (<%= bit_field_mask %>),
+  .o_bit_field_write_data   (<%= bit_field_write_data %>),
+  .i_bit_field_read_data    (<%= bit_field_read_data %>),
+  .i_bit_field_value        (<%= bit_field_value %>)
 );

data/lib/rggen/verilog/rtl/register/type/indirect.erb

@@ -7,23 +7,23 @@ rggen_indirect_register #(
   .DATA_WIDTH           (<%= width %>),
   .INDIRECT_MATCH_WIDTH (<%= index_match_width %>)
 ) u_register (
-  .i_clk                  (<%= clock %>),
-  .i_rst_n                (<%= reset %>),
-  .i_register_valid       (<%= register_valid %>),
-  .i_register_access      (<%= register_access %>),
-  .i_register_address     (<%= register_address %>),
-  .i_register_write_data  (<%= register_write_data %>),
-  .i_register_strobe      (<%= register_strobe %>),
-  .o_register_active      (<%= register_active %>),
-  .o_register_ready       (<%= register_ready %>),
-  .o_register_status      (<%= register_status %>),
-  .o_register_read_data   (<%= register_read_data %>),
-  .o_register_value       (<%= register_value %>),
-  .i_indirect_match       (<%= indirect_match %>),
-  .o_bit_field_valid      (<%= bit_field_valid %>),
-  .o_bit_field_read_mask  (<%= bit_field_read_mask %>),
-  .o_bit_field_write_mask (<%= bit_field_write_mask %>),
-  .o_bit_field_write_data (<%= bit_field_write_data %>),
-  .i_bit_field_read_data  (<%= bit_field_read_data %>),
-  .i_bit_field_value      (<%= bit_field_value %>)
+  .i_clk                    (<%= clock %>),
+  .i_rst_n                  (<%= reset %>),
+  .i_register_valid         (<%= register_valid %>),
+  .i_register_access        (<%= register_access %>),
+  .i_register_address       (<%= register_address %>),
+  .i_register_write_data    (<%= register_write_data %>),
+  .i_register_strobe        (<%= register_strobe %>),
+  .o_register_active        (<%= register_active %>),
+  .o_register_ready         (<%= register_ready %>),
+  .o_register_status        (<%= register_status %>),
+  .o_register_read_data     (<%= register_read_data %>),
+  .o_register_value         (<%= register_value %>),
+  .i_indirect_match         (<%= indirect_match %>),
+  .o_bit_field_read_valid   (<%= bit_field_read_valid %>),
+  .o_bit_field_write_valid  (<%= bit_field_write_valid %>),
+  .o_bit_field_mask         (<%= bit_field_mask %>),
+  .o_bit_field_write_data   (<%= bit_field_write_data %>),
+  .i_bit_field_read_data    (<%= bit_field_read_data %>),
+  .i_bit_field_value        (<%= bit_field_value %>)
 );

data/lib/rggen/verilog/rtl/register/type/rw.erb

@@ -6,22 +6,22 @@ rggen_default_register #(
   .BUS_WIDTH      (<%= bus_width %>),
   .DATA_WIDTH     (<%= width %>)
 ) u_register (
-  .i_clk                  (<%= clock %>),
-  .i_rst_n                (<%= reset %>),
-  .i_register_valid       (<%= register_valid %>),
-  .i_register_access      (<%= register_access %>),
-  .i_register_address     (<%= register_address %>),
-  .i_register_write_data  (<%= register_write_data %>),
-  .i_register_strobe      (<%= register_strobe %>),
-  .o_register_active      (<%= register_active %>),
-  .o_register_ready       (<%= register_ready %>),
-  .o_register_status      (<%= register_status %>),
-  .o_register_read_data   (<%= register_read_data %>),
-  .o_register_value       (<%= register_value %>),
-  .o_bit_field_valid      (<%= bit_field_valid %>),
-  .o_bit_field_read_mask  (<%= bit_field_read_mask %>),
-  .o_bit_field_write_mask (<%= bit_field_write_mask %>),
-  .o_bit_field_write_data (<%= bit_field_write_data %>),
-  .i_bit_field_read_data  (<%= bit_field_read_data %>),
-  .i_bit_field_value      (<%= bit_field_value %>)
+  .i_clk                    (<%= clock %>),
+  .i_rst_n                  (<%= reset %>),
+  .i_register_valid         (<%= register_valid %>),
+  .i_register_access        (<%= register_access %>),
+  .i_register_address       (<%= register_address %>),
+  .i_register_write_data    (<%= register_write_data %>),
+  .i_register_strobe        (<%= register_strobe %>),
+  .o_register_active        (<%= register_active %>),
+  .o_register_ready         (<%= register_ready %>),
+  .o_register_status        (<%= register_status %>),
+  .o_register_read_data     (<%= register_read_data %>),
+  .o_register_value         (<%= register_value %>),
+  .o_bit_field_read_valid   (<%= bit_field_read_valid %>),
+  .o_bit_field_write_valid  (<%= bit_field_write_valid %>),
+  .o_bit_field_mask         (<%= bit_field_mask %>),
+  .o_bit_field_write_data   (<%= bit_field_write_data %>),
+  .i_bit_field_read_data    (<%= bit_field_read_data %>),
+  .i_bit_field_value        (<%= bit_field_value %>)
 );

data/lib/rggen/verilog/rtl/register/type.rb

@@ -60,16 +60,16 @@ RgGen.define_list_feature(:register, :type) do
         register_block.register_value[[register.index], 0, width]
       end
 
-      def bit_field_valid
-        register.bit_field_valid
+      def bit_field_read_valid
+        register.bit_field_read_valid
       end
 
-      def bit_field_read_mask
-        register.bit_field_read_mask
+      def bit_field_write_valid
+        register.bit_field_write_valid
       end
 
-      def bit_field_write_mask
-        register.bit_field_write_mask
+      def bit_field_mask
+        register.bit_field_mask
       end
 
       def bit_field_write_data

data/lib/rggen/verilog/rtl/register/verilog_top.rb

@@ -6,14 +6,14 @@ RgGen.define_simple_feature(:register, :verilog_top) do
 
     build do
       unless register.bit_fields.empty?
-        wire :bit_field_valid, {
-          name: 'w_bit_field_valid', width: 1
+        wire :bit_field_read_valid, {
+          name: 'w_bit_field_read_valid', width: 1
         }
-        wire :bit_field_read_mask, {
-          name: 'w_bit_field_read_mask', width: register.width
+        wire :bit_field_write_valid, {
+          name: 'w_bit_field_write_valid', width: 1
         }
-        wire :bit_field_write_mask, {
-          name: 'w_bit_field_write_mask', width: register.width
+        wire :bit_field_mask, {
+          name: 'w_bit_field_mask', width: register.width
         }
         wire :bit_field_write_data, {
           name: 'w_bit_field_write_data', width: register.width

data/lib/rggen/verilog/version.rb

@@ -2,6 +2,6 @@
 
 module RgGen
   module Verilog
-    VERSION = '0.13.0'
+    VERSION = '0.13.1'
   end
 end

metadata

@@ -1,13 +1,13 @@
 --- !ruby/object:Gem::Specification
 name: rggen-verilog
 version: !ruby/object:Gem::Version
-  version: 0.13.0
+  version: 0.13.1
 platform: ruby
 authors:
 - Taichi Ishitani
 bindir: bin
 cert_chain: []
-date: 2025-02-19 00:00:00.000000000 Z
+date: 2025-06-01 00:00:00.000000000 Z
 dependencies:
 - !ruby/object:Gem::Dependency
   name: rggen-systemverilog
@@ -15,14 +15,14 @@ dependencies:
     requirements:
     - - ">="
       - !ruby/object:Gem::Version
-        version: 0.35.0
+        version: 0.35.1
   type: :runtime
   prerelease: false
   version_requirements: !ruby/object:Gem::Requirement
     requirements:
     - - ">="
       - !ruby/object:Gem::Version
-        version: 0.35.0
+        version: 0.35.1
 description: Verilog write plugin for RgGen
 email:
 - rggen@googlegroups.com
@@ -133,5 +133,5 @@ required_rubygems_version: !ruby/object:Gem::Requirement
 requirements: []
 rubygems_version: 3.6.2
 specification_version: 4
-summary: rggen-verilog-0.13.0
+summary: rggen-verilog-0.13.1
 test_files: []