rggen-verilog 0.12.0 → 0.13.0

checksums.yaml

@@ -1,7 +1,7 @@
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data/README.md

@@ -1,6 +1,6 @@
 [![Gem Version](https://badge.fury.io/rb/rggen-verilog.svg)](https://badge.fury.io/rb/rggen-verilog)
 [![CI](https://github.com/rggen/rggen-verilog/workflows/CI/badge.svg)](https://github.com/rggen/rggen-verilog/actions?query=workflow%3ACI)
-[![Maintainability](https://api.codeclimate.com/v1/badges/7a4090f4a7c21d29036c/maintainability)](https://codeclimate.com/github/rggen/rggen-verilog/maintainability)
+[![Maintainability](https://qlty.sh/badges/93f1f04b-d863-4f44-a968-2f2721a8f3de/maintainability.svg)](https://qlty.sh/gh/rggen/projects/rggen-verilog)
 [![codecov](https://codecov.io/gh/rggen/rggen-verilog/branch/master/graph/badge.svg)](https://codecov.io/gh/rggen/rggen-verilog)
 [![Gitter](https://badges.gitter.im/rggen/rggen.svg)](https://gitter.im/rggen/rggen?utm_source=badge&utm_medium=badge&utm_campaign=pr-badge)
 

data/lib/rggen/verilog/rtl/bit_field/type.rb

@@ -23,8 +23,8 @@ RgGen.define_list_feature(:bit_field, :type) do
 
       def initial_value
         if multiple_initial_values?
-          index = bit_field.local_index
-          total_bits = width * bit_field.sequence_size
+          index = bit_field.flat_loop_index
+          total_bits = width * array_size.inject(:*)
           macro_call('rggen_slice', [bit_field.initial_value, total_bits, width, index])
         else
           bit_field.initial_value
@@ -32,7 +32,8 @@ RgGen.define_list_feature(:bit_field, :type) do
       end
 
       def multiple_initial_values?
-        bit_field.initial_value_array? && bit_field.sequence_size > 1
+        bit_field.initial_value_array? &&
+          (array_size.size > 1 || array_size.first > 1)
       end
 
       def clock
@@ -75,7 +76,7 @@ RgGen.define_list_feature(:bit_field, :type) do
         bit_field.reference? &&
           bit_field
             .find_reference(register_block.bit_fields)
-            .value(bit_field.local_indices, bit_field.reference_width)
+            .value(bit_field.local_indexes, bit_field.reference_width)
       end
 
       def loop_variables

data/lib/rggen/verilog/rtl/bit_field/verilog_top.rb

@@ -11,7 +11,7 @@ RgGen.define_simple_feature(:bit_field, :verilog_top) do
       if parameterized_initial_value?
         parameter :initial_value, {
           name: initial_value_name, width: bit_field.width,
-          array_size: initial_value_array_size, default: initial_value_rhs
+          array_size: initial_value_size, default: initial_value_rhs
         }
       else
         define_accessor_for_initial_value
@@ -34,7 +34,7 @@ RgGen.define_simple_feature(:bit_field, :verilog_top) do
     private
 
     def register_value(offsets, lsb, width)
-      index = register.index(offsets || register.local_indices)
+      index = register.index(offsets || register.local_indexes)
       register_block.register_value[[index], lsb, width]
     end
 
@@ -52,8 +52,8 @@ RgGen.define_simple_feature(:bit_field, :verilog_top) do
       "#{bit_field.full_name('_')}_initial_value".upcase
     end
 
-    def initial_value_array_size
-      bit_field.initial_value_array? && [bit_field.sequence_size] || nil
+    def initial_value_size
+      bit_field.initial_value_array? && array_size || nil
     end
 
     def initial_value_rhs
@@ -62,7 +62,8 @@ RgGen.define_simple_feature(:bit_field, :verilog_top) do
       elsif bit_field.fixed_initial_value?
         merged_initial_values
       else
-        repeat(bit_field.sequence_size, sized_initial_value)
+        size = array_size.inject(:*)
+        repeat(size, sized_initial_value)
       end
     end
 
@@ -71,12 +72,12 @@ RgGen.define_simple_feature(:bit_field, :verilog_top) do
     end
 
     def merged_initial_values
-      value =
-        bit_field
-          .initial_values
+      initial_values = bit_field.initial_values(flatten: true)
+      merged_value =
+        initial_values
           .map.with_index { |v, i| v << (i * bit_field.width) }
           .inject(:|)
-      hex(value, bit_field.width * bit_field.sequence_size)
+      hex(merged_value, bit_field.width * initial_values.size)
     end
 
     def loop_size

data/lib/rggen/verilog/rtl/register_block/protocol/avalon.erb

@@ -0,0 +1,32 @@
+rggen_avalon_adapter #(
+  .ADDRESS_WIDTH        (<%= address_width %>),
+  .LOCAL_ADDRESS_WIDTH  (<%= local_address_width %>),
+  .BUS_WIDTH            (<%= bus_width %>),
+  .REGISTERS            (<%= total_registers %>),
+  .PRE_DECODE           (<%= pre_decode %>),
+  .BASE_ADDRESS         (<%= base_address %>),
+  .BYTE_SIZE            (<%= byte_size %>),
+  .ERROR_STATUS         (<%= error_status %>),
+  .DEFAULT_READ_DATA    (<%= default_read_data %>),
+  .INSERT_SLICER        (<%= insert_slicer %>)
+) u_adapter (
+  .i_clk                  (<%= register_block.clock %>),
+  .i_rst_n                (<%= register_block.reset %>),
+  .i_read                 (<%= read %>),
+  .i_write                (<%= write %>),
+  .i_address              (<%= address %>),
+  .i_byteenable           (<%= byteenable %>),
+  .i_writedata            (<%= writedata %>),
+  .o_waitrequest          (<%= waitrequest %>),
+  .o_response             (<%= response %>),
+  .o_readdata             (<%= readdata %>),
+  .o_register_valid       (<%= register_block.register_valid %>),
+  .o_register_access      (<%= register_block.register_access %>),
+  .o_register_address     (<%= register_block.register_address %>),
+  .o_register_write_data  (<%= register_block.register_write_data %>),
+  .o_register_strobe      (<%= register_block.register_strobe %>),
+  .i_register_active      (<%= register_block.register_active %>),
+  .i_register_ready       (<%= register_block.register_ready %>),
+  .i_register_status      (<%= register_block.register_status %>),
+  .i_register_read_data   (<%= register_block.register_read_data %>)
+);

data/lib/rggen/verilog/rtl/register_block/protocol/avalon.rb

@@ -0,0 +1,34 @@
+# frozen_string_literal: true
+
+RgGen.define_list_item_feature(:register_block, :protocol, :avalon) do
+  verilog_rtl do
+    build do
+      input :read, {
+        name: 'i_read', width: 1
+      }
+      input :write, {
+        name: 'i_write', width: 1
+      }
+      input :address, {
+        name: 'i_address', width: address_width
+      }
+      input :byteenable, {
+        name: 'i_byteenable', width: bus_width / 8
+      }
+      input :writedata, {
+        name: 'i_writedata', width: bus_width
+      }
+      output :waitrequest, {
+        name: 'o_waitrequest', width: 1
+      }
+      output :response, {
+        name: 'o_response', width: 2
+      }
+      output :readdata, {
+        name: 'o_readdata', width: bus_width
+      }
+    end
+
+    main_code :register_block, from_template: true
+  end
+end

data/lib/rggen/verilog/rtl/register_block/protocol/native.erb

@@ -7,6 +7,7 @@ rggen_native_adapter #(
   .PRE_DECODE           (<%= pre_decode %>),
   .BASE_ADDRESS         (<%= base_address %>),
   .BYTE_SIZE            (<%= byte_size %>),
+  .USE_READ_STROBE      (<%= use_read_strobe %>),
   .ERROR_STATUS         (<%= error_status %>),
   .DEFAULT_READ_DATA    (<%= default_read_data %>),
   .INSERT_SLICER        (<%= insert_slicer %>)

data/lib/rggen/verilog/rtl/register_block/protocol/native.rb

@@ -6,6 +6,9 @@ RgGen.define_list_item_feature(:register_block, :protocol, :native) do
       parameter :strobe_width, {
         name: 'STROBE_WIDTH', default: bus_width / 8
       }
+      parameter :use_read_strobe, {
+        name: 'USE_READ_STROBE', default: 0
+      }
 
       input :valid, {
         name: 'i_csrbus_valid', width: 1

data/lib/rggen/verilog/version.rb

@@ -2,6 +2,6 @@
 
 module RgGen
   module Verilog
-    VERSION = '0.12.0'
+    VERSION = '0.13.0'
   end
 end

data/lib/rggen/verilog.rb

@@ -26,6 +26,7 @@ RgGen.setup_plugin :'rggen-verilog' do |plugin|
     'verilog/rtl/register_block/protocol',
     'verilog/rtl/register_block/protocol/apb',
     'verilog/rtl/register_block/protocol/axi4lite',
+    'verilog/rtl/register_block/protocol/avalon',
     'verilog/rtl/register_block/protocol/wishbone',
     'verilog/rtl/register_block/protocol/native',
     'verilog/rtl/register_file/verilog_top',

metadata

@@ -1,13 +1,13 @@
 --- !ruby/object:Gem::Specification
 name: rggen-verilog
 version: !ruby/object:Gem::Version
-  version: 0.12.0
+  version: 0.13.0
 platform: ruby
 authors:
 - Taichi Ishitani
 bindir: bin
 cert_chain: []
-date: 2025-01-23 00:00:00.000000000 Z
+date: 2025-02-19 00:00:00.000000000 Z
 dependencies:
 - !ruby/object:Gem::Dependency
   name: rggen-systemverilog
@@ -15,14 +15,14 @@ dependencies:
     requirements:
     - - ">="
       - !ruby/object:Gem::Version
-        version: 0.34.0
+        version: 0.35.0
   type: :runtime
   prerelease: false
   version_requirements: !ruby/object:Gem::Requirement
     requirements:
     - - ">="
       - !ruby/object:Gem::Version
-        version: 0.34.0
+        version: 0.35.0
 description: Verilog write plugin for RgGen
 email:
 - rggen@googlegroups.com
@@ -89,6 +89,8 @@ files:
 - lib/rggen/verilog/rtl/register_block/protocol.rb
 - lib/rggen/verilog/rtl/register_block/protocol/apb.erb
 - lib/rggen/verilog/rtl/register_block/protocol/apb.rb
+- lib/rggen/verilog/rtl/register_block/protocol/avalon.erb
+- lib/rggen/verilog/rtl/register_block/protocol/avalon.rb
 - lib/rggen/verilog/rtl/register_block/protocol/axi4lite.erb
 - lib/rggen/verilog/rtl/register_block/protocol/axi4lite.rb
 - lib/rggen/verilog/rtl/register_block/protocol/native.erb
@@ -131,5 +133,5 @@ required_rubygems_version: !ruby/object:Gem::Requirement
 requirements: []
 rubygems_version: 3.6.2
 specification_version: 4
-summary: rggen-verilog-0.12.0
+summary: rggen-verilog-0.13.0
 test_files: []