rggen-verilog 0.11.1 → 0.13.0
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- checksums.yaml +4 -4
- data/LICENSE +1 -1
- data/README.md +2 -2
- data/lib/rggen/verilog/register_map/keyword_checker.rb +43 -0
- data/lib/rggen/verilog/register_map/name.rb +9 -0
- data/lib/rggen/verilog/rtl/bit_field/type/custom.rb +8 -8
- data/lib/rggen/verilog/rtl/bit_field/type/rc_w0c_w1c_wc_woc.rb +3 -3
- data/lib/rggen/verilog/rtl/bit_field/type/ro_rotrg.rb +2 -2
- data/lib/rggen/verilog/rtl/bit_field/type/rohw.rb +3 -3
- data/lib/rggen/verilog/rtl/bit_field/type/row0trg_row1trg.rb +2 -2
- data/lib/rggen/verilog/rtl/bit_field/type/rowo_rowotrg.rb +4 -4
- data/lib/rggen/verilog/rtl/bit_field/type/rs_w0s_w1s_ws_wos.rb +2 -2
- data/lib/rggen/verilog/rtl/bit_field/type/rw_rwtrg_w1.rb +3 -3
- data/lib/rggen/verilog/rtl/bit_field/type/rwc.rb +2 -2
- data/lib/rggen/verilog/rtl/bit_field/type/rwe_rwl.rb +2 -2
- data/lib/rggen/verilog/rtl/bit_field/type/rwhw.rb +3 -3
- data/lib/rggen/verilog/rtl/bit_field/type/rws.rb +2 -2
- data/lib/rggen/verilog/rtl/bit_field/type/w0crs_w0src_w1crs_w1src_wcrs_wsrc.rb +1 -1
- data/lib/rggen/verilog/rtl/bit_field/type/w0t_w1t.rb +1 -1
- data/lib/rggen/verilog/rtl/bit_field/type/w0trg_w1trg.rb +1 -1
- data/lib/rggen/verilog/rtl/bit_field/type/wo_wo1_wotrg.rb +2 -2
- data/lib/rggen/verilog/rtl/bit_field/type/wrc_wrs.rb +1 -1
- data/lib/rggen/verilog/rtl/bit_field/type.rb +5 -4
- data/lib/rggen/verilog/rtl/bit_field/verilog_top.rb +10 -9
- data/lib/rggen/verilog/rtl/feature.rb +5 -5
- data/lib/rggen/verilog/rtl/register/type/external.rb +1 -1
- data/lib/rggen/verilog/rtl/register_block/protocol/avalon.erb +32 -0
- data/lib/rggen/verilog/rtl/register_block/protocol/avalon.rb +34 -0
- data/lib/rggen/verilog/rtl/register_block/protocol/native.erb +34 -0
- data/lib/rggen/verilog/rtl/register_block/protocol/native.rb +41 -0
- data/lib/rggen/verilog/rtl/register_block/protocol.rb +3 -3
- data/lib/rggen/verilog/rtl/register_block/verilog_top.rb +1 -1
- data/lib/rggen/verilog/utility.rb +2 -2
- data/lib/rggen/verilog/version.rb +1 -1
- data/lib/rggen/verilog.rb +7 -0
- metadata +13 -10
checksums.yaml
CHANGED
@@ -1,7 +1,7 @@
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---
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SHA256:
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-
metadata.gz:
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data.tar.gz:
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metadata.gz: 17ad07e3cc71d30ed31d55a9221a7b2f9d258affbeccf2579f5edb69c8d5afae
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data.tar.gz: f0be0a0ae406237db5afbd407ec5975b4d06ede79776209dd9196f8eeff64f24
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SHA512:
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metadata.gz:
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data.tar.gz:
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metadata.gz: d1819a36b2dab2e3ed36f3fdb9da9d283518dad03f123386eb1c6621f640bfd23c3aa7c1b2608a699140dbde9fe30d7fa5144ad5961abcadc881257b40ce88d9
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data.tar.gz: a49180376e08f244a4e66c77fbf03a700f6e9d4d3ce7af0147a0e2a88a95216d346359a9a151daa2fa8045bcafa33a53783ddf4484bdb8ab3eb7a5bd1dad2c0b
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data/LICENSE
CHANGED
@@ -1,6 +1,6 @@
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The MIT License (MIT)
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Copyright (c) 2020-
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Copyright (c) 2020-2025 Taichi Ishitani
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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data/README.md
CHANGED
@@ -1,6 +1,6 @@
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[![Gem Version](https://badge.fury.io/rb/rggen-verilog.svg)](https://badge.fury.io/rb/rggen-verilog)
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[![CI](https://github.com/rggen/rggen-verilog/workflows/CI/badge.svg)](https://github.com/rggen/rggen-verilog/actions?query=workflow%3ACI)
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[![Maintainability](https://
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[![Maintainability](https://qlty.sh/badges/93f1f04b-d863-4f44-a968-2f2721a8f3de/maintainability.svg)](https://qlty.sh/gh/rggen/projects/rggen-verilog)
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[![codecov](https://codecov.io/gh/rggen/rggen-verilog/branch/master/graph/badge.svg)](https://codecov.io/gh/rggen/rggen-verilog)
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[![Gitter](https://badges.gitter.im/rggen/rggen.svg)](https://gitter.im/rggen/rggen?utm_source=badge&utm_medium=badge&utm_campaign=pr-badge)
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@@ -68,7 +68,7 @@ Feedbacks, bus reports, questions and etc. are welcome! You can post them bu usi
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## Copyright & License
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-
Copyright © 2020-
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Copyright © 2020-2025 Taichi Ishitani. RgGen::Verilog is licensed under the [MIT License](https://opensource.org/licenses/MIT), see [LICENSE](LICENSE) for futher details.
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## Code of Conduct
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@@ -0,0 +1,43 @@
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1
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+
# frozen_string_literal: true
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module RgGen
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module Verilog
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module RegisterMap
|
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module KeywordChecker
|
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VERILOG_KEYWORDS = [
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+
'always', 'and', 'assign', 'automatic', 'begin', 'buf', 'bufif0', 'bufif1',
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'case', 'casex', 'casez', 'cell', 'cmos', 'config', 'deassign', 'default',
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'defparam', 'design', 'disable', 'edge', 'else', 'end', 'endcase', 'endconfig',
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'endfunction', 'endgenerate', 'endmodule', 'endprimitive', 'endspecify',
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'endtable', 'endtask', 'event', 'for', 'force', 'forever', 'fork', 'function',
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'generate', 'genvar', 'highz0', 'highz1', 'if', 'ifnone', 'incdir', 'include',
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'initial', 'inout', 'input', 'instance', 'integer', 'join', 'large', 'liblist',
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'library', 'localparam', 'macromodule', 'medium', 'module', 'nand', 'negedge',
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'nmos', 'nor', 'noshowcancelled', 'not', 'notif0', 'notif1', 'or', 'output',
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'parameter', 'pmos', 'posedge', 'primitive', 'pull0', 'pull1', 'pulldown',
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'pullup', 'pulsestyle_onevent', 'pulsestyle_ondetect', 'rcmos', 'real',
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'realtime', 'reg', 'release', 'repeat', 'rnmos', 'rpmos', 'rtran', 'rtranif0',
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'rtranif1', 'scalared', 'showcancelled', 'signed', 'small', 'specify',
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'specparam', 'strong0', 'strong1', 'supply0', 'supply1', 'table', 'task',
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'time', 'tran', 'tranif0', 'tranif1', 'tri', 'tri0', 'tri1', 'triand', 'trior',
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'trireg', 'unsigned', 'use', 'uwire', 'vectored', 'wait', 'wand', 'weak0',
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'weak1', 'while', 'wire', 'wor', 'xnor', 'xor'
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].freeze
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def self.included(klass)
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klass.class_eval do
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verify(:feature, prepend: true) do
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error_condition do
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@name && VERILOG_KEYWORDS.include?(@name)
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end
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message do
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layer_name = component.layer.to_s.sub('_', ' ')
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"verilog keyword is not allowed for #{layer_name} name: #{@name}"
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end
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end
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end
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end
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end
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end
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end
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end
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@@ -5,39 +5,39 @@ RgGen.define_list_item_feature(:bit_field, :type, :custom) do
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build do
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if external_read_data?
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input :value_in, {
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-
name: "i_#{full_name}", width
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+
name: "i_#{full_name}", width:, array_size:
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}
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else
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output :value_out, {
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-
name: "o_#{full_name}", width
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+
name: "o_#{full_name}", width:, array_size:
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}
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end
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if bit_field.hw_write?
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input :hw_write_enable, {
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-
name: "i_#{full_name}_hw_write_enable", width: 1, array_size:
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name: "i_#{full_name}_hw_write_enable", width: 1, array_size:
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}
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input :hw_write_data, {
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name: "i_#{full_name}_hw_write_data", width
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name: "i_#{full_name}_hw_write_data", width:, array_size:
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}
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end
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if bit_field.hw_set?
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input :hw_set, {
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name: "i_#{full_name}_hw_set", width
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+
name: "i_#{full_name}_hw_set", width:, array_size:
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}
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end
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if bit_field.hw_clear?
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input :hw_clear, {
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-
name: "i_#{full_name}_hw_clear", width
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+
name: "i_#{full_name}_hw_clear", width:, array_size:
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}
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end
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if bit_field.write_trigger?
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output :write_trigger, {
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-
name: "o_#{full_name}_write_trigger", width: 1, array_size:
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+
name: "o_#{full_name}_write_trigger", width: 1, array_size:
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}
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end
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if bit_field.read_trigger?
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output :read_trigger, {
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-
name: "o_#{full_name}_read_trigger", width: 1, array_size:
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name: "o_#{full_name}_read_trigger", width: 1, array_size:
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}
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end
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end
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@@ -4,14 +4,14 @@ RgGen.define_list_item_feature(:bit_field, :type, [:rc, :w0c, :w1c, :wc, :woc])
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verilog_rtl do
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build do
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input :set, {
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-
name: "i_#{full_name}_set", width
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+
name: "i_#{full_name}_set", width:, array_size:
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}
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output :value_out, {
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-
name: "o_#{full_name}", width
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+
name: "o_#{full_name}", width:, array_size:
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}
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if bit_field.reference?
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output :value_unmasked, {
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-
name: "o_#{full_name}_unmasked", width
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+
name: "o_#{full_name}_unmasked", width:, array_size:
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}
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end
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end
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@@ -5,12 +5,12 @@ RgGen.define_list_item_feature(:bit_field, :type, [:ro, :rotrg]) do
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build do
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unless bit_field.reference?
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input :value_in, {
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-
name: "i_#{full_name}", width
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+
name: "i_#{full_name}", width:, array_size:
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}
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end
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if rotrg?
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output :read_trigger, {
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-
name: "o_#{full_name}_read_trigger", width: 1, array_size:
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+
name: "o_#{full_name}_read_trigger", width: 1, array_size:
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}
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end
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end
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@@ -5,14 +5,14 @@ RgGen.define_list_item_feature(:bit_field, :type, :rohw) do
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build do
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unless bit_field.reference?
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input :valid, {
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-
name: "i_#{full_name}_valid", width: 1, array_size:
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+
name: "i_#{full_name}_valid", width: 1, array_size:
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}
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end
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input :value_in, {
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-
name: "i_#{full_name}", width
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+
name: "i_#{full_name}", width:, array_size:
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}
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output :value_out, {
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-
name: "o_#{full_name}", width
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+
name: "o_#{full_name}", width:, array_size:
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}
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end
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@@ -5,11 +5,11 @@ RgGen.define_list_item_feature(:bit_field, :type, [:row0trg, :row1trg]) do
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build do
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unless bit_field.reference?
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input :value_in, {
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-
name: "i_#{full_name}", width
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+
name: "i_#{full_name}", width:, array_size:
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}
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end
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output :trigger, {
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-
name: "o_#{full_name}_trigger", width
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+
name: "o_#{full_name}_trigger", width:, array_size:
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}
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14
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end
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@@ -4,19 +4,19 @@ RgGen.define_list_item_feature(:bit_field, :type, [:rowo, :rowotrg]) do
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verilog_rtl do
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build do
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output :value_out, {
|
7
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-
name: "o_#{full_name}", width
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7
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+
name: "o_#{full_name}", width:, array_size:
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}
|
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9
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unless bit_field.reference?
|
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input :value_in, {
|
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-
name: "i_#{full_name}", width
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+
name: "i_#{full_name}", width:, array_size:
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}
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end
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if rowotrg?
|
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output :write_trigger, {
|
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-
name: "o_#{full_name}_write_trigger", width: 1, array_size:
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+
name: "o_#{full_name}_write_trigger", width: 1, array_size:
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}
|
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output :read_trigger, {
|
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-
name: "o_#{full_name}_read_trigger", width: 1, array_size:
|
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+
name: "o_#{full_name}_read_trigger", width: 1, array_size:
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}
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end
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end
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@@ -4,10 +4,10 @@ RgGen.define_list_item_feature(:bit_field, :type, [:rs, :w0s, :w1s, :ws, :wos])
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4
4
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verilog_rtl do
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5
5
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build do
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6
6
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input :clear, {
|
7
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-
name: "i_#{full_name}_clear", width
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7
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+
name: "i_#{full_name}_clear", width:, array_size:
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}
|
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9
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output :value_out, {
|
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-
name: "o_#{full_name}", width
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+
name: "o_#{full_name}", width:, array_size:
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}
|
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12
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end
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13
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@@ -4,14 +4,14 @@ RgGen.define_list_item_feature(:bit_field, :type, [:rw, :rwtrg, :w1]) do
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4
4
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verilog_rtl do
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5
5
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build do
|
6
6
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output :value_out, {
|
7
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-
name: "o_#{full_name}", width
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7
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+
name: "o_#{full_name}", width:, array_size:
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}
|
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9
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if rwtrg?
|
10
10
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output :write_trigger, {
|
11
|
-
name: "o_#{full_name}_write_trigger", width: 1, array_size:
|
11
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+
name: "o_#{full_name}_write_trigger", width: 1, array_size:
|
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}
|
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13
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output :read_trigger, {
|
14
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-
name: "o_#{full_name}_read_trigger", width: 1, array_size:
|
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+
name: "o_#{full_name}_read_trigger", width: 1, array_size:
|
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}
|
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end
|
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end
|
@@ -5,11 +5,11 @@ RgGen.define_list_item_feature(:bit_field, :type, :rwc) do
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5
5
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build do
|
6
6
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unless bit_field.reference?
|
7
7
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input :clear, {
|
8
|
-
name: "i_#{full_name}_clear", width: 1, array_size:
|
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+
name: "i_#{full_name}_clear", width: 1, array_size:
|
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9
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}
|
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end
|
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11
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output :value_out, {
|
12
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-
name: "o_#{full_name}", width
|
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+
name: "o_#{full_name}", width:, array_size:
|
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13
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}
|
14
14
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end
|
15
15
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@@ -6,11 +6,11 @@ RgGen.define_list_item_feature(:bit_field, :type, [:rwe, :rwl]) do
|
|
6
6
|
unless bit_field.reference?
|
7
7
|
input :control, {
|
8
8
|
name: "i_#{full_name}_#{enable_or_lock}",
|
9
|
-
width: 1, array_size:
|
9
|
+
width: 1, array_size:
|
10
10
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}
|
11
11
|
end
|
12
12
|
output :value_out, {
|
13
|
-
name: "o_#{full_name}", width
|
13
|
+
name: "o_#{full_name}", width:, array_size:
|
14
14
|
}
|
15
15
|
end
|
16
16
|
|
@@ -5,14 +5,14 @@ RgGen.define_list_item_feature(:bit_field, :type, :rwhw) do
|
|
5
5
|
build do
|
6
6
|
unless bit_field.reference?
|
7
7
|
input :valid, {
|
8
|
-
name: "i_#{full_name}_valid", width: 1, array_size:
|
8
|
+
name: "i_#{full_name}_valid", width: 1, array_size:
|
9
9
|
}
|
10
10
|
end
|
11
11
|
input :value_in, {
|
12
|
-
name: "i_#{full_name}", width
|
12
|
+
name: "i_#{full_name}", width:, array_size:
|
13
13
|
}
|
14
14
|
output :value_out, {
|
15
|
-
name: "o_#{full_name}", width
|
15
|
+
name: "o_#{full_name}", width:, array_size:
|
16
16
|
}
|
17
17
|
end
|
18
18
|
|
@@ -5,11 +5,11 @@ RgGen.define_list_item_feature(:bit_field, :type, :rws) do
|
|
5
5
|
build do
|
6
6
|
unless bit_field.reference?
|
7
7
|
input :set, {
|
8
|
-
name: "i_#{full_name}_set", width: 1, array_size:
|
8
|
+
name: "i_#{full_name}_set", width: 1, array_size:
|
9
9
|
}
|
10
10
|
end
|
11
11
|
output :value_out, {
|
12
|
-
name: "o_#{full_name}", width
|
12
|
+
name: "o_#{full_name}", width:, array_size:
|
13
13
|
}
|
14
14
|
end
|
15
15
|
|
@@ -4,11 +4,11 @@ RgGen.define_list_item_feature(:bit_field, :type, [:wo, :wo1, :wotrg]) do
|
|
4
4
|
verilog_rtl do
|
5
5
|
build do
|
6
6
|
output :value_out, {
|
7
|
-
name: "o_#{full_name}", width
|
7
|
+
name: "o_#{full_name}", width:, array_size:
|
8
8
|
}
|
9
9
|
if wotrg?
|
10
10
|
output :write_trigger, {
|
11
|
-
name: "o_#{full_name}_write_trigger", width: 1, array_size:
|
11
|
+
name: "o_#{full_name}_write_trigger", width: 1, array_size:
|
12
12
|
}
|
13
13
|
end
|
14
14
|
end
|
@@ -23,8 +23,8 @@ RgGen.define_list_feature(:bit_field, :type) do
|
|
23
23
|
|
24
24
|
def initial_value
|
25
25
|
if multiple_initial_values?
|
26
|
-
index = bit_field.
|
27
|
-
total_bits = width *
|
26
|
+
index = bit_field.flat_loop_index
|
27
|
+
total_bits = width * array_size.inject(:*)
|
28
28
|
macro_call('rggen_slice', [bit_field.initial_value, total_bits, width, index])
|
29
29
|
else
|
30
30
|
bit_field.initial_value
|
@@ -32,7 +32,8 @@ RgGen.define_list_feature(:bit_field, :type) do
|
|
32
32
|
end
|
33
33
|
|
34
34
|
def multiple_initial_values?
|
35
|
-
bit_field.initial_value_array? &&
|
35
|
+
bit_field.initial_value_array? &&
|
36
|
+
(array_size.size > 1 || array_size.first > 1)
|
36
37
|
end
|
37
38
|
|
38
39
|
def clock
|
@@ -75,7 +76,7 @@ RgGen.define_list_feature(:bit_field, :type) do
|
|
75
76
|
bit_field.reference? &&
|
76
77
|
bit_field
|
77
78
|
.find_reference(register_block.bit_fields)
|
78
|
-
.value(bit_field.
|
79
|
+
.value(bit_field.local_indexes, bit_field.reference_width)
|
79
80
|
end
|
80
81
|
|
81
82
|
def loop_variables
|
@@ -11,7 +11,7 @@ RgGen.define_simple_feature(:bit_field, :verilog_top) do
|
|
11
11
|
if parameterized_initial_value?
|
12
12
|
parameter :initial_value, {
|
13
13
|
name: initial_value_name, width: bit_field.width,
|
14
|
-
array_size:
|
14
|
+
array_size: initial_value_size, default: initial_value_rhs
|
15
15
|
}
|
16
16
|
else
|
17
17
|
define_accessor_for_initial_value
|
@@ -34,7 +34,7 @@ RgGen.define_simple_feature(:bit_field, :verilog_top) do
|
|
34
34
|
private
|
35
35
|
|
36
36
|
def register_value(offsets, lsb, width)
|
37
|
-
index = register.index(offsets || register.
|
37
|
+
index = register.index(offsets || register.local_indexes)
|
38
38
|
register_block.register_value[[index], lsb, width]
|
39
39
|
end
|
40
40
|
|
@@ -52,8 +52,8 @@ RgGen.define_simple_feature(:bit_field, :verilog_top) do
|
|
52
52
|
"#{bit_field.full_name('_')}_initial_value".upcase
|
53
53
|
end
|
54
54
|
|
55
|
-
def
|
56
|
-
bit_field.initial_value_array? &&
|
55
|
+
def initial_value_size
|
56
|
+
bit_field.initial_value_array? && array_size || nil
|
57
57
|
end
|
58
58
|
|
59
59
|
def initial_value_rhs
|
@@ -62,7 +62,8 @@ RgGen.define_simple_feature(:bit_field, :verilog_top) do
|
|
62
62
|
elsif bit_field.fixed_initial_value?
|
63
63
|
merged_initial_values
|
64
64
|
else
|
65
|
-
|
65
|
+
size = array_size.inject(:*)
|
66
|
+
repeat(size, sized_initial_value)
|
66
67
|
end
|
67
68
|
end
|
68
69
|
|
@@ -71,12 +72,12 @@ RgGen.define_simple_feature(:bit_field, :verilog_top) do
|
|
71
72
|
end
|
72
73
|
|
73
74
|
def merged_initial_values
|
74
|
-
|
75
|
-
|
76
|
-
|
75
|
+
initial_values = bit_field.initial_values(flatten: true)
|
76
|
+
merged_value =
|
77
|
+
initial_values
|
77
78
|
.map.with_index { |v, i| v << (i * bit_field.width) }
|
78
79
|
.inject(:|)
|
79
|
-
hex(
|
80
|
+
hex(merged_value, bit_field.width * initial_values.size)
|
80
81
|
end
|
81
82
|
|
82
83
|
def loop_size
|
@@ -8,20 +8,20 @@ module RgGen
|
|
8
8
|
|
9
9
|
private
|
10
10
|
|
11
|
-
def create_variable(data_type, attributes, &
|
11
|
+
def create_variable(data_type, attributes, &)
|
12
12
|
attributes = attributes.merge(array_format: :serialized)
|
13
13
|
super
|
14
14
|
end
|
15
15
|
|
16
|
-
def create_port(direction, attributes, &
|
16
|
+
def create_port(direction, attributes, &)
|
17
17
|
attributes =
|
18
18
|
attributes
|
19
19
|
.except(:data_type)
|
20
|
-
.merge(direction
|
21
|
-
DataObject.new(:argument, attributes, &
|
20
|
+
.merge(direction:, array_format: :serialized)
|
21
|
+
DataObject.new(:argument, attributes, &)
|
22
22
|
end
|
23
23
|
|
24
|
-
def create_parameter(parameter_type, attributes, &
|
24
|
+
def create_parameter(parameter_type, attributes, &)
|
25
25
|
attributes = attributes.merge(array_format: :serialized)
|
26
26
|
super
|
27
27
|
end
|
@@ -5,7 +5,7 @@ RgGen.define_list_item_feature(:register, :type, :external) do
|
|
5
5
|
build do
|
6
6
|
parameter :strobe_width, {
|
7
7
|
name: "#{register.name}_strobe_width".upcase,
|
8
|
-
default:
|
8
|
+
default: register_block.byte_width
|
9
9
|
}
|
10
10
|
output :external_valid, {
|
11
11
|
name: "o_#{register.name}_valid", width: 1
|
@@ -0,0 +1,32 @@
|
|
1
|
+
rggen_avalon_adapter #(
|
2
|
+
.ADDRESS_WIDTH (<%= address_width %>),
|
3
|
+
.LOCAL_ADDRESS_WIDTH (<%= local_address_width %>),
|
4
|
+
.BUS_WIDTH (<%= bus_width %>),
|
5
|
+
.REGISTERS (<%= total_registers %>),
|
6
|
+
.PRE_DECODE (<%= pre_decode %>),
|
7
|
+
.BASE_ADDRESS (<%= base_address %>),
|
8
|
+
.BYTE_SIZE (<%= byte_size %>),
|
9
|
+
.ERROR_STATUS (<%= error_status %>),
|
10
|
+
.DEFAULT_READ_DATA (<%= default_read_data %>),
|
11
|
+
.INSERT_SLICER (<%= insert_slicer %>)
|
12
|
+
) u_adapter (
|
13
|
+
.i_clk (<%= register_block.clock %>),
|
14
|
+
.i_rst_n (<%= register_block.reset %>),
|
15
|
+
.i_read (<%= read %>),
|
16
|
+
.i_write (<%= write %>),
|
17
|
+
.i_address (<%= address %>),
|
18
|
+
.i_byteenable (<%= byteenable %>),
|
19
|
+
.i_writedata (<%= writedata %>),
|
20
|
+
.o_waitrequest (<%= waitrequest %>),
|
21
|
+
.o_response (<%= response %>),
|
22
|
+
.o_readdata (<%= readdata %>),
|
23
|
+
.o_register_valid (<%= register_block.register_valid %>),
|
24
|
+
.o_register_access (<%= register_block.register_access %>),
|
25
|
+
.o_register_address (<%= register_block.register_address %>),
|
26
|
+
.o_register_write_data (<%= register_block.register_write_data %>),
|
27
|
+
.o_register_strobe (<%= register_block.register_strobe %>),
|
28
|
+
.i_register_active (<%= register_block.register_active %>),
|
29
|
+
.i_register_ready (<%= register_block.register_ready %>),
|
30
|
+
.i_register_status (<%= register_block.register_status %>),
|
31
|
+
.i_register_read_data (<%= register_block.register_read_data %>)
|
32
|
+
);
|
@@ -0,0 +1,34 @@
|
|
1
|
+
# frozen_string_literal: true
|
2
|
+
|
3
|
+
RgGen.define_list_item_feature(:register_block, :protocol, :avalon) do
|
4
|
+
verilog_rtl do
|
5
|
+
build do
|
6
|
+
input :read, {
|
7
|
+
name: 'i_read', width: 1
|
8
|
+
}
|
9
|
+
input :write, {
|
10
|
+
name: 'i_write', width: 1
|
11
|
+
}
|
12
|
+
input :address, {
|
13
|
+
name: 'i_address', width: address_width
|
14
|
+
}
|
15
|
+
input :byteenable, {
|
16
|
+
name: 'i_byteenable', width: bus_width / 8
|
17
|
+
}
|
18
|
+
input :writedata, {
|
19
|
+
name: 'i_writedata', width: bus_width
|
20
|
+
}
|
21
|
+
output :waitrequest, {
|
22
|
+
name: 'o_waitrequest', width: 1
|
23
|
+
}
|
24
|
+
output :response, {
|
25
|
+
name: 'o_response', width: 2
|
26
|
+
}
|
27
|
+
output :readdata, {
|
28
|
+
name: 'o_readdata', width: bus_width
|
29
|
+
}
|
30
|
+
end
|
31
|
+
|
32
|
+
main_code :register_block, from_template: true
|
33
|
+
end
|
34
|
+
end
|
@@ -0,0 +1,34 @@
|
|
1
|
+
rggen_native_adapter #(
|
2
|
+
.ADDRESS_WIDTH (<%= address_width %>),
|
3
|
+
.LOCAL_ADDRESS_WIDTH (<%= local_address_width %>),
|
4
|
+
.BUS_WIDTH (<%= bus_width %>),
|
5
|
+
.STROBE_WIDTH (<%= strobe_width %>),
|
6
|
+
.REGISTERS (<%= total_registers %>),
|
7
|
+
.PRE_DECODE (<%= pre_decode %>),
|
8
|
+
.BASE_ADDRESS (<%= base_address %>),
|
9
|
+
.BYTE_SIZE (<%= byte_size %>),
|
10
|
+
.USE_READ_STROBE (<%= use_read_strobe %>),
|
11
|
+
.ERROR_STATUS (<%= error_status %>),
|
12
|
+
.DEFAULT_READ_DATA (<%= default_read_data %>),
|
13
|
+
.INSERT_SLICER (<%= insert_slicer %>)
|
14
|
+
) u_adapter (
|
15
|
+
.i_clk (<%= register_block.clock %>),
|
16
|
+
.i_rst_n (<%= register_block.reset %>),
|
17
|
+
.i_csrbus_valid (<%= valid %>),
|
18
|
+
.i_csrbus_access (<%= access %>),
|
19
|
+
.i_csrbus_address (<%= address %>),
|
20
|
+
.i_csrbus_write_data (<%= write_data %>),
|
21
|
+
.i_csrbus_strobe (<%= strobe %>),
|
22
|
+
.o_csrbus_ready (<%= ready %>),
|
23
|
+
.o_csrbus_status (<%= status %>),
|
24
|
+
.o_csrbus_read_data (<%= read_data %>),
|
25
|
+
.o_register_valid (<%= register_block.register_valid %>),
|
26
|
+
.o_register_access (<%= register_block.register_access %>),
|
27
|
+
.o_register_address (<%= register_block.register_address %>),
|
28
|
+
.o_register_write_data (<%= register_block.register_write_data %>),
|
29
|
+
.o_register_strobe (<%= register_block.register_strobe %>),
|
30
|
+
.i_register_active (<%= register_block.register_active %>),
|
31
|
+
.i_register_ready (<%= register_block.register_ready %>),
|
32
|
+
.i_register_status (<%= register_block.register_status %>),
|
33
|
+
.i_register_read_data (<%= register_block.register_read_data %>)
|
34
|
+
);
|
@@ -0,0 +1,41 @@
|
|
1
|
+
# frozen_string_literal: true
|
2
|
+
|
3
|
+
RgGen.define_list_item_feature(:register_block, :protocol, :native) do
|
4
|
+
verilog_rtl do
|
5
|
+
build do
|
6
|
+
parameter :strobe_width, {
|
7
|
+
name: 'STROBE_WIDTH', default: bus_width / 8
|
8
|
+
}
|
9
|
+
parameter :use_read_strobe, {
|
10
|
+
name: 'USE_READ_STROBE', default: 0
|
11
|
+
}
|
12
|
+
|
13
|
+
input :valid, {
|
14
|
+
name: 'i_csrbus_valid', width: 1
|
15
|
+
}
|
16
|
+
input :access, {
|
17
|
+
name: 'i_csrbus_access', width: 2
|
18
|
+
}
|
19
|
+
input :address, {
|
20
|
+
name: 'i_csrbus_address', width: address_width
|
21
|
+
}
|
22
|
+
input :write_data, {
|
23
|
+
name: 'i_csrbus_write_data', width: bus_width
|
24
|
+
}
|
25
|
+
input :strobe, {
|
26
|
+
name: 'i_csrbus_strobe', width: strobe_width
|
27
|
+
}
|
28
|
+
output :ready, {
|
29
|
+
name: 'o_csrbus_ready', width: 1
|
30
|
+
}
|
31
|
+
output :status, {
|
32
|
+
name: 'o_csrbus_status', width: 2
|
33
|
+
}
|
34
|
+
output :read_data, {
|
35
|
+
name: 'o_csrbus_read_data', width: bus_width
|
36
|
+
}
|
37
|
+
end
|
38
|
+
|
39
|
+
main_code :register_block, from_template: true
|
40
|
+
end
|
41
|
+
end
|
@@ -29,7 +29,7 @@ RgGen.define_list_feature(:register_block, :protocol) do
|
|
29
29
|
private
|
30
30
|
|
31
31
|
def bus_width
|
32
|
-
|
32
|
+
register_block.bus_width
|
33
33
|
end
|
34
34
|
|
35
35
|
def local_address_width
|
@@ -46,8 +46,8 @@ RgGen.define_list_feature(:register_block, :protocol) do
|
|
46
46
|
end
|
47
47
|
|
48
48
|
factory do
|
49
|
-
def target_feature_key(
|
50
|
-
|
49
|
+
def target_feature_key(_configuration, register_block)
|
50
|
+
register_block.protocol
|
51
51
|
end
|
52
52
|
end
|
53
53
|
end
|
@@ -5,8 +5,8 @@ module RgGen
|
|
5
5
|
module Utility
|
6
6
|
private
|
7
7
|
|
8
|
-
def local_scope(name, attributes = {}, &
|
9
|
-
LocalScope.new(attributes.merge(name:
|
8
|
+
def local_scope(name, attributes = {}, &)
|
9
|
+
LocalScope.new(attributes.merge(name:), &).to_code
|
10
10
|
end
|
11
11
|
|
12
12
|
def fill_0(width)
|
data/lib/rggen/verilog.rb
CHANGED
@@ -8,6 +8,7 @@ require_relative 'verilog/rtl/component'
|
|
8
8
|
require_relative 'verilog/rtl/feature'
|
9
9
|
require_relative 'verilog/rtl_header/component'
|
10
10
|
require_relative 'verilog/rtl_header/feature'
|
11
|
+
require_relative 'verilog/register_map/keyword_checker'
|
11
12
|
require_relative 'verilog/factories'
|
12
13
|
|
13
14
|
RgGen.setup_plugin :'rggen-verilog' do |plugin|
|
@@ -25,7 +26,9 @@ RgGen.setup_plugin :'rggen-verilog' do |plugin|
|
|
25
26
|
'verilog/rtl/register_block/protocol',
|
26
27
|
'verilog/rtl/register_block/protocol/apb',
|
27
28
|
'verilog/rtl/register_block/protocol/axi4lite',
|
29
|
+
'verilog/rtl/register_block/protocol/avalon',
|
28
30
|
'verilog/rtl/register_block/protocol/wishbone',
|
31
|
+
'verilog/rtl/register_block/protocol/native',
|
29
32
|
'verilog/rtl/register_file/verilog_top',
|
30
33
|
'verilog/rtl/register/verilog_top',
|
31
34
|
'verilog/rtl/register/type',
|
@@ -66,4 +69,8 @@ RgGen.setup_plugin :'rggen-verilog' do |plugin|
|
|
66
69
|
'verilog/rtl_header/register/verilog_rtl_header',
|
67
70
|
'verilog/rtl_header/register_block/verilog_rtl_header'
|
68
71
|
]
|
72
|
+
|
73
|
+
plugin.files [
|
74
|
+
'verilog/register_map/name'
|
75
|
+
]
|
69
76
|
end
|
metadata
CHANGED
@@ -1,14 +1,13 @@
|
|
1
1
|
--- !ruby/object:Gem::Specification
|
2
2
|
name: rggen-verilog
|
3
3
|
version: !ruby/object:Gem::Version
|
4
|
-
version: 0.
|
4
|
+
version: 0.13.0
|
5
5
|
platform: ruby
|
6
6
|
authors:
|
7
7
|
- Taichi Ishitani
|
8
|
-
autorequire:
|
9
8
|
bindir: bin
|
10
9
|
cert_chain: []
|
11
|
-
date:
|
10
|
+
date: 2025-02-19 00:00:00.000000000 Z
|
12
11
|
dependencies:
|
13
12
|
- !ruby/object:Gem::Dependency
|
14
13
|
name: rggen-systemverilog
|
@@ -16,14 +15,14 @@ dependencies:
|
|
16
15
|
requirements:
|
17
16
|
- - ">="
|
18
17
|
- !ruby/object:Gem::Version
|
19
|
-
version: 0.
|
18
|
+
version: 0.35.0
|
20
19
|
type: :runtime
|
21
20
|
prerelease: false
|
22
21
|
version_requirements: !ruby/object:Gem::Requirement
|
23
22
|
requirements:
|
24
23
|
- - ">="
|
25
24
|
- !ruby/object:Gem::Version
|
26
|
-
version: 0.
|
25
|
+
version: 0.35.0
|
27
26
|
description: Verilog write plugin for RgGen
|
28
27
|
email:
|
29
28
|
- rggen@googlegroups.com
|
@@ -36,6 +35,8 @@ files:
|
|
36
35
|
- README.md
|
37
36
|
- lib/rggen/verilog.rb
|
38
37
|
- lib/rggen/verilog/factories.rb
|
38
|
+
- lib/rggen/verilog/register_map/keyword_checker.rb
|
39
|
+
- lib/rggen/verilog/register_map/name.rb
|
39
40
|
- lib/rggen/verilog/rtl/bit_field/type.rb
|
40
41
|
- lib/rggen/verilog/rtl/bit_field/type/custom.erb
|
41
42
|
- lib/rggen/verilog/rtl/bit_field/type/custom.rb
|
@@ -88,8 +89,12 @@ files:
|
|
88
89
|
- lib/rggen/verilog/rtl/register_block/protocol.rb
|
89
90
|
- lib/rggen/verilog/rtl/register_block/protocol/apb.erb
|
90
91
|
- lib/rggen/verilog/rtl/register_block/protocol/apb.rb
|
92
|
+
- lib/rggen/verilog/rtl/register_block/protocol/avalon.erb
|
93
|
+
- lib/rggen/verilog/rtl/register_block/protocol/avalon.rb
|
91
94
|
- lib/rggen/verilog/rtl/register_block/protocol/axi4lite.erb
|
92
95
|
- lib/rggen/verilog/rtl/register_block/protocol/axi4lite.rb
|
96
|
+
- lib/rggen/verilog/rtl/register_block/protocol/native.erb
|
97
|
+
- lib/rggen/verilog/rtl/register_block/protocol/native.rb
|
93
98
|
- lib/rggen/verilog/rtl/register_block/protocol/wishbone.erb
|
94
99
|
- lib/rggen/verilog/rtl/register_block/protocol/wishbone.rb
|
95
100
|
- lib/rggen/verilog/rtl/register_block/verilog_macros.erb
|
@@ -112,7 +117,6 @@ metadata:
|
|
112
117
|
rubygems_mfa_required: 'true'
|
113
118
|
source_code_uri: https://github.com/rggen/rggen-verilog
|
114
119
|
wiki_uri: https://github.com/rggen/rggen/wiki
|
115
|
-
post_install_message:
|
116
120
|
rdoc_options: []
|
117
121
|
require_paths:
|
118
122
|
- lib
|
@@ -120,15 +124,14 @@ required_ruby_version: !ruby/object:Gem::Requirement
|
|
120
124
|
requirements:
|
121
125
|
- - ">="
|
122
126
|
- !ruby/object:Gem::Version
|
123
|
-
version: '3.
|
127
|
+
version: '3.1'
|
124
128
|
required_rubygems_version: !ruby/object:Gem::Requirement
|
125
129
|
requirements:
|
126
130
|
- - ">="
|
127
131
|
- !ruby/object:Gem::Version
|
128
132
|
version: '0'
|
129
133
|
requirements: []
|
130
|
-
rubygems_version: 3.
|
131
|
-
signing_key:
|
134
|
+
rubygems_version: 3.6.2
|
132
135
|
specification_version: 4
|
133
|
-
summary: rggen-verilog-0.
|
136
|
+
summary: rggen-verilog-0.13.0
|
134
137
|
test_files: []
|