rggen-verilog 0.10.0 → 0.11.1

checksums.yaml

@@ -1,7 +1,7 @@
 ---
 SHA256:
-  metadata.gz: ae3ef0f79a6f941f4efa341eca05fb18fea782cfdab3992e4456c764aa3ba138
-  data.tar.gz: ac2651f017ab663d7f6dd1cc652f9be843096eca7ce88641fbcef47f8fcab3d6
+  metadata.gz: 5c3c718beffbd398b73e1783be15e50f6b9c3b103c122779b4d6baa848b9992f
+  data.tar.gz: 7efc7297a728743b96fb447f11e63ee59eb69840790970683a31506f8d4f8547
 SHA512:
-  metadata.gz: d3181cf232bb8370a0be9a634d59e3f6770f4e8529b39f6b50f83cca267b7baaad5d194586deaf92b97a47a388a50d0545ef0aca81eba948be9f10008067796d
-  data.tar.gz: 1ca0607fb3c090e49ef057e2de426ec9c4ddc91080e3f39a5b21bc27480f828be89bb1f263e8314dbe26e2e3671f5c4db2ede7deadfc2a1b12f134f75abcbe09
+  metadata.gz: 2035b9d4163eb93c20afcaa4edd5809fabb1338ae8e4b2c2cc6440cae7fde49bbf179cdc4bcb76f65ffb33c61e66c859b694948f98fc27a78556a0f8614c6373
+  data.tar.gz: c1112eb1588ea48f963177b235a55e1251b7b9c4fa3802e6907ba752a6de695077207fa0472b76c1e44bd34b990b71a46318a178224459de85f8549e7b6988be

data/LICENSE

@@ -1,6 +1,6 @@
 The MIT License (MIT)
 
-Copyright (c) 2020-2023 Taichi Ishitani
+Copyright (c) 2020-2024 Taichi Ishitani
 
 Permission is hereby granted, free of charge, to any person obtaining a copy
 of this software and associated documentation files (the "Software"), to deal

data/README.md

@@ -68,7 +68,7 @@ Feedbacks, bus reports, questions and etc. are welcome! You can post them bu usi
 
 ## Copyright & License
 
-Copyright © 2020-2023 Taichi Ishitani. RgGen::Verilog is licensed under the [MIT License](https://opensource.org/licenses/MIT), see [LICENSE](LICENSE) for futher details.
+Copyright © 2020-2024 Taichi Ishitani. RgGen::Verilog is licensed under the [MIT License](https://opensource.org/licenses/MIT), see [LICENSE](LICENSE) for futher details.
 
 ## Code of Conduct
 

data/lib/rggen/verilog/rtl/bit_field/type/{rol.erb → rohw.erb}

@@ -14,7 +14,7 @@ rggen_bit_field #(
   .o_sw_value         (<%= bit_field_value %>),
   .o_write_trigger    (),
   .o_read_trigger     (),
-  .i_hw_write_enable  (<%= latch_signal %>),
+  .i_hw_write_enable  (<%= valid_signal %>),
   .i_hw_write_data    (<%= value_in[loop_variables] %>),
   .i_hw_set           (<%= fill_0(width) %>),
   .i_hw_clear         (<%= fill_0(width) %>),

data/lib/rggen/verilog/rtl/bit_field/type/{rol.rb → rohw.rb}

@@ -1,11 +1,11 @@
 # frozen_string_literal: true
 
-RgGen.define_list_item_feature(:bit_field, :type, :rol) do
+RgGen.define_list_item_feature(:bit_field, :type, :rohw) do
   verilog_rtl do
     build do
       unless bit_field.reference?
-        input :latch, {
-          name: "i_#{full_name}_latch", width: 1, array_size: array_size
+        input :valid, {
+          name: "i_#{full_name}_valid", width: 1, array_size: array_size
         }
       end
       input :value_in, {
@@ -18,8 +18,8 @@ RgGen.define_list_item_feature(:bit_field, :type, :rol) do
 
     main_code :bit_field, from_template: true
 
-    def latch_signal
-      reference_bit_field || latch[loop_variables]
+    def valid_signal
+      reference_bit_field || valid[loop_variables]
     end
   end
 end

data/lib/rggen/verilog/rtl/bit_field/type/rwhw.erb

@@ -0,0 +1,24 @@
+rggen_bit_field #(
+  .WIDTH          (<%= width %>),
+  .INITIAL_VALUE  (<%= initial_value %>)
+) u_bit_field (
+  .i_clk              (<%= clock %>),
+  .i_rst_n            (<%= reset %>),
+  .i_sw_valid         (<%= bit_field_valid %>),
+  .i_sw_read_mask     (<%= bit_field_read_mask %>),
+  .i_sw_write_enable  (1'b1),
+  .i_sw_write_mask    (<%= bit_field_write_mask %>),
+  .i_sw_write_data    (<%= bit_field_write_data %>),
+  .o_sw_read_data     (<%= bit_field_read_data %>),
+  .o_sw_value         (<%= bit_field_value %>),
+  .o_write_trigger    (),
+  .o_read_trigger     (),
+  .i_hw_write_enable  (<%= valid_signal %>),
+  .i_hw_write_data    (<%= value_in[loop_variables] %>),
+  .i_hw_set           (<%= fill_0(width) %>),
+  .i_hw_clear         (<%= fill_0(width) %>),
+  .i_value            (<%= fill_0(width) %>),
+  .i_mask             (<%= fill_1(width) %>),
+  .o_value            (<%= value_out[loop_variables] %>),
+  .o_value_unmasked   ()
+);

data/lib/rggen/verilog/rtl/bit_field/type/rwhw.rb

@@ -0,0 +1,27 @@
+# frozen_string_literal: true
+
+RgGen.define_list_item_feature(:bit_field, :type, :rwhw) do
+  verilog_rtl do
+    build do
+      unless bit_field.reference?
+        input :valid, {
+          name: "i_#{full_name}_valid", width: 1, array_size: array_size
+        }
+      end
+      input :value_in, {
+        name: "i_#{full_name}", width: width, array_size: array_size
+      }
+      output :value_out, {
+        name: "o_#{full_name}", width: width, array_size: array_size
+      }
+    end
+
+    main_code :bit_field, from_template: true
+
+    private
+
+    def valid_signal
+      reference_bit_field || valid[loop_variables]
+    end
+  end
+end

data/lib/rggen/verilog/rtl/bit_field/type/rws.erb

@@ -1,6 +1,7 @@
 rggen_bit_field #(
   .WIDTH          (<%= width %>),
-  .INITIAL_VALUE  (<%= initial_value %>)
+  .INITIAL_VALUE  (<%= initial_value %>),
+  .HW_SET_WIDTH   (1)
 ) u_bit_field (
   .i_clk              (<%= clock %>),
   .i_rst_n            (<%= reset %>),
@@ -13,9 +14,9 @@ rggen_bit_field #(
   .o_sw_value         (<%= bit_field_value %>),
   .o_write_trigger    (),
   .o_read_trigger     (),
-  .i_hw_write_enable  (<%= set_signal %>),
-  .i_hw_write_data    (<%= value_in[loop_variables] %>),
-  .i_hw_set           (<%= fill_0(width) %>),
+  .i_hw_write_enable  (1'b0),
+  .i_hw_write_data    (<%= fill_0(width) %>),
+  .i_hw_set           (<%= set_signal %>),
   .i_hw_clear         (<%= fill_0(width) %>),
   .i_value            (<%= fill_0(width) %>),
   .i_mask             (<%= fill_1(width) %>),

data/lib/rggen/verilog/rtl/bit_field/type/rws.rb

@@ -8,9 +8,6 @@ RgGen.define_list_item_feature(:bit_field, :type, :rws) do
           name: "i_#{full_name}_set", width: 1, array_size: array_size
         }
       end
-      input :value_in, {
-        name: "i_#{full_name}", width: width, array_size: array_size
-      }
       output :value_out, {
         name: "o_#{full_name}", width: width, array_size: array_size
       }

data/lib/rggen/verilog/rtl/register/type/indirect.erb

@@ -5,8 +5,7 @@ rggen_indirect_register #(
   .OFFSET_ADDRESS       (<%= offset_address %>),
   .BUS_WIDTH            (<%= bus_width %>),
   .DATA_WIDTH           (<%= width %>),
-  .INDIRECT_INDEX_WIDTH (<%= index_width %>),
-  .INDIRECT_INDEX_VALUE (<%= concat(index_values) %>)
+  .INDIRECT_MATCH_WIDTH (<%= index_match_width %>)
 ) u_register (
   .i_clk                  (<%= clock %>),
   .i_rst_n                (<%= reset %>),
@@ -20,7 +19,7 @@ rggen_indirect_register #(
   .o_register_status      (<%= register_status %>),
   .o_register_read_data   (<%= register_read_data %>),
   .o_register_value       (<%= register_value %>),
-  .i_indirect_index       (<%= indirect_index %>),
+  .i_indirect_match       (<%= indirect_match %>),
   .o_bit_field_valid      (<%= bit_field_valid %>),
   .o_bit_field_read_mask  (<%= bit_field_read_mask %>),
   .o_bit_field_write_mask (<%= bit_field_write_mask %>),

data/lib/rggen/verilog/rtl/register/type/indirect.rb

@@ -5,14 +5,20 @@ RgGen.define_list_item_feature(:register, :type, :indirect) do
     include RgGen::SystemVerilog::RTL::IndirectIndex
 
     build do
-      wire :indirect_index, {
-        name: 'w_indirect_index', width: index_width
+      wire :indirect_match, {
+        name: 'w_indirect_match', width: index_match_width
       }
     end
 
     main_code :register do |code|
-      code << indirect_index_assignment << nl
+      indirect_index_matches(code)
       code << process_template
     end
+
+    private
+
+    def array_index_value(value, width)
+      value[0, width]
+    end
   end
 end

data/lib/rggen/verilog/version.rb

@@ -2,6 +2,6 @@
 
 module RgGen
   module Verilog
-    VERSION = '0.10.0'
+    VERSION = '0.11.1'
   end
 end

data/lib/rggen/verilog.rb

@@ -38,13 +38,14 @@ RgGen.setup_plugin :'rggen-verilog' do |plugin|
     'verilog/rtl/bit_field/type/rc_w0c_w1c_wc_woc',
     'verilog/rtl/bit_field/type/ro_rotrg',
     'verilog/rtl/bit_field/type/rof',
-    'verilog/rtl/bit_field/type/rol',
+    'verilog/rtl/bit_field/type/rohw',
     'verilog/rtl/bit_field/type/row0trg_row1trg',
     'verilog/rtl/bit_field/type/rowo_rowotrg',
     'verilog/rtl/bit_field/type/rs_w0s_w1s_ws_wos',
     'verilog/rtl/bit_field/type/rw_rwtrg_w1',
     'verilog/rtl/bit_field/type/rwc',
     'verilog/rtl/bit_field/type/rwe_rwl',
+    'verilog/rtl/bit_field/type/rwhw',
     'verilog/rtl/bit_field/type/rws',
     'verilog/rtl/bit_field/type/w0crs_w0src_w1crs_w1src_wcrs_wsrc',
     'verilog/rtl/bit_field/type/w0t_w1t',

metadata

@@ -1,14 +1,14 @@
 --- !ruby/object:Gem::Specification
 name: rggen-verilog
 version: !ruby/object:Gem::Version
-  version: 0.10.0
+  version: 0.11.1
 platform: ruby
 authors:
 - Taichi Ishitani
 autorequire: 
 bindir: bin
 cert_chain: []
-date: 2023-12-28 00:00:00.000000000 Z
+date: 2024-11-28 00:00:00.000000000 Z
 dependencies:
 - !ruby/object:Gem::Dependency
   name: rggen-systemverilog
@@ -16,14 +16,14 @@ dependencies:
     requirements:
     - - ">="
       - !ruby/object:Gem::Version
-        version: 0.32.0
+        version: 0.33.1
   type: :runtime
   prerelease: false
   version_requirements: !ruby/object:Gem::Requirement
     requirements:
     - - ">="
       - !ruby/object:Gem::Version
-        version: 0.32.0
+        version: 0.33.1
 description: Verilog write plugin for RgGen
 email:
 - rggen@googlegroups.com
@@ -45,8 +45,8 @@ files:
 - lib/rggen/verilog/rtl/bit_field/type/ro_rotrg.rb
 - lib/rggen/verilog/rtl/bit_field/type/rof.erb
 - lib/rggen/verilog/rtl/bit_field/type/rof.rb
-- lib/rggen/verilog/rtl/bit_field/type/rol.erb
-- lib/rggen/verilog/rtl/bit_field/type/rol.rb
+- lib/rggen/verilog/rtl/bit_field/type/rohw.erb
+- lib/rggen/verilog/rtl/bit_field/type/rohw.rb
 - lib/rggen/verilog/rtl/bit_field/type/row0trg_row1trg.erb
 - lib/rggen/verilog/rtl/bit_field/type/row0trg_row1trg.rb
 - lib/rggen/verilog/rtl/bit_field/type/rowo_rowotrg.erb
@@ -59,6 +59,8 @@ files:
 - lib/rggen/verilog/rtl/bit_field/type/rwc.rb
 - lib/rggen/verilog/rtl/bit_field/type/rwe_rwl.erb
 - lib/rggen/verilog/rtl/bit_field/type/rwe_rwl.rb
+- lib/rggen/verilog/rtl/bit_field/type/rwhw.erb
+- lib/rggen/verilog/rtl/bit_field/type/rwhw.rb
 - lib/rggen/verilog/rtl/bit_field/type/rws.erb
 - lib/rggen/verilog/rtl/bit_field/type/rws.rb
 - lib/rggen/verilog/rtl/bit_field/type/w0crs_w0src_w1crs_w1src_wcrs_wsrc.erb
@@ -125,8 +127,8 @@ required_rubygems_version: !ruby/object:Gem::Requirement
     - !ruby/object:Gem::Version
       version: '0'
 requirements: []
-rubygems_version: 3.5.3
+rubygems_version: 3.5.16
 signing_key: 
 specification_version: 4
-summary: rggen-verilog-0.10.0
+summary: rggen-verilog-0.11.1
 test_files: []