rggen-systemverilog 0.27.1 → 0.28.0

Sign up to get free protection for your applications and to get access to all the features.
checksums.yaml CHANGED
@@ -1,7 +1,7 @@
1
1
  ---
2
2
  SHA256:
3
- metadata.gz: b163ec13c4940ca6d489739aaae909dd3d189627eff20383cef519537bade127
4
- data.tar.gz: 6bdfd55721b6e7c1a7250eed73cb5ca6ce1a2dba28d57e134b06b601397afabe
3
+ metadata.gz: 60c25d990cd209fcfe988002dee2325f1ec8d319295f9014cfe59715b87d44e7
4
+ data.tar.gz: db8957f134063c33fdd6efbfe3596e5871ac6f166359bb4f7b013f883ab9f3bd
5
5
  SHA512:
6
- metadata.gz: f8327405b12e0d43ab8801772b85efd57f0a71f856f0f07efec961d97c7b70c4bacee05968303a41178201e9b90a16b289af24b23a71cb403ed5949fbeba0251
7
- data.tar.gz: be673375b40e9d4c8241be45a4feb8ee4a09d815bc4ecd0926759f058dea021e8588b270de22408f8a34fa8cb5f50772f51addc47b3cfa60dba0c858064bccbd
6
+ metadata.gz: 759a5c90f3311b34f016b4fbade25d14785349f9ae88e1244596baa9b44abb80453eb3609ad2534d0b9d78a390aa8f39c747257c0a9ababa209b669cbb52b331
7
+ data.tar.gz: d0923aa115d8251966cad5ee14846b6037d1187e5c889ff288af6c0a26b132dcd7823916dd8d7214317dccbc849f85482fc1b2d947b6cf465cc218d8d704fef2
@@ -76,8 +76,8 @@ module RgGen
76
76
  def __serialized_lsb__(array_index, lsb)
77
77
  index =
78
78
  array_index
79
- .yield_self(&method(:__serialized_index__))
80
- .yield_self(&method(:__enclose_index_in_parenthesis))
79
+ .then(&method(:__serialized_index__))
80
+ .then(&method(:__enclose_index_in_parenthesis))
81
81
  array_lsb = __reduce_array__([@width, index], :*, 1)
82
82
  __reduce_array__([array_lsb, lsb], :+, 0)
83
83
  end
@@ -87,7 +87,7 @@ module RgGen
87
87
  .reverse
88
88
  .zip(__index_factors__)
89
89
  .map { |i, f| __calc_index_value__(i, f) }
90
- .yield_self { |values| __reduce_array__(values.reverse, :+, 0) }
90
+ .then { |values| __reduce_array__(values.reverse, :+, 0) }
91
91
  end
92
92
 
93
93
  def __enclose_index_in_parenthesis(index)
@@ -0,0 +1,28 @@
1
+ # frozen_string_literal: true
2
+
3
+ RgGen.define_list_item_feature(:bit_field, :type, :custom) do
4
+ sv_ral do
5
+ model_name do
6
+ 'rggen_ral_custom_field ' \
7
+ "#(#{sw_read}, #{sw_write}, #{write_once}, #{hw_update})"
8
+ end
9
+
10
+ private
11
+
12
+ def sw_read
13
+ string(bit_field.sw_read.upcase)
14
+ end
15
+
16
+ def sw_write
17
+ string(bit_field.sw_write.upcase)
18
+ end
19
+
20
+ def write_once
21
+ bit_field.sw_write_once? && 1 || 0
22
+ end
23
+
24
+ def hw_update
25
+ bit_field.hw_update? && 1 || 0
26
+ end
27
+ end
28
+ end
@@ -0,0 +1,5 @@
1
+ # frozen_string_literal: true
2
+
3
+ RgGen.define_list_item_feature(:bit_field, :type, [:rof, :rol]) do
4
+ sv_ral { access 'RO' }
5
+ end
@@ -22,7 +22,8 @@ RgGen.setup_plugin :'rggen-sv-ral' do |plugin|
22
22
  'ral/register/type/external',
23
23
  'ral/register/type/indirect',
24
24
  'ral/bit_field/type',
25
- 'ral/bit_field/type/rof',
25
+ 'ral/bit_field/type/custom',
26
+ 'ral/bit_field/type/rof_rol',
26
27
  'ral/bit_field/type/rotrg_rwtrg_wotrg',
27
28
  'ral/bit_field/type/row0trg_row1trg_w0trg_w1trg',
28
29
  'ral/bit_field/type/rowo_rowotrg',
@@ -0,0 +1,25 @@
1
+ rggen_bit_field #(
2
+ .WIDTH (<%= width %>),
3
+ .INITIAL_VALUE (<%= initial_value %>),
4
+ .SW_READ_ACTION (<%= sw_read_action %>),
5
+ .SW_WRITE_ACTION (<%= sw_write_action %>),
6
+ .SW_WRITE_ONCE (<%= write_once %>),
7
+ .STORAGE (<%= storage %>),
8
+ .EXTERNAL_READ_DATA (<%= external_read_data %>),
9
+ .TRIGGER (<%= trigger %>)
10
+ ) u_bit_field (
11
+ .i_clk (i_clk),
12
+ .i_rst_n (i_rst_n),
13
+ .bit_field_if (bit_field_sub_if),
14
+ .o_write_trigger (<%= output_port(:write_trigger) %>),
15
+ .o_read_trigger (<%= output_port(:read_trigger) %>),
16
+ .i_sw_write_enable ('1),
17
+ .i_hw_write_enable (<%= input_port(:hw_write_enable) %>),
18
+ .i_hw_write_data (<%= input_port(:hw_write_data) %>),
19
+ .i_hw_set (<%= input_port(:hw_set) %>),
20
+ .i_hw_clear (<%= input_port(:hw_clear) %>),
21
+ .i_value (<%= input_port(:value_in) %>),
22
+ .i_mask ('1),
23
+ .o_value (<%= output_port(:value_out) %>),
24
+ .o_value_unmasked ()
25
+ );
@@ -0,0 +1,121 @@
1
+ # frozen_string_literal: true
2
+
3
+ RgGen.define_list_item_feature(:bit_field, :type, :custom) do
4
+ sv_rtl do
5
+ build do
6
+ if external_read_data?
7
+ input :value_in, {
8
+ name: "i_#{full_name}", width: width,
9
+ array_size: array_size, array_format: array_port_format
10
+ }
11
+ else
12
+ output :value_out, {
13
+ name: "o_#{full_name}", width: width,
14
+ array_size: array_size, array_format: array_port_format
15
+ }
16
+ end
17
+ if bit_field.hw_write?
18
+ input :hw_write_enable, {
19
+ name: "i_#{full_name}_hw_write_enable", width: 1,
20
+ array_size: array_size, array_format: array_port_format
21
+ }
22
+ input :hw_write_data, {
23
+ name: "i_#{full_name}_hw_write_data", width: width,
24
+ array_size: array_size, array_format: array_port_format
25
+ }
26
+ end
27
+ if bit_field.hw_set?
28
+ input :hw_set, {
29
+ name: "i_#{full_name}_hw_set", width: width,
30
+ array_size: array_size, array_format: array_port_format
31
+ }
32
+ end
33
+ if bit_field.hw_clear?
34
+ input :hw_clear, {
35
+ name: "i_#{full_name}_hw_clear", width: width,
36
+ array_size: array_size, array_format: array_port_format
37
+ }
38
+ end
39
+ if bit_field.write_trigger?
40
+ output :write_trigger, {
41
+ name: "o_#{full_name}_write_trigger", width: 1,
42
+ array_size: array_size, array_format: array_port_format
43
+ }
44
+ end
45
+ if bit_field.read_trigger?
46
+ output :read_trigger, {
47
+ name: "o_#{full_name}_read_trigger", width: 1,
48
+ array_size: array_size, array_format: array_port_format
49
+ }
50
+ end
51
+ end
52
+
53
+ main_code :bit_field, from_template: true
54
+
55
+ private
56
+
57
+ def external_read_data?
58
+ !bit_field.sw_update? && !bit_field.hw_update?
59
+ end
60
+
61
+ def initial_value
62
+ external_read_data? && all_bits_0 || super
63
+ end
64
+
65
+ def sw_read_action
66
+ {
67
+ none: 'RGGEN_READ_NONE',
68
+ default: 'RGGEN_READ_DEFAULT',
69
+ set: 'RGGEN_READ_SET',
70
+ clear: 'RGGEN_READ_CLEAR'
71
+ }[bit_field.sw_read]
72
+ end
73
+
74
+ def sw_write_action
75
+ {
76
+ none: 'RGGEN_WRITE_NONE',
77
+ default: 'RGGEN_WRITE_DEFAULT',
78
+ clear_0: 'RGGEN_WRITE_0_CLEAR',
79
+ clear_1: 'RGGEN_WRITE_1_CLEAR',
80
+ clear: 'RGGEN_WRITE_CLEAR',
81
+ set_0: 'RGGEN_WRITE_0_SET',
82
+ set_1: 'RGGEN_WRITE_1_SET',
83
+ set: 'RGGEN_WRITE_SET',
84
+ toggle_0: 'RGGEN_WRITE_0_TOGGLE',
85
+ toggle_1: 'RGGEN_WRITE_1_TOGGLE'
86
+ }[bit_field.sw_write]
87
+ end
88
+
89
+ def write_once
90
+ bit_field.sw_write_once? && 1 || 0
91
+ end
92
+
93
+ def storage
94
+ external_read_data? && 0 || 1
95
+ end
96
+
97
+ def external_read_data
98
+ external_read_data? && 1 || 0
99
+ end
100
+
101
+ def trigger?
102
+ bit_field.write_trigger? || bit_field.read_trigger?
103
+ end
104
+
105
+ def trigger
106
+ trigger? && 1 || 0
107
+ end
108
+
109
+ def input_port(name)
110
+ find_port(name, all_bits_0)
111
+ end
112
+
113
+ def output_port(name)
114
+ find_port(name, '')
115
+ end
116
+
117
+ def find_port(name, default_value)
118
+ respond_to?(name) && __send__(name)[loop_variables] || default_value
119
+ end
120
+ end
121
+ end
@@ -0,0 +1,20 @@
1
+ rggen_bit_field #(
2
+ .WIDTH (<%= width %>),
3
+ .INITIAL_VALUE (<%= initial_value %>),
4
+ .SW_WRITE_ACTION (RGGEN_WRITE_NONE)
5
+ ) u_bit_field (
6
+ .i_clk (<%= clock %>),
7
+ .i_rst_n (<%= reset %>),
8
+ .bit_field_if (<%= bit_field_if %>),
9
+ .o_write_trigger (),
10
+ .o_read_trigger (),
11
+ .i_sw_write_enable ('1),
12
+ .i_hw_write_enable (<%= latch_signal %>),
13
+ .i_hw_write_data (<%= value_in[loop_variables] %>),
14
+ .i_hw_set ('0),
15
+ .i_hw_clear ('0),
16
+ .i_value ('0),
17
+ .i_mask ('1),
18
+ .o_value (<%= value_out[loop_variables] %>),
19
+ .o_value_unmasked ()
20
+ );
@@ -0,0 +1,30 @@
1
+ # frozen_string_literal: true
2
+
3
+ RgGen.define_list_item_feature(:bit_field, :type, :rol) do
4
+ sv_rtl do
5
+ build do
6
+ unless bit_field.reference?
7
+ input :latch, {
8
+ name: "i_#{full_name}_latch", width: 1,
9
+ array_size: array_size, array_format: array_port_format
10
+ }
11
+ end
12
+ input :value_in, {
13
+ name: "i_#{full_name}", width: width,
14
+ array_size: array_size, array_format: array_port_format
15
+ }
16
+ output :value_out, {
17
+ name: "o_#{full_name}", width: width,
18
+ array_size: array_size, array_format: array_port_format
19
+ }
20
+ end
21
+
22
+ main_code :bit_field, from_template: true
23
+
24
+ private
25
+
26
+ def latch_signal
27
+ reference_bit_field || latch[loop_variables]
28
+ end
29
+ end
30
+ end
@@ -20,7 +20,7 @@ RgGen.define_list_item_feature(
20
20
  end
21
21
 
22
22
  def read_set?
23
- [:w0crs, :w1crs, :wcrs].include?(bit_field.type)
23
+ [:w0crs, :w1crs, :wcrs].any? { |type| bit_field.type == type }
24
24
  end
25
25
 
26
26
  def write_action
@@ -51,9 +51,9 @@ module RgGen
51
51
 
52
52
  def index(offset_or_offsets = nil)
53
53
  offset_or_offsets
54
- .yield_self(&method(:index_operands))
55
- .yield_self(&method(:partial_sums))
56
- .yield_self(&method(:reduce_indices))
54
+ .then(&method(:index_operands))
55
+ .then(&method(:partial_sums))
56
+ .then(&method(:reduce_indices))
57
57
  end
58
58
 
59
59
  def inside_loop?
@@ -27,8 +27,8 @@ module RgGen
27
27
  def offset_address
28
28
  [*register_files, register]
29
29
  .flat_map(&method(:collect_offsets))
30
- .yield_self(&method(:partial_sums))
31
- .yield_self(&method(:format_offsets))
30
+ .then(&method(:partial_sums))
31
+ .then(&method(:format_offsets))
32
32
  end
33
33
 
34
34
  def collect_offsets(component)
@@ -32,9 +32,11 @@ RgGen.setup_plugin :'rggen-sv-rtl' do |plugin|
32
32
  'rtl/register/type/indirect',
33
33
  'rtl/bit_field/sv_rtl_top',
34
34
  'rtl/bit_field/type',
35
+ 'rtl/bit_field/type/custom',
35
36
  'rtl/bit_field/type/rc_w0c_w1c_wc_woc',
36
37
  'rtl/bit_field/type/ro_rotrg',
37
38
  'rtl/bit_field/type/rof',
39
+ 'rtl/bit_field/type/rol',
38
40
  'rtl/bit_field/type/row0trg_row1trg',
39
41
  'rtl/bit_field/type/rowo_rowotrg',
40
42
  'rtl/bit_field/type/rs_w0s_w1s_ws_wos',
@@ -2,6 +2,6 @@
2
2
 
3
3
  module RgGen
4
4
  module SystemVerilog
5
- VERSION = '0.27.1'
5
+ VERSION = '0.28.0'
6
6
  end
7
7
  end
metadata CHANGED
@@ -1,14 +1,14 @@
1
1
  --- !ruby/object:Gem::Specification
2
2
  name: rggen-systemverilog
3
3
  version: !ruby/object:Gem::Version
4
- version: 0.27.1
4
+ version: 0.28.0
5
5
  platform: ruby
6
6
  authors:
7
7
  - Taichi Ishitani
8
8
  autorequire:
9
9
  bindir: bin
10
10
  cert_chain: []
11
- date: 2022-08-30 00:00:00.000000000 Z
11
+ date: 2022-10-10 00:00:00.000000000 Z
12
12
  dependencies:
13
13
  - !ruby/object:Gem::Dependency
14
14
  name: bundler
@@ -55,7 +55,8 @@ files:
55
55
  - lib/rggen/systemverilog/common/utility/structure_definition.rb
56
56
  - lib/rggen/systemverilog/ral.rb
57
57
  - lib/rggen/systemverilog/ral/bit_field/type.rb
58
- - lib/rggen/systemverilog/ral/bit_field/type/rof.rb
58
+ - lib/rggen/systemverilog/ral/bit_field/type/custom.rb
59
+ - lib/rggen/systemverilog/ral/bit_field/type/rof_rol.rb
59
60
  - lib/rggen/systemverilog/ral/bit_field/type/rotrg_rwtrg_wotrg.rb
60
61
  - lib/rggen/systemverilog/ral/bit_field/type/row0trg_row1trg_w0trg_w1trg.rb
61
62
  - lib/rggen/systemverilog/ral/bit_field/type/rowo_rowotrg.rb
@@ -76,12 +77,16 @@ files:
76
77
  - lib/rggen/systemverilog/rtl.rb
77
78
  - lib/rggen/systemverilog/rtl/bit_field/sv_rtl_top.rb
78
79
  - lib/rggen/systemverilog/rtl/bit_field/type.rb
80
+ - lib/rggen/systemverilog/rtl/bit_field/type/custom.erb
81
+ - lib/rggen/systemverilog/rtl/bit_field/type/custom.rb
79
82
  - lib/rggen/systemverilog/rtl/bit_field/type/rc_w0c_w1c_wc_woc.erb
80
83
  - lib/rggen/systemverilog/rtl/bit_field/type/rc_w0c_w1c_wc_woc.rb
81
84
  - lib/rggen/systemverilog/rtl/bit_field/type/ro_rotrg.erb
82
85
  - lib/rggen/systemverilog/rtl/bit_field/type/ro_rotrg.rb
83
86
  - lib/rggen/systemverilog/rtl/bit_field/type/rof.erb
84
87
  - lib/rggen/systemverilog/rtl/bit_field/type/rof.rb
88
+ - lib/rggen/systemverilog/rtl/bit_field/type/rol.erb
89
+ - lib/rggen/systemverilog/rtl/bit_field/type/rol.rb
85
90
  - lib/rggen/systemverilog/rtl/bit_field/type/row0trg_row1trg.erb
86
91
  - lib/rggen/systemverilog/rtl/bit_field/type/row0trg_row1trg.rb
87
92
  - lib/rggen/systemverilog/rtl/bit_field/type/rowo_rowotrg.erb
@@ -158,5 +163,5 @@ requirements: []
158
163
  rubygems_version: 3.3.7
159
164
  signing_key:
160
165
  specification_version: 4
161
- summary: rggen-systemverilog-0.27.1
166
+ summary: rggen-systemverilog-0.28.0
162
167
  test_files: []
@@ -1,5 +0,0 @@
1
- # frozen_string_literal: true
2
-
3
- RgGen.define_list_item_feature(:bit_field, :type, :rof) do
4
- sv_ral { access 'RO' }
5
- end