rggen-systemverilog 0.27.1 → 0.28.0

checksums.yaml

@@ -1,7 +1,7 @@
 ---
 SHA256:
-  metadata.gz: b163ec13c4940ca6d489739aaae909dd3d189627eff20383cef519537bade127
-  data.tar.gz: 6bdfd55721b6e7c1a7250eed73cb5ca6ce1a2dba28d57e134b06b601397afabe
+  metadata.gz: 60c25d990cd209fcfe988002dee2325f1ec8d319295f9014cfe59715b87d44e7
+  data.tar.gz: db8957f134063c33fdd6efbfe3596e5871ac6f166359bb4f7b013f883ab9f3bd
 SHA512:
-  metadata.gz: f8327405b12e0d43ab8801772b85efd57f0a71f856f0f07efec961d97c7b70c4bacee05968303a41178201e9b90a16b289af24b23a71cb403ed5949fbeba0251
-  data.tar.gz: be673375b40e9d4c8241be45a4feb8ee4a09d815bc4ecd0926759f058dea021e8588b270de22408f8a34fa8cb5f50772f51addc47b3cfa60dba0c858064bccbd
+  metadata.gz: 759a5c90f3311b34f016b4fbade25d14785349f9ae88e1244596baa9b44abb80453eb3609ad2534d0b9d78a390aa8f39c747257c0a9ababa209b669cbb52b331
+  data.tar.gz: d0923aa115d8251966cad5ee14846b6037d1187e5c889ff288af6c0a26b132dcd7823916dd8d7214317dccbc849f85482fc1b2d947b6cf465cc218d8d704fef2

data/lib/rggen/systemverilog/common/utility/identifier.rb

@@ -76,8 +76,8 @@ module RgGen
           def __serialized_lsb__(array_index, lsb)
             index =
               array_index
-                .yield_self(&method(:__serialized_index__))
-                .yield_self(&method(:__enclose_index_in_parenthesis))
+                .then(&method(:__serialized_index__))
+                .then(&method(:__enclose_index_in_parenthesis))
             array_lsb = __reduce_array__([@width, index], :*, 1)
             __reduce_array__([array_lsb, lsb], :+, 0)
           end
@@ -87,7 +87,7 @@ module RgGen
               .reverse
               .zip(__index_factors__)
               .map { |i, f| __calc_index_value__(i, f) }
-              .yield_self { |values| __reduce_array__(values.reverse, :+, 0) }
+              .then { |values| __reduce_array__(values.reverse, :+, 0) }
           end
 
           def __enclose_index_in_parenthesis(index)

data/lib/rggen/systemverilog/ral/bit_field/type/custom.rb

@@ -0,0 +1,28 @@
+# frozen_string_literal: true
+
+RgGen.define_list_item_feature(:bit_field, :type, :custom) do
+  sv_ral do
+    model_name do
+      'rggen_ral_custom_field ' \
+        "#(#{sw_read}, #{sw_write}, #{write_once}, #{hw_update})"
+    end
+
+    private
+
+    def sw_read
+      string(bit_field.sw_read.upcase)
+    end
+
+    def sw_write
+      string(bit_field.sw_write.upcase)
+    end
+
+    def write_once
+      bit_field.sw_write_once? && 1 || 0
+    end
+
+    def hw_update
+      bit_field.hw_update? && 1 || 0
+    end
+  end
+end

data/lib/rggen/systemverilog/ral/bit_field/type/rof_rol.rb

@@ -0,0 +1,5 @@
+# frozen_string_literal: true
+
+RgGen.define_list_item_feature(:bit_field, :type, [:rof, :rol]) do
+  sv_ral { access 'RO' }
+end

data/lib/rggen/systemverilog/ral.rb

@@ -22,7 +22,8 @@ RgGen.setup_plugin :'rggen-sv-ral' do |plugin|
     'ral/register/type/external',
     'ral/register/type/indirect',
     'ral/bit_field/type',
-    'ral/bit_field/type/rof',
+    'ral/bit_field/type/custom',
+    'ral/bit_field/type/rof_rol',
     'ral/bit_field/type/rotrg_rwtrg_wotrg',
     'ral/bit_field/type/row0trg_row1trg_w0trg_w1trg',
     'ral/bit_field/type/rowo_rowotrg',

data/lib/rggen/systemverilog/rtl/bit_field/type/custom.erb

@@ -0,0 +1,25 @@
+rggen_bit_field #(
+  .WIDTH              (<%= width %>),
+  .INITIAL_VALUE      (<%= initial_value %>),
+  .SW_READ_ACTION     (<%= sw_read_action %>),
+  .SW_WRITE_ACTION    (<%= sw_write_action %>),
+  .SW_WRITE_ONCE      (<%= write_once %>),
+  .STORAGE            (<%= storage %>),
+  .EXTERNAL_READ_DATA (<%= external_read_data %>),
+  .TRIGGER            (<%= trigger %>)
+) u_bit_field (
+  .i_clk              (i_clk),
+  .i_rst_n            (i_rst_n),
+  .bit_field_if       (bit_field_sub_if),
+  .o_write_trigger    (<%= output_port(:write_trigger) %>),
+  .o_read_trigger     (<%= output_port(:read_trigger) %>),
+  .i_sw_write_enable  ('1),
+  .i_hw_write_enable  (<%= input_port(:hw_write_enable) %>),
+  .i_hw_write_data    (<%= input_port(:hw_write_data) %>),
+  .i_hw_set           (<%= input_port(:hw_set) %>),
+  .i_hw_clear         (<%= input_port(:hw_clear) %>),
+  .i_value            (<%= input_port(:value_in) %>),
+  .i_mask             ('1),
+  .o_value            (<%= output_port(:value_out) %>),
+  .o_value_unmasked   ()
+);

data/lib/rggen/systemverilog/rtl/bit_field/type/custom.rb

@@ -0,0 +1,121 @@
+# frozen_string_literal: true
+
+RgGen.define_list_item_feature(:bit_field, :type, :custom) do
+  sv_rtl do
+    build do
+      if external_read_data?
+        input :value_in, {
+          name: "i_#{full_name}", width: width,
+          array_size: array_size, array_format: array_port_format
+        }
+      else
+        output :value_out, {
+          name: "o_#{full_name}", width: width,
+          array_size: array_size, array_format: array_port_format
+        }
+      end
+      if bit_field.hw_write?
+        input :hw_write_enable, {
+          name: "i_#{full_name}_hw_write_enable", width: 1,
+          array_size: array_size, array_format: array_port_format
+        }
+        input :hw_write_data, {
+          name: "i_#{full_name}_hw_write_data", width: width,
+          array_size: array_size, array_format: array_port_format
+        }
+      end
+      if bit_field.hw_set?
+        input :hw_set, {
+          name: "i_#{full_name}_hw_set", width: width,
+          array_size: array_size, array_format: array_port_format
+        }
+      end
+      if bit_field.hw_clear?
+        input :hw_clear, {
+          name: "i_#{full_name}_hw_clear", width: width,
+          array_size: array_size, array_format: array_port_format
+        }
+      end
+      if bit_field.write_trigger?
+        output :write_trigger, {
+          name: "o_#{full_name}_write_trigger", width: 1,
+          array_size: array_size, array_format: array_port_format
+        }
+      end
+      if bit_field.read_trigger?
+        output :read_trigger, {
+          name: "o_#{full_name}_read_trigger", width: 1,
+          array_size: array_size, array_format: array_port_format
+        }
+      end
+    end
+
+    main_code :bit_field, from_template: true
+
+    private
+
+    def external_read_data?
+      !bit_field.sw_update? && !bit_field.hw_update?
+    end
+
+    def initial_value
+      external_read_data? && all_bits_0 || super
+    end
+
+    def sw_read_action
+      {
+        none: 'RGGEN_READ_NONE',
+        default: 'RGGEN_READ_DEFAULT',
+        set: 'RGGEN_READ_SET',
+        clear: 'RGGEN_READ_CLEAR'
+      }[bit_field.sw_read]
+    end
+
+    def sw_write_action
+      {
+        none: 'RGGEN_WRITE_NONE',
+        default: 'RGGEN_WRITE_DEFAULT',
+        clear_0: 'RGGEN_WRITE_0_CLEAR',
+        clear_1: 'RGGEN_WRITE_1_CLEAR',
+        clear: 'RGGEN_WRITE_CLEAR',
+        set_0: 'RGGEN_WRITE_0_SET',
+        set_1: 'RGGEN_WRITE_1_SET',
+        set: 'RGGEN_WRITE_SET',
+        toggle_0: 'RGGEN_WRITE_0_TOGGLE',
+        toggle_1: 'RGGEN_WRITE_1_TOGGLE'
+      }[bit_field.sw_write]
+    end
+
+    def write_once
+      bit_field.sw_write_once? && 1 || 0
+    end
+
+    def storage
+      external_read_data? && 0 || 1
+    end
+
+    def external_read_data
+      external_read_data? && 1 || 0
+    end
+
+    def trigger?
+      bit_field.write_trigger? || bit_field.read_trigger?
+    end
+
+    def trigger
+      trigger? && 1 || 0
+    end
+
+    def input_port(name)
+      find_port(name, all_bits_0)
+    end
+
+    def output_port(name)
+      find_port(name, '')
+    end
+
+    def find_port(name, default_value)
+      respond_to?(name) && __send__(name)[loop_variables] || default_value
+    end
+  end
+end

data/lib/rggen/systemverilog/rtl/bit_field/type/rol.erb

@@ -0,0 +1,20 @@
+rggen_bit_field #(
+  .WIDTH            (<%= width %>),
+  .INITIAL_VALUE    (<%= initial_value %>),
+  .SW_WRITE_ACTION  (RGGEN_WRITE_NONE)
+) u_bit_field (
+  .i_clk              (<%= clock %>),
+  .i_rst_n            (<%= reset %>),
+  .bit_field_if       (<%= bit_field_if %>),
+  .o_write_trigger    (),
+  .o_read_trigger     (),
+  .i_sw_write_enable  ('1),
+  .i_hw_write_enable  (<%= latch_signal %>),
+  .i_hw_write_data    (<%= value_in[loop_variables] %>),
+  .i_hw_set           ('0),
+  .i_hw_clear         ('0),
+  .i_value            ('0),
+  .i_mask             ('1),
+  .o_value            (<%= value_out[loop_variables] %>),
+  .o_value_unmasked   ()
+);

data/lib/rggen/systemverilog/rtl/bit_field/type/rol.rb

@@ -0,0 +1,30 @@
+# frozen_string_literal: true
+
+RgGen.define_list_item_feature(:bit_field, :type, :rol) do
+  sv_rtl do
+    build do
+      unless bit_field.reference?
+        input :latch, {
+          name: "i_#{full_name}_latch", width: 1,
+          array_size: array_size, array_format: array_port_format
+        }
+      end
+      input :value_in, {
+        name: "i_#{full_name}", width: width,
+        array_size: array_size, array_format: array_port_format
+      }
+      output :value_out, {
+        name: "o_#{full_name}", width: width,
+        array_size: array_size, array_format: array_port_format
+      }
+    end
+
+    main_code :bit_field, from_template: true
+
+    private
+
+    def latch_signal
+      reference_bit_field || latch[loop_variables]
+    end
+  end
+end

data/lib/rggen/systemverilog/rtl/bit_field/type/w0crs_w0src_w1crs_w1src_wcrs_wsrc.rb

@@ -20,7 +20,7 @@ RgGen.define_list_item_feature(
     end
 
     def read_set?
-      [:w0crs, :w1crs, :wcrs].include?(bit_field.type)
+      [:w0crs, :w1crs, :wcrs].any? { |type| bit_field.type == type }
     end
 
     def write_action

data/lib/rggen/systemverilog/rtl/register_index.rb

@@ -51,9 +51,9 @@ module RgGen
 
         def index(offset_or_offsets = nil)
           offset_or_offsets
-            .yield_self(&method(:index_operands))
-            .yield_self(&method(:partial_sums))
-            .yield_self(&method(:reduce_indices))
+            .then(&method(:index_operands))
+            .then(&method(:partial_sums))
+            .then(&method(:reduce_indices))
         end
 
         def inside_loop?

data/lib/rggen/systemverilog/rtl/register_type.rb

@@ -27,8 +27,8 @@ module RgGen
         def offset_address
           [*register_files, register]
             .flat_map(&method(:collect_offsets))
-            .yield_self(&method(:partial_sums))
-            .yield_self(&method(:format_offsets))
+            .then(&method(:partial_sums))
+            .then(&method(:format_offsets))
         end
 
         def collect_offsets(component)

data/lib/rggen/systemverilog/rtl.rb

@@ -32,9 +32,11 @@ RgGen.setup_plugin :'rggen-sv-rtl' do |plugin|
     'rtl/register/type/indirect',
     'rtl/bit_field/sv_rtl_top',
     'rtl/bit_field/type',
+    'rtl/bit_field/type/custom',
     'rtl/bit_field/type/rc_w0c_w1c_wc_woc',
     'rtl/bit_field/type/ro_rotrg',
     'rtl/bit_field/type/rof',
+    'rtl/bit_field/type/rol',
     'rtl/bit_field/type/row0trg_row1trg',
     'rtl/bit_field/type/rowo_rowotrg',
     'rtl/bit_field/type/rs_w0s_w1s_ws_wos',

data/lib/rggen/systemverilog/version.rb

@@ -2,6 +2,6 @@
 
 module RgGen
   module SystemVerilog
-    VERSION = '0.27.1'
+    VERSION = '0.28.0'
   end
 end

metadata

@@ -1,14 +1,14 @@
 --- !ruby/object:Gem::Specification
 name: rggen-systemverilog
 version: !ruby/object:Gem::Version
-  version: 0.27.1
+  version: 0.28.0
 platform: ruby
 authors:
 - Taichi Ishitani
 autorequire: 
 bindir: bin
 cert_chain: []
-date: 2022-08-30 00:00:00.000000000 Z
+date: 2022-10-10 00:00:00.000000000 Z
 dependencies:
 - !ruby/object:Gem::Dependency
   name: bundler
@@ -55,7 +55,8 @@ files:
 - lib/rggen/systemverilog/common/utility/structure_definition.rb
 - lib/rggen/systemverilog/ral.rb
 - lib/rggen/systemverilog/ral/bit_field/type.rb
-- lib/rggen/systemverilog/ral/bit_field/type/rof.rb
+- lib/rggen/systemverilog/ral/bit_field/type/custom.rb
+- lib/rggen/systemverilog/ral/bit_field/type/rof_rol.rb
 - lib/rggen/systemverilog/ral/bit_field/type/rotrg_rwtrg_wotrg.rb
 - lib/rggen/systemverilog/ral/bit_field/type/row0trg_row1trg_w0trg_w1trg.rb
 - lib/rggen/systemverilog/ral/bit_field/type/rowo_rowotrg.rb
@@ -76,12 +77,16 @@ files:
 - lib/rggen/systemverilog/rtl.rb
 - lib/rggen/systemverilog/rtl/bit_field/sv_rtl_top.rb
 - lib/rggen/systemverilog/rtl/bit_field/type.rb
+- lib/rggen/systemverilog/rtl/bit_field/type/custom.erb
+- lib/rggen/systemverilog/rtl/bit_field/type/custom.rb
 - lib/rggen/systemverilog/rtl/bit_field/type/rc_w0c_w1c_wc_woc.erb
 - lib/rggen/systemverilog/rtl/bit_field/type/rc_w0c_w1c_wc_woc.rb
 - lib/rggen/systemverilog/rtl/bit_field/type/ro_rotrg.erb
 - lib/rggen/systemverilog/rtl/bit_field/type/ro_rotrg.rb
 - lib/rggen/systemverilog/rtl/bit_field/type/rof.erb
 - lib/rggen/systemverilog/rtl/bit_field/type/rof.rb
+- lib/rggen/systemverilog/rtl/bit_field/type/rol.erb
+- lib/rggen/systemverilog/rtl/bit_field/type/rol.rb
 - lib/rggen/systemverilog/rtl/bit_field/type/row0trg_row1trg.erb
 - lib/rggen/systemverilog/rtl/bit_field/type/row0trg_row1trg.rb
 - lib/rggen/systemverilog/rtl/bit_field/type/rowo_rowotrg.erb
@@ -158,5 +163,5 @@ requirements: []
 rubygems_version: 3.3.7
 signing_key: 
 specification_version: 4
-summary: rggen-systemverilog-0.27.1
+summary: rggen-systemverilog-0.28.0
 test_files: []

data/lib/rggen/systemverilog/ral/bit_field/type/rof.rb

@@ -1,5 +0,0 @@
-# frozen_string_literal: true
-
-RgGen.define_list_item_feature(:bit_field, :type, :rof) do
-  sv_ral { access 'RO' }
-end