rggen-systemverilog 0.21.0 → 0.21.1

checksums.yaml

@@ -1,7 +1,7 @@
 ---
 SHA256:
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-  data.tar.gz: e6152bbed9134750811957f1d46aeba5769e12bf39196b440d3c4362c22bdd6a
+  metadata.gz: 1adaf5c9adddfa719676ff863b5172b976ce9e74ef3c979515fc0fa90c4bc3ca
+  data.tar.gz: 63469ade8ab437c95069caec46c58fd2aba98a44f18e09722d63bbf51f11f62c
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+  data.tar.gz: 017b6bf1fd636740ab84a55634f0979620ce9bbb27ea383c8db78850108448a8cfac58034eadef2f24e01a3384df803620bcd8f1bc2ec1882d914f3741e734ea

data/lib/rggen/systemverilog/rtl/register_block/protocol/axi4lite.erb

@@ -1,4 +1,5 @@
 rggen_axi4lite_adapter #(
+  .ID_WIDTH             (<%= id_width %>),
   .ADDRESS_WIDTH        (<%= address_width %>),
   .LOCAL_ADDRESS_WIDTH  (<%= local_address_width %>),
   .BUS_WIDTH            (<%= bus_width %>),

data/lib/rggen/systemverilog/rtl/register_block/protocol/axi4lite.rb

@@ -13,6 +13,9 @@ RgGen.define_list_item_feature(:register_block, :protocol, :axi4lite) do
 
   sv_rtl do
     build do
+      parameter :id_width, {
+        name: 'ID_WIDTH', data_type: :int, default: 0
+      }
       parameter :write_first, {
         name: 'WRITE_FIRST', data_type: :bit, default: 1
       }
@@ -28,6 +31,9 @@ RgGen.define_list_item_feature(:register_block, :protocol, :axi4lite) do
         output :awready, {
           name: 'o_awready', data_type: :logic, width: 1
         }
+        input :awid, {
+          name: 'i_awid', data_type: :logic, width: id_port_width
+        }
         input :awaddr, {
           name: 'i_awaddr', data_type: :logic, width: address_width
         }
@@ -49,6 +55,9 @@ RgGen.define_list_item_feature(:register_block, :protocol, :axi4lite) do
         output :bvalid, {
           name: 'o_bvalid', data_type: :logic, width: 1
         }
+        output :bid, {
+          name: 'o_bid', data_type: :logic, width: id_port_width
+        }
         input :bready, {
           name: 'i_bready', data_type: :logic, width: 1
         }
@@ -61,6 +70,9 @@ RgGen.define_list_item_feature(:register_block, :protocol, :axi4lite) do
         output :arready, {
           name: 'o_arready', data_type: :logic, width: 1
         }
+        input :arid, {
+          name: 'i_arid', data_type: :logic, width: id_port_width
+        }
         input :araddr, {
           name: 'i_araddr', data_type: :logic, width: address_width
         }
@@ -73,6 +85,9 @@ RgGen.define_list_item_feature(:register_block, :protocol, :axi4lite) do
         input :rready, {
           name: 'i_rready', data_type: :logic, width: 1
         }
+        output :rid, {
+          name: 'o_rid', data_type: :logic, width: id_port_width
+        }
         output :rdata, {
           name: 'o_rdata', data_type: :logic, width: bus_width
         }
@@ -81,13 +96,13 @@ RgGen.define_list_item_feature(:register_block, :protocol, :axi4lite) do
         }
         interface :axi4lite_if, {
           name: 'axi4lite_if', interface_type: 'rggen_axi4lite_if',
-          parameter_values: [address_width, bus_width],
+          parameter_values: [id_width, address_width, bus_width],
           variables: [
-            'awvalid', 'awready', 'awaddr', 'awprot',
+            'awvalid', 'awready', 'awid', 'awaddr', 'awprot',
             'wvalid', 'wready', 'wdata', 'wstrb',
-            'bvalid', 'bready', 'bresp',
-            'arvalid', 'arready', 'araddr', 'arprot',
-            'rvalid', 'rready', 'rdata', 'rresp'
+            'bvalid', 'bready', 'bid', 'bresp',
+            'arvalid', 'arready', 'arid', 'araddr', 'arprot',
+            'rvalid', 'rready', 'rid', 'rdata', 'rresp'
           ]
         }
       end
@@ -99,6 +114,7 @@ RgGen.define_list_item_feature(:register_block, :protocol, :axi4lite) do
         [
           [axi4lite_if.awvalid, awvalid],
           [awready, axi4lite_if.awready],
+          [axi4lite_if.awid, awid],
           [axi4lite_if.awaddr, awaddr],
           [axi4lite_if.awprot, awprot],
           [axi4lite_if.wvalid, wvalid],
@@ -107,17 +123,26 @@ RgGen.define_list_item_feature(:register_block, :protocol, :axi4lite) do
           [axi4lite_if.wstrb, wstrb],
           [bvalid, axi4lite_if.bvalid],
           [axi4lite_if.bready, bready],
+          [bid, axi4lite_if.bid],
           [bresp, axi4lite_if.bresp],
           [axi4lite_if.arvalid, arvalid],
           [arready, axi4lite_if.arready],
+          [axi4lite_if.arid, arid],
           [axi4lite_if.araddr, araddr],
           [axi4lite_if.arprot, arprot],
           [rvalid, axi4lite_if.rvalid],
           [axi4lite_if.rready, rready],
+          [rid, axi4lite_if.rid],
           [rdata, axi4lite_if.rdata],
           [rresp, axi4lite_if.rresp]
         ].each { |lhs, rhs| code << assign(lhs, rhs) << nl }
       end
     end
+
+    private
+
+    def id_port_width
+      "((#{id_width}>0)?#{id_width}:1)"
+    end
   end
 end

data/lib/rggen/systemverilog/version.rb

@@ -2,6 +2,6 @@
 
 module RgGen
   module SystemVerilog
-    VERSION = '0.21.0'
+    VERSION = '0.21.1'
   end
 end

metadata

@@ -1,14 +1,14 @@
 --- !ruby/object:Gem::Specification
 name: rggen-systemverilog
 version: !ruby/object:Gem::Version
-  version: 0.21.0
+  version: 0.21.1
 platform: ruby
 authors:
 - Taichi Ishitani
 autorequire: 
 bindir: bin
 cert_chain: []
-date: 2020-07-22 00:00:00.000000000 Z
+date: 2020-07-24 00:00:00.000000000 Z
 dependencies:
 - !ruby/object:Gem::Dependency
   name: docile
@@ -177,5 +177,5 @@ requirements: []
 rubygems_version: 3.1.2
 signing_key: 
 specification_version: 4
-summary: rggen-systemverilog-0.21.0
+summary: rggen-systemverilog-0.21.1
 test_files: []