rggen-systemverilog 0.21.0 → 0.21.1

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checksums.yaml CHANGED
@@ -1,7 +1,7 @@
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  SHA256:
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+ data.tar.gz: 017b6bf1fd636740ab84a55634f0979620ce9bbb27ea383c8db78850108448a8cfac58034eadef2f24e01a3384df803620bcd8f1bc2ec1882d914f3741e734ea
@@ -1,4 +1,5 @@
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  rggen_axi4lite_adapter #(
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+ .ID_WIDTH (<%= id_width %>),
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  .ADDRESS_WIDTH (<%= address_width %>),
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  .LOCAL_ADDRESS_WIDTH (<%= local_address_width %>),
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  .BUS_WIDTH (<%= bus_width %>),
@@ -13,6 +13,9 @@ RgGen.define_list_item_feature(:register_block, :protocol, :axi4lite) do
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  sv_rtl do
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  build do
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+ parameter :id_width, {
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+ name: 'ID_WIDTH', data_type: :int, default: 0
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+ }
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  parameter :write_first, {
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  name: 'WRITE_FIRST', data_type: :bit, default: 1
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  }
@@ -28,6 +31,9 @@ RgGen.define_list_item_feature(:register_block, :protocol, :axi4lite) do
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  output :awready, {
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  name: 'o_awready', data_type: :logic, width: 1
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  }
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+ input :awid, {
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+ name: 'i_awid', data_type: :logic, width: id_port_width
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+ }
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  input :awaddr, {
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  name: 'i_awaddr', data_type: :logic, width: address_width
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  }
@@ -49,6 +55,9 @@ RgGen.define_list_item_feature(:register_block, :protocol, :axi4lite) do
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  output :bvalid, {
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  name: 'o_bvalid', data_type: :logic, width: 1
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  }
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+ output :bid, {
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+ name: 'o_bid', data_type: :logic, width: id_port_width
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+ }
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  input :bready, {
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  name: 'i_bready', data_type: :logic, width: 1
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  }
@@ -61,6 +70,9 @@ RgGen.define_list_item_feature(:register_block, :protocol, :axi4lite) do
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  output :arready, {
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  name: 'o_arready', data_type: :logic, width: 1
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  }
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+ input :arid, {
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+ name: 'i_arid', data_type: :logic, width: id_port_width
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+ }
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  input :araddr, {
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  name: 'i_araddr', data_type: :logic, width: address_width
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  }
@@ -73,6 +85,9 @@ RgGen.define_list_item_feature(:register_block, :protocol, :axi4lite) do
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  input :rready, {
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  name: 'i_rready', data_type: :logic, width: 1
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  }
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+ output :rid, {
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+ name: 'o_rid', data_type: :logic, width: id_port_width
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+ }
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  output :rdata, {
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  name: 'o_rdata', data_type: :logic, width: bus_width
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  }
@@ -81,13 +96,13 @@ RgGen.define_list_item_feature(:register_block, :protocol, :axi4lite) do
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  }
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  interface :axi4lite_if, {
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  name: 'axi4lite_if', interface_type: 'rggen_axi4lite_if',
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- parameter_values: [address_width, bus_width],
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+ parameter_values: [id_width, address_width, bus_width],
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  variables: [
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- 'awvalid', 'awready', 'awaddr', 'awprot',
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+ 'awvalid', 'awready', 'awid', 'awaddr', 'awprot',
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  'wvalid', 'wready', 'wdata', 'wstrb',
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- 'bvalid', 'bready', 'bresp',
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- 'arvalid', 'arready', 'araddr', 'arprot',
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- 'rvalid', 'rready', 'rdata', 'rresp'
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+ 'bvalid', 'bready', 'bid', 'bresp',
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+ 'arvalid', 'arready', 'arid', 'araddr', 'arprot',
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+ 'rvalid', 'rready', 'rid', 'rdata', 'rresp'
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  ]
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  }
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  end
@@ -99,6 +114,7 @@ RgGen.define_list_item_feature(:register_block, :protocol, :axi4lite) do
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  [
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  [axi4lite_if.awvalid, awvalid],
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  [awready, axi4lite_if.awready],
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+ [axi4lite_if.awid, awid],
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  [axi4lite_if.awaddr, awaddr],
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  [axi4lite_if.awprot, awprot],
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  [axi4lite_if.wvalid, wvalid],
@@ -107,17 +123,26 @@ RgGen.define_list_item_feature(:register_block, :protocol, :axi4lite) do
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  [axi4lite_if.wstrb, wstrb],
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  [bvalid, axi4lite_if.bvalid],
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  [axi4lite_if.bready, bready],
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+ [bid, axi4lite_if.bid],
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  [bresp, axi4lite_if.bresp],
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  [axi4lite_if.arvalid, arvalid],
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  [arready, axi4lite_if.arready],
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+ [axi4lite_if.arid, arid],
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  [axi4lite_if.araddr, araddr],
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  [axi4lite_if.arprot, arprot],
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  [rvalid, axi4lite_if.rvalid],
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  [axi4lite_if.rready, rready],
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+ [rid, axi4lite_if.rid],
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  [rdata, axi4lite_if.rdata],
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  [rresp, axi4lite_if.rresp]
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  ].each { |lhs, rhs| code << assign(lhs, rhs) << nl }
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  end
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  end
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+
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+ private
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+
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+ def id_port_width
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+ "((#{id_width}>0)?#{id_width}:1)"
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+ end
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  end
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  end
@@ -2,6 +2,6 @@
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  module RgGen
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  module SystemVerilog
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- VERSION = '0.21.0'
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+ VERSION = '0.21.1'
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  end
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  end
metadata CHANGED
@@ -1,14 +1,14 @@
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  --- !ruby/object:Gem::Specification
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  name: rggen-systemverilog
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  version: !ruby/object:Gem::Version
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- version: 0.21.0
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+ version: 0.21.1
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  platform: ruby
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  authors:
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  - Taichi Ishitani
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  autorequire:
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  bindir: bin
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  cert_chain: []
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- date: 2020-07-22 00:00:00.000000000 Z
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+ date: 2020-07-24 00:00:00.000000000 Z
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  dependencies:
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  - !ruby/object:Gem::Dependency
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  name: docile
@@ -177,5 +177,5 @@ requirements: []
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  rubygems_version: 3.1.2
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  signing_key:
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  specification_version: 4
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- summary: rggen-systemverilog-0.21.0
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+ summary: rggen-systemverilog-0.21.1
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  test_files: []