rggen-systemverilog 0.20.0 → 0.21.0

checksums.yaml

@@ -1,7 +1,7 @@
 ---
 SHA256:
-  metadata.gz: 2074da98933b8ffc3d433d76d62acf272535b39d75db5322d4268ff4e80a9aa2
-  data.tar.gz: 17b8d6a0250efcf5f1f29f12445b1b08940b6abb2dc9811b77a5ed0865e92693
+  metadata.gz: 9b642c6748857ea3e78bcca5eeda544387fca31bdb85de17c51182e0da0f0c7f
+  data.tar.gz: e6152bbed9134750811957f1d46aeba5769e12bf39196b440d3c4362c22bdd6a
 SHA512:
-  metadata.gz: fcb60eb491c928338cc398fab428b80c3b3a132d3f6395b4ac73765d1503c2d403653d4285f8740079cc9f8155ef8d36042bf2c3f1b0d481fef2f3d08ab0a6f2
-  data.tar.gz: 97f26f59a360bfcd36fb47e2aa1455396d5b93e978c3de18a0395cb65bbdeab5ac3820f28a57dec8401af836064b3aace1f34241541ef59bb8fbd236cdf0e896
+  metadata.gz: 254ad7f6a05832eb99e6863fa82fab47edc1701d6e348dd5049ab9f9b3d16fe72ab29e82ba0611e8c9c0243675d21d4437d1a74e229eee383c199cb467c950f4
+  data.tar.gz: 7d3b17ff333fe06f68d1e802afd2cbcca411ef3bc4c34c54bc79487d821643772cf98be55eef61a1b826f506bfe816e6420caa3c4c63632aaf0f0fcc6374d8c3

data/lib/rggen/systemverilog/common/utility.rb

@@ -45,6 +45,10 @@ module RgGen
           end
         end
 
+        def all_bits_0
+          "'0"
+        end
+
         def bin(value, width = nil)
           if width
             width = bit_width(value, width)

data/lib/rggen/systemverilog/rtl/register_block/protocol.rb

@@ -65,21 +65,27 @@ RgGen.define_list_feature(:register_block, :protocol) do
 
     base_feature do
       build do
+        parameter :address_width, {
+          name: 'ADDRESS_WIDTH', data_type: :int, default: local_address_width
+        }
+        parameter :pre_decode, {
+          name: 'PRE_DECODE', data_type: :bit, width: 1, default: 0
+        }
+        parameter :base_address, {
+          name: 'BASE_ADDRESS', data_type: :bit, width: address_width,
+          default: all_bits_0
+        }
         parameter :error_status, {
           name: 'ERROR_STATUS', data_type: :bit, width: 1, default: 0
         }
         parameter :default_read_data, {
           name: 'DEFAULT_READ_DATA', data_type: :bit, width: bus_width,
-          default: hex(0, bus_width)
+          default: all_bits_0
         }
       end
 
       private
 
-      def address_width
-        configuration.address_width
-      end
-
       def bus_width
         configuration.bus_width
       end
@@ -96,6 +102,10 @@ RgGen.define_list_feature(:register_block, :protocol) do
         register_block.total_registers
       end
 
+      def byte_size
+        register_block.byte_size
+      end
+
       def clock
         register_block.clock
       end

data/lib/rggen/systemverilog/rtl/register_block/protocol/apb.erb

@@ -1,9 +1,13 @@
 rggen_apb_adapter #(
-  .ADDRESS_WIDTH      (<%= local_address_width %>),
-  .BUS_WIDTH          (<%= bus_width %>),
-  .REGISTERS          (<%= total_registers %>),
-  .ERROR_STATUS       (<%= error_status %>),
-  .DEFAULT_READ_DATA  (<%= default_read_data %>)
+  .ADDRESS_WIDTH        (<%= address_width %>),
+  .LOCAL_ADDRESS_WIDTH  (<%= local_address_width %>),
+  .BUS_WIDTH            (<%= bus_width %>),
+  .REGISTERS            (<%= total_registers %>),
+  .PRE_DECODE           (<%= pre_decode %>),
+  .BASE_ADDRESS         (<%= base_address %>),
+  .BYTE_SIZE            (<%= byte_size %>),
+  .ERROR_STATUS         (<%= error_status %>),
+  .DEFAULT_READ_DATA    (<%= default_read_data %>)
 ) u_adapter (
   .i_clk        (<%= clock %>),
   .i_rst_n      (<%= reset %>),

data/lib/rggen/systemverilog/rtl/register_block/protocol/axi4lite.erb

@@ -1,10 +1,14 @@
 rggen_axi4lite_adapter #(
-  .ADDRESS_WIDTH      (<%= local_address_width %>),
-  .BUS_WIDTH          (<%= bus_width %>),
-  .REGISTERS          (<%= total_registers %>),
-  .ERROR_STATUS       (<%= error_status %>),
-  .DEFAULT_READ_DATA  (<%= default_read_data %>),
-  .WRITE_FIRST        (<%= write_first %>)
+  .ADDRESS_WIDTH        (<%= address_width %>),
+  .LOCAL_ADDRESS_WIDTH  (<%= local_address_width %>),
+  .BUS_WIDTH            (<%= bus_width %>),
+  .REGISTERS            (<%= total_registers %>),
+  .PRE_DECODE           (<%= pre_decode %>),
+  .BASE_ADDRESS         (<%= base_address %>),
+  .BYTE_SIZE            (<%= byte_size %>),
+  .ERROR_STATUS         (<%= error_status %>),
+  .DEFAULT_READ_DATA    (<%= default_read_data %>),
+  .WRITE_FIRST          (<%= write_first %>)
 ) u_adapter (
   .i_clk        (<%= clock %>),
   .i_rst_n      (<%= reset %>),

data/lib/rggen/systemverilog/version.rb

@@ -2,6 +2,6 @@
 
 module RgGen
   module SystemVerilog
-    VERSION = '0.20.0'
+    VERSION = '0.21.0'
   end
 end

metadata

@@ -1,14 +1,14 @@
 --- !ruby/object:Gem::Specification
 name: rggen-systemverilog
 version: !ruby/object:Gem::Version
-  version: 0.20.0
+  version: 0.21.0
 platform: ruby
 authors:
 - Taichi Ishitani
 autorequire: 
 bindir: bin
 cert_chain: []
-date: 2020-07-06 00:00:00.000000000 Z
+date: 2020-07-22 00:00:00.000000000 Z
 dependencies:
 - !ruby/object:Gem::Dependency
   name: docile
@@ -177,5 +177,5 @@ requirements: []
 rubygems_version: 3.1.2
 signing_key: 
 specification_version: 4
-summary: rggen-systemverilog-0.20.0
+summary: rggen-systemverilog-0.21.0
 test_files: []