rggen-systemverilog 0.20.0 → 0.21.0

This diff represents the content of publicly available package versions that have been released to one of the supported registries. The information contained in this diff is provided for informational purposes only and reflects changes between package versions as they appear in their respective public registries.
Files changed (7) hide show
  1. checksums.yaml +4 -4
  2. data/lib/rggen/systemverilog/common/utility.rb +4 -0
  3. data/lib/rggen/systemverilog/rtl/register_block/protocol.rb +15 -5
  4. data/lib/rggen/systemverilog/rtl/register_block/protocol/apb.erb +9 -5
  5. data/lib/rggen/systemverilog/rtl/register_block/protocol/axi4lite.erb +10 -6
  6. data/lib/rggen/systemverilog/version.rb +1 -1
  7. metadata +3 -3
checksums.yaml CHANGED
@@ -1,7 +1,7 @@
1
1
  ---
2
2
  SHA256:
3
- metadata.gz: 2074da98933b8ffc3d433d76d62acf272535b39d75db5322d4268ff4e80a9aa2
4
- data.tar.gz: 17b8d6a0250efcf5f1f29f12445b1b08940b6abb2dc9811b77a5ed0865e92693
3
+ metadata.gz: 9b642c6748857ea3e78bcca5eeda544387fca31bdb85de17c51182e0da0f0c7f
4
+ data.tar.gz: e6152bbed9134750811957f1d46aeba5769e12bf39196b440d3c4362c22bdd6a
5
5
  SHA512:
6
- metadata.gz: fcb60eb491c928338cc398fab428b80c3b3a132d3f6395b4ac73765d1503c2d403653d4285f8740079cc9f8155ef8d36042bf2c3f1b0d481fef2f3d08ab0a6f2
7
- data.tar.gz: 97f26f59a360bfcd36fb47e2aa1455396d5b93e978c3de18a0395cb65bbdeab5ac3820f28a57dec8401af836064b3aace1f34241541ef59bb8fbd236cdf0e896
6
+ metadata.gz: 254ad7f6a05832eb99e6863fa82fab47edc1701d6e348dd5049ab9f9b3d16fe72ab29e82ba0611e8c9c0243675d21d4437d1a74e229eee383c199cb467c950f4
7
+ data.tar.gz: 7d3b17ff333fe06f68d1e802afd2cbcca411ef3bc4c34c54bc79487d821643772cf98be55eef61a1b826f506bfe816e6420caa3c4c63632aaf0f0fcc6374d8c3
data/lib/rggen/systemverilog/common/utility.rb CHANGED
@@ -45,6 +45,10 @@ module RgGen
45
45
  end
46
46
  end
47
47
 
48
+ def all_bits_0
49
+ "'0"
50
+ end
51
+
48
52
  def bin(value, width = nil)
49
53
  if width
50
54
  width = bit_width(value, width)
data/lib/rggen/systemverilog/rtl/register_block/protocol.rb CHANGED
@@ -65,21 +65,27 @@ RgGen.define_list_feature(:register_block, :protocol) do
65
65
 
66
66
  base_feature do
67
67
  build do
68
+ parameter :address_width, {
69
+ name: 'ADDRESS_WIDTH', data_type: :int, default: local_address_width
70
+ }
71
+ parameter :pre_decode, {
72
+ name: 'PRE_DECODE', data_type: :bit, width: 1, default: 0
73
+ }
74
+ parameter :base_address, {
75
+ name: 'BASE_ADDRESS', data_type: :bit, width: address_width,
76
+ default: all_bits_0
77
+ }
68
78
  parameter :error_status, {
69
79
  name: 'ERROR_STATUS', data_type: :bit, width: 1, default: 0
70
80
  }
71
81
  parameter :default_read_data, {
72
82
  name: 'DEFAULT_READ_DATA', data_type: :bit, width: bus_width,
73
- default: hex(0, bus_width)
83
+ default: all_bits_0
74
84
  }
75
85
  end
76
86
 
77
87
  private
78
88
 
79
- def address_width
80
- configuration.address_width
81
- end
82
-
83
89
  def bus_width
84
90
  configuration.bus_width
85
91
  end
@@ -96,6 +102,10 @@ RgGen.define_list_feature(:register_block, :protocol) do
96
102
  register_block.total_registers
97
103
  end
98
104
 
105
+ def byte_size
106
+ register_block.byte_size
107
+ end
108
+
99
109
  def clock
100
110
  register_block.clock
101
111
  end
data/lib/rggen/systemverilog/rtl/register_block/protocol/apb.erb CHANGED
@@ -1,9 +1,13 @@
1
1
  rggen_apb_adapter #(
2
- .ADDRESS_WIDTH (<%= local_address_width %>),
3
- .BUS_WIDTH (<%= bus_width %>),
4
- .REGISTERS (<%= total_registers %>),
5
- .ERROR_STATUS (<%= error_status %>),
6
- .DEFAULT_READ_DATA (<%= default_read_data %>)
2
+ .ADDRESS_WIDTH (<%= address_width %>),
3
+ .LOCAL_ADDRESS_WIDTH (<%= local_address_width %>),
4
+ .BUS_WIDTH (<%= bus_width %>),
5
+ .REGISTERS (<%= total_registers %>),
6
+ .PRE_DECODE (<%= pre_decode %>),
7
+ .BASE_ADDRESS (<%= base_address %>),
8
+ .BYTE_SIZE (<%= byte_size %>),
9
+ .ERROR_STATUS (<%= error_status %>),
10
+ .DEFAULT_READ_DATA (<%= default_read_data %>)
7
11
  ) u_adapter (
8
12
  .i_clk (<%= clock %>),
9
13
  .i_rst_n (<%= reset %>),
data/lib/rggen/systemverilog/rtl/register_block/protocol/axi4lite.erb CHANGED
@@ -1,10 +1,14 @@
1
1
  rggen_axi4lite_adapter #(
2
- .ADDRESS_WIDTH (<%= local_address_width %>),
3
- .BUS_WIDTH (<%= bus_width %>),
4
- .REGISTERS (<%= total_registers %>),
5
- .ERROR_STATUS (<%= error_status %>),
6
- .DEFAULT_READ_DATA (<%= default_read_data %>),
7
- .WRITE_FIRST (<%= write_first %>)
2
+ .ADDRESS_WIDTH (<%= address_width %>),
3
+ .LOCAL_ADDRESS_WIDTH (<%= local_address_width %>),
4
+ .BUS_WIDTH (<%= bus_width %>),
5
+ .REGISTERS (<%= total_registers %>),
6
+ .PRE_DECODE (<%= pre_decode %>),
7
+ .BASE_ADDRESS (<%= base_address %>),
8
+ .BYTE_SIZE (<%= byte_size %>),
9
+ .ERROR_STATUS (<%= error_status %>),
10
+ .DEFAULT_READ_DATA (<%= default_read_data %>),
11
+ .WRITE_FIRST (<%= write_first %>)
8
12
  ) u_adapter (
9
13
  .i_clk (<%= clock %>),
10
14
  .i_rst_n (<%= reset %>),
data/lib/rggen/systemverilog/version.rb CHANGED
@@ -2,6 +2,6 @@
2
2
 
3
3
  module RgGen
4
4
  module SystemVerilog
5
- VERSION = '0.20.0'
5
+ VERSION = '0.21.0'
6
6
  end
7
7
  end
metadata CHANGED
@@ -1,14 +1,14 @@
1
1
  --- !ruby/object:Gem::Specification
2
2
  name: rggen-systemverilog
3
3
  version: !ruby/object:Gem::Version
4
- version: 0.20.0
4
+ version: 0.21.0
5
5
  platform: ruby
6
6
  authors:
7
7
  - Taichi Ishitani
8
8
  autorequire:
9
9
  bindir: bin
10
10
  cert_chain: []
11
- date: 2020-07-06 00:00:00.000000000 Z
11
+ date: 2020-07-22 00:00:00.000000000 Z
12
12
  dependencies:
13
13
  - !ruby/object:Gem::Dependency
14
14
  name: docile
@@ -177,5 +177,5 @@ requirements: []
177
177
  rubygems_version: 3.1.2
178
178
  signing_key:
179
179
  specification_version: 4
180
- summary: rggen-systemverilog-0.20.0
180
+ summary: rggen-systemverilog-0.21.0
181
181
  test_files: []