rggen-systemverilog 0.16.0 → 0.17.0
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- checksums.yaml +4 -4
- data/lib/rggen/systemverilog/common/utility.rb +7 -2
- data/lib/rggen/systemverilog/common/utility/local_scope.rb +6 -0
- data/lib/rggen/systemverilog/ral/bit_field/type.rb +7 -8
- data/lib/rggen/systemverilog/rtl/bit_field/sv_rtl_top.rb +61 -0
- data/lib/rggen/systemverilog/rtl/bit_field/type.rb +2 -1
- data/lib/rggen/systemverilog/rtl/feature.rb +4 -3
- data/lib/rggen/systemverilog/rtl/register_block/protocol.rb +10 -0
- data/lib/rggen/systemverilog/rtl/register_block/protocol/apb.erb +5 -3
- data/lib/rggen/systemverilog/rtl/register_block/protocol/axi4lite.erb +6 -4
- data/lib/rggen/systemverilog/version.rb +1 -1
- metadata +3 -3
checksums.yaml
CHANGED
@@ -1,7 +1,7 @@
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1
1
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---
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2
2
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SHA256:
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3
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-
metadata.gz:
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4
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-
data.tar.gz:
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3
|
+
metadata.gz: 222ace28ccb5d96354eaf040d8c560e9c87ac73affba7bf5a3cac3a545898080
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4
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+
data.tar.gz: 7b652f0b27638800264f3bbfcd26d70ed0e89ad76f5e5ac7aeb8dc7023b8f09f
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5
5
|
SHA512:
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6
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-
metadata.gz:
|
7
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-
data.tar.gz:
|
6
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+
metadata.gz: 7f7c5046c3f60c3fe7b4114fa97b9b4029422b7a2eae52b3cdadd2919c83ed4378c900692eea1e1317d6dfbbc5846609a09fe86500060a0d6ba3c6376b2a9475
|
7
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+
data.tar.gz: 423aaf6583e719a1d3923de06651545e07fe5784fda7e469954975e36b3b5590019924caa5ef27bfdbc1f7ae25cbfc999e94ec43d504f3d08ded87acc8e68678
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@@ -24,8 +24,13 @@ module RgGen
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24
24
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"{#{Array(expressions).join(', ')}}"
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25
25
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end
|
26
26
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|
27
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-
def
|
28
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-
"
|
27
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+
def repeat(count, expression)
|
28
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+
"{#{count}{#{expression}}}"
|
29
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+
end
|
30
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+
|
31
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+
def array(expressions = nil, default: nil)
|
32
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+
default_item = default && "default: #{default}"
|
33
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+
"'#{concat([*Array(expressions), default_item].compact)}"
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29
34
|
end
|
30
35
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|
31
36
|
def function_call(name, expressions = nil)
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@@ -6,6 +6,7 @@ module RgGen
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|
6
6
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module Utility
|
7
7
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class LocalScope < StructureDefinition
|
8
8
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define_attribute :name
|
9
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+
define_attribute :parameters
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9
10
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define_attribute :variables
|
10
11
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define_attribute :loop_size
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11
12
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@@ -28,6 +29,7 @@ module RgGen
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28
29
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def pre_body_code(code)
|
29
30
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genvar_declarations(code)
|
30
31
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generate_for_header(code)
|
32
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+
parameter_declarations(code)
|
31
33
|
variable_declarations(code)
|
32
34
|
end
|
33
35
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|
@@ -47,6 +49,10 @@ module RgGen
|
|
47
49
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"for (#{genvar} = 0;#{genvar} < #{size};++#{genvar}) begin : g"
|
48
50
|
end
|
49
51
|
|
52
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+
def parameter_declarations(code)
|
53
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+
add_declarations_to_body(code, Array(parameters))
|
54
|
+
end
|
55
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+
|
50
56
|
def variable_declarations(code)
|
51
57
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add_declarations_to_body(code, Array(variables))
|
52
58
|
end
|
@@ -30,11 +30,8 @@ RgGen.define_list_feature(:bit_field, :type) do
|
|
30
30
|
end
|
31
31
|
|
32
32
|
def model_name
|
33
|
-
|
34
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-
|
35
|
-
else
|
36
|
-
helper.model_name || :rggen_ral_field
|
37
|
-
end
|
33
|
+
name = helper.model_name
|
34
|
+
name&.is_a?(Proc) && instance_eval(&name) || name || :rggen_ral_field
|
38
35
|
end
|
39
36
|
|
40
37
|
def constructors
|
@@ -54,7 +51,7 @@ RgGen.define_list_feature(:bit_field, :type) do
|
|
54
51
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def arguments(index)
|
55
52
|
[
|
56
53
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ral_model[index], bit_field.lsb(index), bit_field.width,
|
57
|
-
access, volatile, reset_value, valid_reset
|
54
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+
access, volatile, reset_value(index), valid_reset
|
58
55
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]
|
59
56
|
end
|
60
57
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|
@@ -62,8 +59,10 @@ RgGen.define_list_feature(:bit_field, :type) do
|
|
62
59
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bit_field.volatile? && 1 || 0
|
63
60
|
end
|
64
61
|
|
65
|
-
def reset_value
|
66
|
-
|
62
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+
def reset_value(index)
|
63
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+
value =
|
64
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+
bit_field.initial_values&.at(index) || bit_field.initial_value || 0
|
65
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+
hex(value, bit_field.width)
|
67
66
|
end
|
68
67
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|
69
68
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def valid_reset
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@@ -8,6 +8,19 @@ RgGen.define_simple_feature(:bit_field, :sv_rtl_top) do
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|
8
8
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export :value
|
9
9
|
|
10
10
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build do
|
11
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+
if fixed_initial_value?
|
12
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+
localparam :bit_field, :initial_value, {
|
13
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+
name: initial_value_name, data_type: :bit, width: bit_field.width,
|
14
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+
array_size: initial_value_size, array_format: initial_value_format,
|
15
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+
default: initial_value_lhs
|
16
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+
}
|
17
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+
elsif initial_value?
|
18
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+
parameter :register_block, :initial_value, {
|
19
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+
name: initial_value_name, data_type: :bit, width: bit_field.width,
|
20
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+
array_size: initial_value_size, array_format: initial_value_format,
|
21
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+
default: initial_value_lhs
|
22
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+
}
|
23
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+
end
|
11
24
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interface :bit_field, :bit_field_sub_if, {
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12
25
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name: 'bit_field_sub_if',
|
13
26
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interface_type: 'rggen_bit_field_if',
|
@@ -18,6 +31,7 @@ RgGen.define_simple_feature(:bit_field, :sv_rtl_top) do
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18
31
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main_code :register do
|
19
32
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local_scope("g_#{bit_field.name}") do |scope|
|
20
33
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scope.loop_size loop_size
|
34
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+
scope.parameters parameters
|
21
35
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scope.variables variables
|
22
36
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scope.body(&method(:body_code))
|
23
37
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end
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@@ -57,6 +71,49 @@ RgGen.define_simple_feature(:bit_field, :sv_rtl_top) do
|
|
57
71
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|
58
72
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private
|
59
73
|
|
74
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+
[:fixed_initial_value?, :initial_value_array?, :initial_value?].each do |m|
|
75
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+
define_method(m) { bit_field.__send__(__method__) }
|
76
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+
end
|
77
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+
|
78
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+
def initial_value_name
|
79
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+
identifiers = []
|
80
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+
identifiers << bit_field.full_name('_') unless fixed_initial_value?
|
81
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+
identifiers << 'initial_value'
|
82
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+
identifiers.join('_').upcase
|
83
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+
end
|
84
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+
|
85
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+
def initial_value_size
|
86
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+
initial_value_array? && [bit_field.sequence_size] || nil
|
87
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+
end
|
88
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+
|
89
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+
def initial_value_format
|
90
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+
fixed_initial_value? && :unpacked ||
|
91
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+
configuration.array_port_format
|
92
|
+
end
|
93
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+
|
94
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+
def initial_value_lhs
|
95
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+
initial_value_array? && initial_value_array_lhs || sized_initial_value
|
96
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+
end
|
97
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+
|
98
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+
def initial_value_array_lhs
|
99
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+
if fixed_initial_value?
|
100
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+
array(sized_initial_values)
|
101
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+
elsif initial_value_format == :unpacked
|
102
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+
array(default: sized_initial_value)
|
103
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+
else
|
104
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+
repeat(bit_field.sequence_size, sized_initial_value)
|
105
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+
end
|
106
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+
end
|
107
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+
|
108
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+
def sized_initial_value
|
109
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+
bit_field.initial_value &&
|
110
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+
hex(bit_field.initial_value, bit_field.width)
|
111
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+
end
|
112
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+
|
113
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+
def sized_initial_values
|
114
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+
bit_field.initial_values&.map { |v| hex(v, bit_field.width) }
|
115
|
+
end
|
116
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+
|
60
117
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def inside_loop?
|
61
118
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register.array? || bit_field.sequential?
|
62
119
|
end
|
@@ -66,6 +123,10 @@ RgGen.define_simple_feature(:bit_field, :sv_rtl_top) do
|
|
66
123
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{ index_name => bit_field.sequence_size }
|
67
124
|
end
|
68
125
|
|
126
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+
def parameters
|
127
|
+
bit_field.declarations(:bit_field, :parameter)
|
128
|
+
end
|
129
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+
|
69
130
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def variables
|
70
131
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bit_field.declarations(:bit_field, :variable)
|
71
132
|
end
|
@@ -26,9 +26,9 @@ module RgGen
|
|
26
26
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InterfacePort.new(attributes, &block)
|
27
27
|
end
|
28
28
|
|
29
|
-
def create_parameter(
|
29
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+
def create_parameter(parameter_type, attributes, block)
|
30
30
|
DataObject.new(
|
31
|
-
:parameter, attributes.merge(parameter_type:
|
31
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+
:parameter, attributes.merge(parameter_type: parameter_type), &block
|
32
32
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)
|
33
33
|
end
|
34
34
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@@ -38,7 +38,8 @@ module RgGen
|
|
38
38
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[:input, :create_argument, :port],
|
39
39
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[:output, :create_argument, :port],
|
40
40
|
[:interface_port, :create_interface_port, :port],
|
41
|
-
[:parameter, :create_parameter, :parameter]
|
41
|
+
[:parameter, :create_parameter, :parameter],
|
42
|
+
[:localparam, :create_parameter, :parameter]
|
42
43
|
].each do |entity, creation_method, declaration_type|
|
43
44
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define_entity(entity, creation_method, declaration_type)
|
44
45
|
end
|
@@ -64,6 +64,16 @@ RgGen.define_list_feature(:register_block, :protocol) do
|
|
64
64
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shared_context.feature_registry(registry)
|
65
65
|
|
66
66
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base_feature do
|
67
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+
build do
|
68
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+
parameter :register_block, :error_status, {
|
69
|
+
name: 'ERROR_STATUS', data_type: :bit, width: 1, default: 0
|
70
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+
}
|
71
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+
parameter :register_block, :default_read_data, {
|
72
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+
name: 'DEFAULT_READ_DATA', data_type: :bit, width: bus_width,
|
73
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+
default: hex(0, bus_width)
|
74
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+
}
|
75
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+
end
|
76
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+
|
67
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private
|
68
78
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|
69
79
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def address_width
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@@ -1,7 +1,9 @@
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1
1
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rggen_apb_adapter #(
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2
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-
.ADDRESS_WIDTH
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3
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-
.BUS_WIDTH
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4
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-
.REGISTERS
|
2
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+
.ADDRESS_WIDTH (<%= local_address_width %>),
|
3
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+
.BUS_WIDTH (<%= bus_width %>),
|
4
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+
.REGISTERS (<%= total_registers %>),
|
5
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+
.ERROR_STATUS (<%= error_status %>),
|
6
|
+
.DEFAULT_READ_DATA (<%= default_read_data %>)
|
5
7
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) u_adapter (
|
6
8
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.i_clk (<%= clock %>),
|
7
9
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.i_rst_n (<%= reset %>),
|
@@ -1,8 +1,10 @@
|
|
1
1
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rggen_axi4lite_adapter #(
|
2
|
-
.ADDRESS_WIDTH
|
3
|
-
.BUS_WIDTH
|
4
|
-
.REGISTERS
|
5
|
-
.
|
2
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+
.ADDRESS_WIDTH (<%= local_address_width %>),
|
3
|
+
.BUS_WIDTH (<%= bus_width %>),
|
4
|
+
.REGISTERS (<%= total_registers %>),
|
5
|
+
.ERROR_STATUS (<%= error_status %>),
|
6
|
+
.DEFAULT_READ_DATA (<%= default_read_data %>),
|
7
|
+
.WRITE_FIRST (<%= write_first %>)
|
6
8
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) u_adapter (
|
7
9
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.i_clk (<%= clock %>),
|
8
10
|
.i_rst_n (<%= reset %>),
|
metadata
CHANGED
@@ -1,14 +1,14 @@
|
|
1
1
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--- !ruby/object:Gem::Specification
|
2
2
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name: rggen-systemverilog
|
3
3
|
version: !ruby/object:Gem::Version
|
4
|
-
version: 0.
|
4
|
+
version: 0.17.0
|
5
5
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platform: ruby
|
6
6
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authors:
|
7
7
|
- Taichi Ishitani
|
8
8
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autorequire:
|
9
9
|
bindir: bin
|
10
10
|
cert_chain: []
|
11
|
-
date: 2019-
|
11
|
+
date: 2019-11-13 00:00:00.000000000 Z
|
12
12
|
dependencies:
|
13
13
|
- !ruby/object:Gem::Dependency
|
14
14
|
name: docile
|
@@ -170,5 +170,5 @@ requirements: []
|
|
170
170
|
rubygems_version: 3.0.3
|
171
171
|
signing_key:
|
172
172
|
specification_version: 4
|
173
|
-
summary: rggen-systemverilog-0.
|
173
|
+
summary: rggen-systemverilog-0.17.0
|
174
174
|
test_files: []
|