rggen-systemverilog 0.16.0 → 0.17.0

checksums.yaml

@@ -1,7 +1,7 @@
 ---
 SHA256:
-  metadata.gz: 62ec6f5cb3ee1c7f88c2b46fa979376823e7d5f5098acf1cc41dd3b10a89de9b
-  data.tar.gz: 5c8976e639c443eb330be03e2c0487c261c50e46ef2fbac6e70adfb514023638
+  metadata.gz: 222ace28ccb5d96354eaf040d8c560e9c87ac73affba7bf5a3cac3a545898080
+  data.tar.gz: 7b652f0b27638800264f3bbfcd26d70ed0e89ad76f5e5ac7aeb8dc7023b8f09f
 SHA512:
-  metadata.gz: 1f8e2778fd4771395143a01cc84e59077e097f33b50b4083d7209e32a81a1988f36d7af140661b07e6a975df35a5e266e8d82272fa6134ac0bd7ae2929aa0d04
-  data.tar.gz: ea482e0d904d91faf76b9575a4807ab92e55056c2ecb16fe4078cf03012314ba9d374088ca34570adbc9d64edec6fa21b647d7476b4c32e365c25946563afe36
+  metadata.gz: 7f7c5046c3f60c3fe7b4114fa97b9b4029422b7a2eae52b3cdadd2919c83ed4378c900692eea1e1317d6dfbbc5846609a09fe86500060a0d6ba3c6376b2a9475
+  data.tar.gz: 423aaf6583e719a1d3923de06651545e07fe5784fda7e469954975e36b3b5590019924caa5ef27bfdbc1f7ae25cbfc999e94ec43d504f3d08ded87acc8e68678

data/lib/rggen/systemverilog/common/utility.rb

@@ -24,8 +24,13 @@ module RgGen
           "{#{Array(expressions).join(', ')}}"
         end
 
-        def array(expressions)
-          "'#{concat(expressions)}"
+        def repeat(count, expression)
+          "{#{count}{#{expression}}}"
+        end
+
+        def array(expressions = nil, default: nil)
+          default_item = default && "default: #{default}"
+          "'#{concat([*Array(expressions), default_item].compact)}"
         end
 
         def function_call(name, expressions = nil)

data/lib/rggen/systemverilog/common/utility/local_scope.rb

@@ -6,6 +6,7 @@ module RgGen
       module Utility
         class LocalScope < StructureDefinition
           define_attribute :name
+          define_attribute :parameters
           define_attribute :variables
           define_attribute :loop_size
 
@@ -28,6 +29,7 @@ module RgGen
           def pre_body_code(code)
             genvar_declarations(code)
             generate_for_header(code)
+            parameter_declarations(code)
             variable_declarations(code)
           end
 
@@ -47,6 +49,10 @@ module RgGen
             "for (#{genvar} = 0;#{genvar} < #{size};++#{genvar}) begin : g"
           end
 
+          def parameter_declarations(code)
+            add_declarations_to_body(code, Array(parameters))
+          end
+
           def variable_declarations(code)
             add_declarations_to_body(code, Array(variables))
           end

data/lib/rggen/systemverilog/ral/bit_field/type.rb

@@ -30,11 +30,8 @@ RgGen.define_list_feature(:bit_field, :type) do
       end
 
       def model_name
-        if helper.model_name&.is_a?(Proc)
-          instance_eval(&helper.model_name)
-        else
-          helper.model_name || :rggen_ral_field
-        end
+        name = helper.model_name
+        name&.is_a?(Proc) && instance_eval(&name) || name || :rggen_ral_field
       end
 
       def constructors
@@ -54,7 +51,7 @@ RgGen.define_list_feature(:bit_field, :type) do
       def arguments(index)
         [
           ral_model[index], bit_field.lsb(index), bit_field.width,
-          access, volatile, reset_value, valid_reset
+          access, volatile, reset_value(index), valid_reset
         ]
       end
 
@@ -62,8 +59,10 @@ RgGen.define_list_feature(:bit_field, :type) do
         bit_field.volatile? && 1 || 0
       end
 
-      def reset_value
-        hex(bit_field.initial_value, bit_field.width)
+      def reset_value(index)
+        value =
+          bit_field.initial_values&.at(index) || bit_field.initial_value || 0
+        hex(value, bit_field.width)
       end
 
       def valid_reset

data/lib/rggen/systemverilog/rtl/bit_field/sv_rtl_top.rb

@@ -8,6 +8,19 @@ RgGen.define_simple_feature(:bit_field, :sv_rtl_top) do
     export :value
 
     build do
+      if fixed_initial_value?
+        localparam :bit_field, :initial_value, {
+          name: initial_value_name, data_type: :bit, width: bit_field.width,
+          array_size: initial_value_size, array_format: initial_value_format,
+          default: initial_value_lhs
+        }
+      elsif initial_value?
+        parameter :register_block, :initial_value, {
+          name: initial_value_name, data_type: :bit, width: bit_field.width,
+          array_size: initial_value_size, array_format: initial_value_format,
+          default: initial_value_lhs
+        }
+      end
       interface :bit_field, :bit_field_sub_if, {
         name: 'bit_field_sub_if',
         interface_type: 'rggen_bit_field_if',
@@ -18,6 +31,7 @@ RgGen.define_simple_feature(:bit_field, :sv_rtl_top) do
     main_code :register do
       local_scope("g_#{bit_field.name}") do |scope|
         scope.loop_size loop_size
+        scope.parameters parameters
         scope.variables variables
         scope.body(&method(:body_code))
       end
@@ -57,6 +71,49 @@ RgGen.define_simple_feature(:bit_field, :sv_rtl_top) do
 
     private
 
+    [:fixed_initial_value?, :initial_value_array?, :initial_value?].each do |m|
+      define_method(m) { bit_field.__send__(__method__) }
+    end
+
+    def initial_value_name
+      identifiers = []
+      identifiers << bit_field.full_name('_') unless fixed_initial_value?
+      identifiers << 'initial_value'
+      identifiers.join('_').upcase
+    end
+
+    def initial_value_size
+      initial_value_array? && [bit_field.sequence_size] || nil
+    end
+
+    def initial_value_format
+      fixed_initial_value? && :unpacked ||
+        configuration.array_port_format
+    end
+
+    def initial_value_lhs
+      initial_value_array? && initial_value_array_lhs || sized_initial_value
+    end
+
+    def initial_value_array_lhs
+      if fixed_initial_value?
+        array(sized_initial_values)
+      elsif initial_value_format == :unpacked
+        array(default: sized_initial_value)
+      else
+        repeat(bit_field.sequence_size, sized_initial_value)
+      end
+    end
+
+    def sized_initial_value
+      bit_field.initial_value &&
+        hex(bit_field.initial_value, bit_field.width)
+    end
+
+    def sized_initial_values
+      bit_field.initial_values&.map { |v| hex(v, bit_field.width) }
+    end
+
     def inside_loop?
       register.array? || bit_field.sequential?
     end
@@ -66,6 +123,10 @@ RgGen.define_simple_feature(:bit_field, :sv_rtl_top) do
         { index_name => bit_field.sequence_size }
     end
 
+    def parameters
+      bit_field.declarations(:bit_field, :parameter)
+    end
+
     def variables
       bit_field.declarations(:bit_field, :variable)
     end

data/lib/rggen/systemverilog/rtl/bit_field/type.rb

@@ -30,7 +30,8 @@ RgGen.define_list_feature(:bit_field, :type) do
       end
 
       def initial_value
-        hex(bit_field.initial_value, bit_field.width)
+        index = bit_field.initial_value_array? && bit_field.local_index || nil
+        bit_field.initial_value[index]
       end
 
       def mask

data/lib/rggen/systemverilog/rtl/feature.rb

@@ -26,9 +26,9 @@ module RgGen
           InterfacePort.new(attributes, &block)
         end
 
-        def create_parameter(_, attributes, block)
+        def create_parameter(parameter_type, attributes, block)
           DataObject.new(
-            :parameter, attributes.merge(parameter_type: :parameter), &block
+            :parameter, attributes.merge(parameter_type: parameter_type), &block
           )
         end
 
@@ -38,7 +38,8 @@ module RgGen
           [:input, :create_argument, :port],
           [:output, :create_argument, :port],
           [:interface_port, :create_interface_port, :port],
-          [:parameter, :create_parameter, :parameter]
+          [:parameter, :create_parameter, :parameter],
+          [:localparam, :create_parameter, :parameter]
         ].each do |entity, creation_method, declaration_type|
           define_entity(entity, creation_method, declaration_type)
         end

data/lib/rggen/systemverilog/rtl/register_block/protocol.rb

@@ -64,6 +64,16 @@ RgGen.define_list_feature(:register_block, :protocol) do
     shared_context.feature_registry(registry)
 
     base_feature do
+      build do
+        parameter :register_block, :error_status, {
+          name: 'ERROR_STATUS', data_type: :bit, width: 1, default: 0
+        }
+        parameter :register_block, :default_read_data, {
+          name: 'DEFAULT_READ_DATA', data_type: :bit, width: bus_width,
+          default: hex(0, bus_width)
+        }
+      end
+
       private
 
       def address_width

data/lib/rggen/systemverilog/rtl/register_block/protocol/apb.erb

@@ -1,7 +1,9 @@
 rggen_apb_adapter #(
-  .ADDRESS_WIDTH  (<%= local_address_width %>),
-  .BUS_WIDTH      (<%= bus_width %>),
-  .REGISTERS      (<%= total_registers %>)
+  .ADDRESS_WIDTH      (<%= local_address_width %>),
+  .BUS_WIDTH          (<%= bus_width %>),
+  .REGISTERS          (<%= total_registers %>),
+  .ERROR_STATUS       (<%= error_status %>),
+  .DEFAULT_READ_DATA  (<%= default_read_data %>)
 ) u_adapter (
   .i_clk        (<%= clock %>),
   .i_rst_n      (<%= reset %>),

data/lib/rggen/systemverilog/rtl/register_block/protocol/axi4lite.erb

@@ -1,8 +1,10 @@
 rggen_axi4lite_adapter #(
-  .ADDRESS_WIDTH  (<%= local_address_width %>),
-  .BUS_WIDTH      (<%= bus_width %>),
-  .REGISTERS      (<%= total_registers %>),
-  .WRITE_FIRST    (<%= write_first %>)
+  .ADDRESS_WIDTH      (<%= local_address_width %>),
+  .BUS_WIDTH          (<%= bus_width %>),
+  .REGISTERS          (<%= total_registers %>),
+  .ERROR_STATUS       (<%= error_status %>),
+  .DEFAULT_READ_DATA  (<%= default_read_data %>),
+  .WRITE_FIRST        (<%= write_first %>)
 ) u_adapter (
   .i_clk        (<%= clock %>),
   .i_rst_n      (<%= reset %>),

data/lib/rggen/systemverilog/version.rb

@@ -2,6 +2,6 @@
 
 module RgGen
   module SystemVerilog
-    VERSION = '0.16.0'
+    VERSION = '0.17.0'
   end
 end

metadata

@@ -1,14 +1,14 @@
 --- !ruby/object:Gem::Specification
 name: rggen-systemverilog
 version: !ruby/object:Gem::Version
-  version: 0.16.0
+  version: 0.17.0
 platform: ruby
 authors:
 - Taichi Ishitani
 autorequire: 
 bindir: bin
 cert_chain: []
-date: 2019-10-01 00:00:00.000000000 Z
+date: 2019-11-13 00:00:00.000000000 Z
 dependencies:
 - !ruby/object:Gem::Dependency
   name: docile
@@ -170,5 +170,5 @@ requirements: []
 rubygems_version: 3.0.3
 signing_key: 
 specification_version: 4
-summary: rggen-systemverilog-0.16.0
+summary: rggen-systemverilog-0.17.0
 test_files: []