rggen-systemverilog 0.15.0 → 0.16.0
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- checksums.yaml +4 -4
- data/lib/rggen/systemverilog/ral/bit_field/type.rb +2 -2
- data/lib/rggen/systemverilog/ral/register/type.rb +2 -2
- data/lib/rggen/systemverilog/rtl/bit_field/type.rb +2 -2
- data/lib/rggen/systemverilog/rtl/global/array_port_format.rb +2 -0
- data/lib/rggen/systemverilog/rtl/global/fold_sv_interface_port.rb +4 -0
- data/lib/rggen/systemverilog/rtl/register/type.rb +5 -4
- data/lib/rggen/systemverilog/rtl/register_block/protocol.rb +4 -4
- data/lib/rggen/systemverilog/version.rb +1 -1
- metadata +3 -3
checksums.yaml
CHANGED
@@ -1,7 +1,7 @@
|
|
1
1
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---
|
2
2
|
SHA256:
|
3
|
-
metadata.gz:
|
4
|
-
data.tar.gz:
|
3
|
+
metadata.gz: 62ec6f5cb3ee1c7f88c2b46fa979376823e7d5f5098acf1cc41dd3b10a89de9b
|
4
|
+
data.tar.gz: 5c8976e639c443eb330be03e2c0487c261c50e46ef2fbac6e70adfb514023638
|
5
5
|
SHA512:
|
6
|
-
metadata.gz:
|
7
|
-
data.tar.gz:
|
6
|
+
metadata.gz: 1f8e2778fd4771395143a01cc84e59077e097f33b50b4083d7209e32a81a1988f36d7af140661b07e6a975df35a5e266e8d82272fa6134ac0bd7ae2929aa0d04
|
7
|
+
data.tar.gz: ea482e0d904d91faf76b9575a4807ab92e55056c2ecb16fe4078cf03012314ba9d374088ca34570adbc9d64edec6fa21b647d7476b4c32e365c25946563afe36
|
@@ -146,8 +146,8 @@ RgGen.define_list_feature(:register, :type) do
|
|
146
146
|
end
|
147
147
|
|
148
148
|
factory do
|
149
|
-
def
|
150
|
-
|
149
|
+
def target_feature_key(_configuration, register)
|
150
|
+
register.type
|
151
151
|
end
|
152
152
|
end
|
153
153
|
end
|
@@ -59,8 +59,8 @@ RgGen.define_list_feature(:bit_field, :type) do
|
|
59
59
|
end
|
60
60
|
|
61
61
|
factory do
|
62
|
-
def
|
63
|
-
target_features
|
62
|
+
def target_feature_key(_configuration, bit_field)
|
63
|
+
target_features.key?(bit_field.type) && bit_field.type || (
|
64
64
|
error "code generator for #{bit_field.type} " \
|
65
65
|
'bit field type is not implemented'
|
66
66
|
)
|
@@ -53,10 +53,11 @@ RgGen.define_list_feature(:register, :type) do
|
|
53
53
|
end
|
54
54
|
|
55
55
|
factory do
|
56
|
-
def
|
57
|
-
|
58
|
-
|
59
|
-
|
56
|
+
def target_feature_key(_configuration, register)
|
57
|
+
type = register.type
|
58
|
+
(target_features.key?(type) || type == :default) && type ||
|
59
|
+
begin
|
60
|
+
error "code generator for #{type} register type " \
|
60
61
|
'is not implemented'
|
61
62
|
end
|
62
63
|
end
|
@@ -40,8 +40,8 @@ RgGen.define_list_feature(:register_block, :protocol) do
|
|
40
40
|
(error 'no protocols are available', position)
|
41
41
|
end
|
42
42
|
|
43
|
-
def
|
44
|
-
|
43
|
+
def target_feature_key(data)
|
44
|
+
data.value
|
45
45
|
end
|
46
46
|
|
47
47
|
private
|
@@ -100,8 +100,8 @@ RgGen.define_list_feature(:register_block, :protocol) do
|
|
100
100
|
end
|
101
101
|
|
102
102
|
factory do
|
103
|
-
def
|
104
|
-
|
103
|
+
def target_feature_key(configuration, _register_block)
|
104
|
+
configuration.protocol
|
105
105
|
end
|
106
106
|
end
|
107
107
|
end
|
metadata
CHANGED
@@ -1,14 +1,14 @@
|
|
1
1
|
--- !ruby/object:Gem::Specification
|
2
2
|
name: rggen-systemverilog
|
3
3
|
version: !ruby/object:Gem::Version
|
4
|
-
version: 0.
|
4
|
+
version: 0.16.0
|
5
5
|
platform: ruby
|
6
6
|
authors:
|
7
7
|
- Taichi Ishitani
|
8
8
|
autorequire:
|
9
9
|
bindir: bin
|
10
10
|
cert_chain: []
|
11
|
-
date: 2019-
|
11
|
+
date: 2019-10-01 00:00:00.000000000 Z
|
12
12
|
dependencies:
|
13
13
|
- !ruby/object:Gem::Dependency
|
14
14
|
name: docile
|
@@ -170,5 +170,5 @@ requirements: []
|
|
170
170
|
rubygems_version: 3.0.3
|
171
171
|
signing_key:
|
172
172
|
specification_version: 4
|
173
|
-
summary: rggen-systemverilog-0.
|
173
|
+
summary: rggen-systemverilog-0.16.0
|
174
174
|
test_files: []
|